drivers/clk/ux500/u8500_of_clk.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Clock definitions for u8500 platform.
   4  *
   5  * Copyright (C) 2012 ST-Ericsson SA
   6  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   7  */
   8
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/mfd/dbx500-prcmu.h>
  13 #include "clk.h"
  14
  15 #define PRCC_NUM_PERIPH_CLUSTERS 6
  16 #define PRCC_PERIPHS_PER_CLUSTER 32
  17
  18 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
  19 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  20 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  21
  22 #define PRCC_SHOW(clk, base, bit) \
  23         clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
  24 #define PRCC_PCLK_STORE(clk, base, bit) \
  25         prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  26 #define PRCC_KCLK_STORE(clk, base, bit)        \
  27         prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  28
  29 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
  30                                      void *data)
  31 {
  32         struct clk **clk_data = data;
  33         unsigned int base, bit;
  34
  35         if (clkspec->args_count != 2)
  36                 return  ERR_PTR(-EINVAL);
  37
  38         base = clkspec->args[0];
  39         bit = clkspec->args[1];
  40
  41         if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
  42                 pr_err("%s: invalid PRCC base %d\n", __func__, base);
  43                 return ERR_PTR(-EINVAL);
  44         }
  45
  46         return PRCC_SHOW(clk_data, base, bit);
  47 }
  48
  49 /* CLKRST4 is missing making it hard to index things */
  50 enum clkrst_index {
  51         CLKRST1_INDEX = 0,
  52         CLKRST2_INDEX,
  53         CLKRST3_INDEX,
  54         CLKRST5_INDEX,
  55         CLKRST6_INDEX,
  56         CLKRST_MAX,
  57 };
  58
  59 static void u8500_clk_init(struct device_node *np)
  60 {
  61         struct prcmu_fw_version *fw_version;
  62         struct device_node *child = NULL;
  63         const char *sgaclk_parent = NULL;
  64         struct clk *clk, *rtc_clk, *twd_clk;
  65         u32 bases[CLKRST_MAX];
  66         int i;
  67
  68         for (i = 0; i < ARRAY_SIZE(bases); i++) {
  69                 struct resource r;
  70
  71                 if (of_address_to_resource(np, i, &r))
  72                         /* Not much choice but to continue */
  73                         pr_err("failed to get CLKRST %d base address\n",
  74                                i + 1);
  75                 bases[i] = r.start;
  76         }
  77
  78         /* Clock sources */
  79         clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  80                                 CLK_IGNORE_UNUSED);
  81         prcmu_clk[PRCMU_PLLSOC0] = clk;
  82
  83         clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  84                                 CLK_IGNORE_UNUSED);
  85         prcmu_clk[PRCMU_PLLSOC1] = clk;
  86
  87         clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
  88                                 CLK_IGNORE_UNUSED);
  89         prcmu_clk[PRCMU_PLLDDR] = clk;
  90
  91         /* FIXME: Add sys, ulp and int clocks here. */
  92
  93         rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
  94                                 CLK_IGNORE_UNUSED,
  95                                 32768);
  96
  97         /* PRCMU clocks */
  98         fw_version = prcmu_get_fw_version();
  99         if (fw_version != NULL) {
 100                 switch (fw_version->project) {
 101                 case PRCMU_FW_PROJECT_U8500_C2:
 102                 case PRCMU_FW_PROJECT_U8500_MBL:
 103                 case PRCMU_FW_PROJECT_U8520:
 104                 case PRCMU_FW_PROJECT_U8420:
 105                 case PRCMU_FW_PROJECT_U8420_SYSCLK:
 106                         sgaclk_parent = "soc0_pll";
 107                         break;
 108                 default:
 109                         break;
 110                 }
 111         }
 112
 113         if (sgaclk_parent)
 114                 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
 115                                         PRCMU_SGACLK, 0);
 116         else
 117                 clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
 118         prcmu_clk[PRCMU_SGACLK] = clk;
 119
 120         clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
 121         prcmu_clk[PRCMU_UARTCLK] = clk;
 122
 123         clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
 124         prcmu_clk[PRCMU_MSP02CLK] = clk;
 125
 126         clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
 127         prcmu_clk[PRCMU_MSP1CLK] = clk;
 128
 129         clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
 130         prcmu_clk[PRCMU_I2CCLK] = clk;
 131
 132         clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
 133         prcmu_clk[PRCMU_SLIMCLK] = clk;
 134
 135         clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
 136         prcmu_clk[PRCMU_PER1CLK] = clk;
 137
 138         clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
 139         prcmu_clk[PRCMU_PER2CLK] = clk;
 140
 141         clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
 142         prcmu_clk[PRCMU_PER3CLK] = clk;
 143
 144         clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
 145         prcmu_clk[PRCMU_PER5CLK] = clk;
 146
 147         clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
 148         prcmu_clk[PRCMU_PER6CLK] = clk;
 149
 150         clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
 151         prcmu_clk[PRCMU_PER7CLK] = clk;
 152
 153         clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 154                                 CLK_SET_RATE_GATE);
 155         prcmu_clk[PRCMU_LCDCLK] = clk;
 156
 157         clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
 158         prcmu_clk[PRCMU_BMLCLK] = clk;
 159
 160         clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 161                                 CLK_SET_RATE_GATE);
 162         prcmu_clk[PRCMU_HSITXCLK] = clk;
 163
 164         clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
 165                                 CLK_SET_RATE_GATE);
 166         prcmu_clk[PRCMU_HSIRXCLK] = clk;
 167
 168         clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
 169                                 CLK_SET_RATE_GATE);
 170         prcmu_clk[PRCMU_HDMICLK] = clk;
 171
 172         clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
 173         prcmu_clk[PRCMU_APEATCLK] = clk;
 174
 175         clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
 176                                 CLK_SET_RATE_GATE);
 177         prcmu_clk[PRCMU_APETRACECLK] = clk;
 178
 179         clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
 180         prcmu_clk[PRCMU_MCDECLK] = clk;
 181
 182         clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
 183         prcmu_clk[PRCMU_IPI2CCLK] = clk;
 184
 185         clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
 186         prcmu_clk[PRCMU_DSIALTCLK] = clk;
 187
 188         clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
 189         prcmu_clk[PRCMU_DMACLK] = clk;
 190
 191         clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
 192         prcmu_clk[PRCMU_B2R2CLK] = clk;
 193
 194         clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 195                                 CLK_SET_RATE_GATE);
 196         prcmu_clk[PRCMU_TVCLK] = clk;
 197
 198         clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
 199         prcmu_clk[PRCMU_SSPCLK] = clk;
 200
 201         clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
 202         prcmu_clk[PRCMU_RNGCLK] = clk;
 203
 204         clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
 205         prcmu_clk[PRCMU_UICCCLK] = clk;
 206
 207         clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
 208         prcmu_clk[PRCMU_TIMCLK] = clk;
 209
 210         clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
 211         prcmu_clk[PRCMU_SYSCLK] = clk;
 212
 213         clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
 214                                         100000000, CLK_SET_RATE_GATE);
 215         prcmu_clk[PRCMU_SDMMCCLK] = clk;
 216
 217         clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 218                                 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 219         prcmu_clk[PRCMU_PLLDSI] = clk;
 220
 221         clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 222                                 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 223         prcmu_clk[PRCMU_DSI0CLK] = clk;
 224
 225         clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 226                                 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 227         prcmu_clk[PRCMU_DSI1CLK] = clk;
 228
 229         clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 230                                 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 231         prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
 232
 233         clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 234                                 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 235         prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
 236
 237         clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 238                                 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 239         prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
 240
 241         clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 242                                 PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
 243         prcmu_clk[PRCMU_ARMSS] = clk;
 244
 245         twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 246                                 CLK_IGNORE_UNUSED, 1, 2);
 247
 248         /*
 249          * FIXME: Add special handled PRCMU clocks here:
 250          * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
 251          * 2. ab9540_clkout1yuv, see clkout0yuv
 252          */
 253
 254         /* PRCC P-clocks */
 255         clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
 256                                 BIT(0), 0);
 257         PRCC_PCLK_STORE(clk, 1, 0);
 258
 259         clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
 260                                 BIT(1), 0);
 261         PRCC_PCLK_STORE(clk, 1, 1);
 262
 263         clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
 264                                 BIT(2), 0);
 265         PRCC_PCLK_STORE(clk, 1, 2);
 266
 267         clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
 268                                 BIT(3), 0);
 269         PRCC_PCLK_STORE(clk, 1, 3);
 270
 271         clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
 272                                 BIT(4), 0);
 273         PRCC_PCLK_STORE(clk, 1, 4);
 274
 275         clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
 276                                 BIT(5), 0);
 277         PRCC_PCLK_STORE(clk, 1, 5);
 278
 279         clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
 280                                 BIT(6), 0);
 281         PRCC_PCLK_STORE(clk, 1, 6);
 282
 283         clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
 284                                 BIT(7), 0);
 285         PRCC_PCLK_STORE(clk, 1, 7);
 286
 287         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
 288                                 BIT(8), 0);
 289         PRCC_PCLK_STORE(clk, 1, 8);
 290
 291         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
 292                                 BIT(9), 0);
 293         PRCC_PCLK_STORE(clk, 1, 9);
 294
 295         clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
 296                                 BIT(10), 0);
 297         PRCC_PCLK_STORE(clk, 1, 10);
 298
 299         clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
 300                                 BIT(11), 0);
 301         PRCC_PCLK_STORE(clk, 1, 11);
 302
 303         clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
 304                                 BIT(0), 0);
 305         PRCC_PCLK_STORE(clk, 2, 0);
 306
 307         clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
 308                                 BIT(1), 0);
 309         PRCC_PCLK_STORE(clk, 2, 1);
 310
 311         clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
 312                                 BIT(2), 0);
 313         PRCC_PCLK_STORE(clk, 2, 2);
 314
 315         clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
 316                                 BIT(3), 0);
 317         PRCC_PCLK_STORE(clk, 2, 3);
 318
 319         clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
 320                                 BIT(4), 0);
 321         PRCC_PCLK_STORE(clk, 2, 4);
 322
 323         clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
 324                                 BIT(5), 0);
 325         PRCC_PCLK_STORE(clk, 2, 5);
 326
 327         clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
 328                                 BIT(6), 0);
 329         PRCC_PCLK_STORE(clk, 2, 6);
 330
 331         clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
 332                                 BIT(7), 0);
 333         PRCC_PCLK_STORE(clk, 2, 7);
 334
 335         clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
 336                                 BIT(8), 0);
 337         PRCC_PCLK_STORE(clk, 2, 8);
 338
 339         clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
 340                                 BIT(9), 0);
 341         PRCC_PCLK_STORE(clk, 2, 9);
 342
 343         clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
 344                                 BIT(10), 0);
 345         PRCC_PCLK_STORE(clk, 2, 10);
 346
 347         clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
 348                                 BIT(11), 0);
 349         PRCC_PCLK_STORE(clk, 2, 11);
 350
 351         clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
 352                                 BIT(12), 0);
 353         PRCC_PCLK_STORE(clk, 2, 12);
 354
 355         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
 356                                 BIT(0), 0);
 357         PRCC_PCLK_STORE(clk, 3, 0);
 358
 359         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
 360                                 BIT(1), 0);
 361         PRCC_PCLK_STORE(clk, 3, 1);
 362
 363         clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
 364                                 BIT(2), 0);
 365         PRCC_PCLK_STORE(clk, 3, 2);
 366
 367         clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
 368                                 BIT(3), 0);
 369         PRCC_PCLK_STORE(clk, 3, 3);
 370
 371         clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
 372                                 BIT(4), 0);
 373         PRCC_PCLK_STORE(clk, 3, 4);
 374
 375         clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
 376                                 BIT(5), 0);
 377         PRCC_PCLK_STORE(clk, 3, 5);
 378
 379         clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
 380                                 BIT(6), 0);
 381         PRCC_PCLK_STORE(clk, 3, 6);
 382
 383         clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
 384                                 BIT(7), 0);
 385         PRCC_PCLK_STORE(clk, 3, 7);
 386
 387         clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
 388                                 BIT(8), 0);
 389         PRCC_PCLK_STORE(clk, 3, 8);
 390
 391         clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
 392                                 BIT(0), 0);
 393         PRCC_PCLK_STORE(clk, 5, 0);
 394
 395         clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
 396                                 BIT(1), 0);
 397         PRCC_PCLK_STORE(clk, 5, 1);
 398
 399         clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
 400                                 BIT(0), 0);
 401         PRCC_PCLK_STORE(clk, 6, 0);
 402
 403         clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
 404                                 BIT(1), 0);
 405         PRCC_PCLK_STORE(clk, 6, 1);
 406
 407         clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
 408                                 BIT(2), 0);
 409         PRCC_PCLK_STORE(clk, 6, 2);
 410
 411         clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
 412                                 BIT(3), 0);
 413         PRCC_PCLK_STORE(clk, 6, 3);
 414
 415         clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
 416                                 BIT(4), 0);
 417         PRCC_PCLK_STORE(clk, 6, 4);
 418
 419         clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
 420                                 BIT(5), 0);
 421         PRCC_PCLK_STORE(clk, 6, 5);
 422
 423         clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
 424                                 BIT(6), 0);
 425         PRCC_PCLK_STORE(clk, 6, 6);
 426
 427         clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
 428                                 BIT(7), 0);
 429         PRCC_PCLK_STORE(clk, 6, 7);
 430
 431         /* PRCC K-clocks
 432          *
 433          * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
 434          * by enabling just the K-clock, even if it is not a valid parent to
 435          * the K-clock. Until drivers get fixed we might need some kind of
 436          * "parent muxed join".
 437          */
 438
 439         /* Periph1 */
 440         clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 441                         bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
 442         PRCC_KCLK_STORE(clk, 1, 0);
 443
 444         clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 445                         bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
 446         PRCC_KCLK_STORE(clk, 1, 1);
 447
 448         clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 449                         bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
 450         PRCC_KCLK_STORE(clk, 1, 2);
 451
 452         clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 453                         bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
 454         PRCC_KCLK_STORE(clk, 1, 3);
 455
 456         clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 457                         bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
 458         PRCC_KCLK_STORE(clk, 1, 4);
 459
 460         clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 461                         bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
 462         PRCC_KCLK_STORE(clk, 1, 5);
 463
 464         clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 465                         bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
 466         PRCC_KCLK_STORE(clk, 1, 6);
 467
 468         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 469                         bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
 470         PRCC_KCLK_STORE(clk, 1, 8);
 471
 472         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 473                         bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
 474         PRCC_KCLK_STORE(clk, 1, 9);
 475
 476         clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 477                         bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
 478         PRCC_KCLK_STORE(clk, 1, 10);
 479
 480         /* Periph2 */
 481         clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 482                         bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
 483         PRCC_KCLK_STORE(clk, 2, 0);
 484
 485         clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 486                         bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
 487         PRCC_KCLK_STORE(clk, 2, 2);
 488
 489         clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 490                         bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
 491         PRCC_KCLK_STORE(clk, 2, 3);
 492
 493         clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 494                         bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
 495         PRCC_KCLK_STORE(clk, 2, 4);
 496
 497         clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 498                         bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
 499         PRCC_KCLK_STORE(clk, 2, 5);
 500
 501         /* Note that rate is received from parent. */
 502         clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 503                         bases[CLKRST2_INDEX], BIT(6),
 504                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 505         PRCC_KCLK_STORE(clk, 2, 6);
 506
 507         clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 508                         bases[CLKRST2_INDEX], BIT(7),
 509                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 510         PRCC_KCLK_STORE(clk, 2, 7);
 511
 512         /* Periph3 */
 513         clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 514                         bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
 515         PRCC_KCLK_STORE(clk, 3, 1);
 516
 517         clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 518                         bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
 519         PRCC_KCLK_STORE(clk, 3, 2);
 520
 521         clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 522                         bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
 523         PRCC_KCLK_STORE(clk, 3, 3);
 524
 525         clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 526                         bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
 527         PRCC_KCLK_STORE(clk, 3, 4);
 528
 529         clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 530                         bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
 531         PRCC_KCLK_STORE(clk, 3, 5);
 532
 533         clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 534                         bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
 535         PRCC_KCLK_STORE(clk, 3, 6);
 536
 537         clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 538                         bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
 539         PRCC_KCLK_STORE(clk, 3, 7);
 540
 541         /* Periph6 */
 542         clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
 543                         bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
 544         PRCC_KCLK_STORE(clk, 6, 0);
 545
 546         for_each_child_of_node(np, child) {
 547                 static struct clk_onecell_data clk_data;
 548
 549                 if (of_node_name_eq(child, "prcmu-clock")) {
 550                         clk_data.clks = prcmu_clk;
 551                         clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
 552                         of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
 553                 }
 554                 if (of_node_name_eq(child, "prcc-periph-clock"))
 555                         of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
 556
 557                 if (of_node_name_eq(child, "prcc-kernel-clock"))
 558                         of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
 559
 560                 if (of_node_name_eq(child, "rtc32k-clock"))
 561                         of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
 562
 563                 if (of_node_name_eq(child, "smp-twd-clock"))
 564                         of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
 565         }
 566 }
 567 CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init);