1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_
4 #define _ICP_QAT_FW_INIT_ADMIN_H_
6 #include "icp_qat_fw.h"
8 enum icp_qat_fw_init_admin_cmd_id
{
9 ICP_QAT_FW_INIT_AE
= 0,
10 ICP_QAT_FW_TRNG_ENABLE
= 1,
11 ICP_QAT_FW_TRNG_DISABLE
= 2,
12 ICP_QAT_FW_CONSTANTS_CFG
= 3,
13 ICP_QAT_FW_STATUS_GET
= 4,
14 ICP_QAT_FW_COUNTERS_GET
= 5,
15 ICP_QAT_FW_LOOPBACK
= 6,
16 ICP_QAT_FW_HEARTBEAT_SYNC
= 7,
17 ICP_QAT_FW_HEARTBEAT_GET
= 8
20 enum icp_qat_fw_init_admin_resp_status
{
21 ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS
= 0,
22 ICP_QAT_FW_INIT_RESP_STATUS_FAIL
25 struct icp_qat_fw_init_admin_req
{
35 __u16 ibuf_size_in_kb
;
44 struct icp_qat_fw_init_admin_resp
{
52 __u16 version_minor_num
;
53 __u16 version_major_num
;
58 __u32 resrvd3
[ICP_QAT_FW_NUM_LONGWORDS_4
];
60 __u32 version_patch_num
;
68 __u64 resp_sent_count
;
71 __u16 compression_algos
;
73 __u32 deflate_capabilities
;
75 __u32 lzs_capabilities
;
82 __u16 public_key_algos
;
90 __u32 successful_count
;
91 __u32 unsuccessful_count
;
97 #define ICP_QAT_FW_COMN_HEARTBEAT_OK 0
98 #define ICP_QAT_FW_COMN_HEARTBEAT_BLOCKED 1
99 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS 0
100 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK 0x1
101 #define ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE
102 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_GET(hdr_t) \
103 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(hdr_t.flags)
105 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val) \
106 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val)
108 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(flags) \
109 QAT_FIELD_GET(flags, \
110 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS, \
111 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK)