drivers/crypto/qat/qat_common/icp_qat_hw.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
   2 /* Copyright(c) 2014 - 2020 Intel Corporation */
   3 #ifndef _ICP_QAT_HW_H_
   4 #define _ICP_QAT_HW_H_
   5
   6 enum icp_qat_hw_ae_id {
   7         ICP_QAT_HW_AE_0 = 0,
   8         ICP_QAT_HW_AE_1 = 1,
   9         ICP_QAT_HW_AE_2 = 2,
  10         ICP_QAT_HW_AE_3 = 3,
  11         ICP_QAT_HW_AE_4 = 4,
  12         ICP_QAT_HW_AE_5 = 5,
  13         ICP_QAT_HW_AE_6 = 6,
  14         ICP_QAT_HW_AE_7 = 7,
  15         ICP_QAT_HW_AE_8 = 8,
  16         ICP_QAT_HW_AE_9 = 9,
  17         ICP_QAT_HW_AE_10 = 10,
  18         ICP_QAT_HW_AE_11 = 11,
  19         ICP_QAT_HW_AE_DELIMITER = 12
  20 };
  21
  22 enum icp_qat_hw_qat_id {
  23         ICP_QAT_HW_QAT_0 = 0,
  24         ICP_QAT_HW_QAT_1 = 1,
  25         ICP_QAT_HW_QAT_2 = 2,
  26         ICP_QAT_HW_QAT_3 = 3,
  27         ICP_QAT_HW_QAT_4 = 4,
  28         ICP_QAT_HW_QAT_5 = 5,
  29         ICP_QAT_HW_QAT_DELIMITER = 6
  30 };
  31
  32 enum icp_qat_hw_auth_algo {
  33         ICP_QAT_HW_AUTH_ALGO_NULL = 0,
  34         ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
  35         ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
  36         ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
  37         ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
  38         ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
  39         ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
  40         ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
  41         ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
  42         ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
  43         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
  44         ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
  45         ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
  46         ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
  47         ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
  48         ICP_QAT_HW_AUTH_RESERVED_1 = 15,
  49         ICP_QAT_HW_AUTH_RESERVED_2 = 16,
  50         ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
  51         ICP_QAT_HW_AUTH_RESERVED_3 = 18,
  52         ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
  53         ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
  54 };
  55
  56 enum icp_qat_hw_auth_mode {
  57         ICP_QAT_HW_AUTH_MODE0 = 0,
  58         ICP_QAT_HW_AUTH_MODE1 = 1,
  59         ICP_QAT_HW_AUTH_MODE2 = 2,
  60         ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
  61 };
  62
  63 struct icp_qat_hw_auth_config {
  64         __u32 config;
  65         __u32 reserved;
  66 };
  67
  68 struct icp_qat_hw_ucs_cipher_config {
  69         __u32 val;
  70         __u32 reserved[3];
  71 };
  72
  73 enum icp_qat_slice_mask {
  74         ICP_ACCEL_MASK_CIPHER_SLICE = BIT(0),
  75         ICP_ACCEL_MASK_AUTH_SLICE = BIT(1),
  76         ICP_ACCEL_MASK_PKE_SLICE = BIT(2),
  77         ICP_ACCEL_MASK_COMPRESS_SLICE = BIT(3),
  78         ICP_ACCEL_MASK_LZS_SLICE = BIT(4),
  79         ICP_ACCEL_MASK_EIA3_SLICE = BIT(5),
  80         ICP_ACCEL_MASK_SHA3_SLICE = BIT(6),
  81 };
  82
  83 enum icp_qat_capabilities_mask {
  84         ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
  85         ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
  86         ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
  87         ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
  88         ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
  89         ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
  90         ICP_ACCEL_CAPABILITIES_LZS_COMPRESSION = BIT(6),
  91         ICP_ACCEL_CAPABILITIES_RAND = BIT(7),
  92         ICP_ACCEL_CAPABILITIES_ZUC = BIT(8),
  93         ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9),
  94         /* Bits 10-25 are currently reserved */
  95         ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26)
  96 };
  97
  98 #define QAT_AUTH_MODE_BITPOS 4
  99 #define QAT_AUTH_MODE_MASK 0xF
 100 #define QAT_AUTH_ALGO_BITPOS 0
 101 #define QAT_AUTH_ALGO_MASK 0xF
 102 #define QAT_AUTH_CMP_BITPOS 8
 103 #define QAT_AUTH_CMP_MASK 0x7F
 104 #define QAT_AUTH_SHA3_PADDING_BITPOS 16
 105 #define QAT_AUTH_SHA3_PADDING_MASK 0x1
 106 #define QAT_AUTH_ALGO_SHA3_BITPOS 22
 107 #define QAT_AUTH_ALGO_SHA3_MASK 0x3
 108 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
 109         (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
 110         ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
 111         (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
 112          QAT_AUTH_ALGO_SHA3_BITPOS) | \
 113          (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
 114         (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
 115         & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
 116         ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
 117
 118 struct icp_qat_hw_auth_counter {
 119         __be32 counter;
 120         __u32 reserved;
 121 };
 122
 123 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
 124 #define QAT_AUTH_COUNT_BITPOS 0
 125 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
 126         (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
 127
 128 struct icp_qat_hw_auth_setup {
 129         struct icp_qat_hw_auth_config auth_config;
 130         struct icp_qat_hw_auth_counter auth_counter;
 131 };
 132
 133 #define QAT_HW_DEFAULT_ALIGNMENT 8
 134 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
 135 #define ICP_QAT_HW_NULL_STATE1_SZ 32
 136 #define ICP_QAT_HW_MD5_STATE1_SZ 16
 137 #define ICP_QAT_HW_SHA1_STATE1_SZ 20
 138 #define ICP_QAT_HW_SHA224_STATE1_SZ 32
 139 #define ICP_QAT_HW_SHA256_STATE1_SZ 32
 140 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
 141 #define ICP_QAT_HW_SHA384_STATE1_SZ 64
 142 #define ICP_QAT_HW_SHA512_STATE1_SZ 64
 143 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
 144 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
 145 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
 146 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
 147 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
 148 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32
 149 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
 150 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
 151 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
 152 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
 153 #define ICP_QAT_HW_NULL_STATE2_SZ 32
 154 #define ICP_QAT_HW_MD5_STATE2_SZ 16
 155 #define ICP_QAT_HW_SHA1_STATE2_SZ 20
 156 #define ICP_QAT_HW_SHA224_STATE2_SZ 32
 157 #define ICP_QAT_HW_SHA256_STATE2_SZ 32
 158 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
 159 #define ICP_QAT_HW_SHA384_STATE2_SZ 64
 160 #define ICP_QAT_HW_SHA512_STATE2_SZ 64
 161 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
 162 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
 163 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
 164 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
 165 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
 166 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
 167 #define ICP_QAT_HW_F9_IK_SZ 16
 168 #define ICP_QAT_HW_F9_FK_SZ 16
 169 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
 170         ICP_QAT_HW_F9_FK_SZ)
 171 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
 172 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
 173 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
 174 #define ICP_QAT_HW_GALOIS_H_SZ 16
 175 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
 176 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
 177
 178 struct icp_qat_hw_auth_sha512 {
 179         struct icp_qat_hw_auth_setup inner_setup;
 180         __u8 state1[ICP_QAT_HW_SHA512_STATE1_SZ];
 181         struct icp_qat_hw_auth_setup outer_setup;
 182         __u8 state2[ICP_QAT_HW_SHA512_STATE2_SZ];
 183 };
 184
 185 struct icp_qat_hw_auth_algo_blk {
 186         struct icp_qat_hw_auth_sha512 sha;
 187 };
 188
 189 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
 190 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
 191
 192 enum icp_qat_hw_cipher_algo {
 193         ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
 194         ICP_QAT_HW_CIPHER_ALGO_DES = 1,
 195         ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
 196         ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
 197         ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
 198         ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
 199         ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
 200         ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
 201         ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
 202         ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
 203         ICP_QAT_HW_CIPHER_DELIMITER = 10
 204 };
 205
 206 enum icp_qat_hw_cipher_mode {
 207         ICP_QAT_HW_CIPHER_ECB_MODE = 0,
 208         ICP_QAT_HW_CIPHER_CBC_MODE = 1,
 209         ICP_QAT_HW_CIPHER_CTR_MODE = 2,
 210         ICP_QAT_HW_CIPHER_F8_MODE = 3,
 211         ICP_QAT_HW_CIPHER_XTS_MODE = 6,
 212         ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
 213 };
 214
 215 struct icp_qat_hw_cipher_config {
 216         __u32 val;
 217         __u32 reserved;
 218 };
 219
 220 enum icp_qat_hw_cipher_dir {
 221         ICP_QAT_HW_CIPHER_ENCRYPT = 0,
 222         ICP_QAT_HW_CIPHER_DECRYPT = 1,
 223 };
 224
 225 enum icp_qat_hw_cipher_convert {
 226         ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
 227         ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
 228 };
 229
 230 #define QAT_CIPHER_MODE_BITPOS 4
 231 #define QAT_CIPHER_MODE_MASK 0xF
 232 #define QAT_CIPHER_ALGO_BITPOS 0
 233 #define QAT_CIPHER_ALGO_MASK 0xF
 234 #define QAT_CIPHER_CONVERT_BITPOS 9
 235 #define QAT_CIPHER_CONVERT_MASK 0x1
 236 #define QAT_CIPHER_DIR_BITPOS 8
 237 #define QAT_CIPHER_DIR_MASK 0x1
 238 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
 239 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
 240 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
 241         (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
 242         ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
 243         ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
 244         ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
 245 #define ICP_QAT_HW_DES_BLK_SZ 8
 246 #define ICP_QAT_HW_3DES_BLK_SZ 8
 247 #define ICP_QAT_HW_NULL_BLK_SZ 8
 248 #define ICP_QAT_HW_AES_BLK_SZ 16
 249 #define ICP_QAT_HW_KASUMI_BLK_SZ 8
 250 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
 251 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
 252 #define ICP_QAT_HW_NULL_KEY_SZ 256
 253 #define ICP_QAT_HW_DES_KEY_SZ 8
 254 #define ICP_QAT_HW_3DES_KEY_SZ 24
 255 #define ICP_QAT_HW_AES_128_KEY_SZ 16
 256 #define ICP_QAT_HW_AES_192_KEY_SZ 24
 257 #define ICP_QAT_HW_AES_256_KEY_SZ 32
 258 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
 259         QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
 260 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
 261         QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
 262 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
 263         QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
 264 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
 265         QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
 266 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
 267         QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
 268 #define ICP_QAT_HW_KASUMI_KEY_SZ 16
 269 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
 270         QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
 271 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
 272         QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
 273 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
 274         QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
 275 #define ICP_QAT_HW_ARC4_KEY_SZ 256
 276 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
 277 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
 278 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
 279 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
 280 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
 281 #define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024
 282
 283 struct icp_qat_hw_cipher_aes256_f8 {
 284         struct icp_qat_hw_cipher_config cipher_config;
 285         __u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
 286 };
 287
 288 struct icp_qat_hw_ucs_cipher_aes256_f8 {
 289         struct icp_qat_hw_ucs_cipher_config cipher_config;
 290         __u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
 291 };
 292
 293 struct icp_qat_hw_cipher_algo_blk {
 294         union {
 295                 struct icp_qat_hw_cipher_aes256_f8 aes;
 296                 struct icp_qat_hw_ucs_cipher_aes256_f8 ucs_aes;
 297         };
 298 } __aligned(64);
 299 #endif