1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
5 #include <linux/bits.h>
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/slab.h>
14 #define PCH_EDGE_FALLING 0
15 #define PCH_EDGE_RISING 1
18 #define PCH_EDGE_BOTH 4
19 #define PCH_IM_MASK GENMASK(2, 0)
21 #define PCH_IRQ_BASE 24
42 OKISEMI_ML7223m_IOH
, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
43 OKISEMI_ML7223n_IOH
/* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
46 /* Specifies number of GPIO PINS */
47 static int gpio_pins
[] = {
48 [INTEL_EG20T_PCH
] = 12,
49 [OKISEMI_ML7223m_IOH
] = 8,
50 [OKISEMI_ML7223n_IOH
] = 8,
54 * struct pch_gpio_reg_data - The register store data.
55 * @ien_reg: To store contents of IEN register.
56 * @imask_reg: To store contents of IMASK register.
57 * @po_reg: To store contents of PO register.
58 * @pm_reg: To store contents of PM register.
59 * @im0_reg: To store contents of IM0 register.
60 * @im1_reg: To store contents of IM1 register.
61 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
64 struct pch_gpio_reg_data
{
75 * struct pch_gpio - GPIO private data structure.
76 * @base: PCI base address of Memory mapped I/O register.
77 * @reg: Memory mapped PCH GPIO register list.
78 * @dev: Pointer to device structure.
79 * @gpio: Data for GPIO infrastructure.
80 * @pch_gpio_reg: Memory mapped Register data is saved here
82 * @lock: Used for register access protection
83 * @irq_base: Save base of IRQ number for interrupt
85 * @spinlock: Used for register access protection
89 struct pch_regs __iomem
*reg
;
91 struct gpio_chip gpio
;
92 struct pch_gpio_reg_data pch_gpio_reg
;
98 static void pch_gpio_set(struct gpio_chip
*gpio
, unsigned int nr
, int val
)
101 struct pch_gpio
*chip
= gpiochip_get_data(gpio
);
104 spin_lock_irqsave(&chip
->spinlock
, flags
);
105 reg_val
= ioread32(&chip
->reg
->po
);
111 iowrite32(reg_val
, &chip
->reg
->po
);
112 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
115 static int pch_gpio_get(struct gpio_chip
*gpio
, unsigned int nr
)
117 struct pch_gpio
*chip
= gpiochip_get_data(gpio
);
119 return !!(ioread32(&chip
->reg
->pi
) & BIT(nr
));
122 static int pch_gpio_direction_output(struct gpio_chip
*gpio
, unsigned int nr
,
125 struct pch_gpio
*chip
= gpiochip_get_data(gpio
);
130 spin_lock_irqsave(&chip
->spinlock
, flags
);
132 reg_val
= ioread32(&chip
->reg
->po
);
137 iowrite32(reg_val
, &chip
->reg
->po
);
139 pm
= ioread32(&chip
->reg
->pm
);
140 pm
&= BIT(gpio_pins
[chip
->ioh
]) - 1;
142 iowrite32(pm
, &chip
->reg
->pm
);
144 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
149 static int pch_gpio_direction_input(struct gpio_chip
*gpio
, unsigned int nr
)
151 struct pch_gpio
*chip
= gpiochip_get_data(gpio
);
155 spin_lock_irqsave(&chip
->spinlock
, flags
);
156 pm
= ioread32(&chip
->reg
->pm
);
157 pm
&= BIT(gpio_pins
[chip
->ioh
]) - 1;
159 iowrite32(pm
, &chip
->reg
->pm
);
160 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
166 * Save register configuration and disable interrupts.
168 static void __maybe_unused
pch_gpio_save_reg_conf(struct pch_gpio
*chip
)
170 chip
->pch_gpio_reg
.ien_reg
= ioread32(&chip
->reg
->ien
);
171 chip
->pch_gpio_reg
.imask_reg
= ioread32(&chip
->reg
->imask
);
172 chip
->pch_gpio_reg
.po_reg
= ioread32(&chip
->reg
->po
);
173 chip
->pch_gpio_reg
.pm_reg
= ioread32(&chip
->reg
->pm
);
174 chip
->pch_gpio_reg
.im0_reg
= ioread32(&chip
->reg
->im0
);
175 if (chip
->ioh
== INTEL_EG20T_PCH
)
176 chip
->pch_gpio_reg
.im1_reg
= ioread32(&chip
->reg
->im1
);
177 if (chip
->ioh
== OKISEMI_ML7223n_IOH
)
178 chip
->pch_gpio_reg
.gpio_use_sel_reg
= ioread32(&chip
->reg
->gpio_use_sel
);
182 * This function restores the register configuration of the GPIO device.
184 static void __maybe_unused
pch_gpio_restore_reg_conf(struct pch_gpio
*chip
)
186 iowrite32(chip
->pch_gpio_reg
.ien_reg
, &chip
->reg
->ien
);
187 iowrite32(chip
->pch_gpio_reg
.imask_reg
, &chip
->reg
->imask
);
188 /* to store contents of PO register */
189 iowrite32(chip
->pch_gpio_reg
.po_reg
, &chip
->reg
->po
);
190 /* to store contents of PM register */
191 iowrite32(chip
->pch_gpio_reg
.pm_reg
, &chip
->reg
->pm
);
192 iowrite32(chip
->pch_gpio_reg
.im0_reg
, &chip
->reg
->im0
);
193 if (chip
->ioh
== INTEL_EG20T_PCH
)
194 iowrite32(chip
->pch_gpio_reg
.im1_reg
, &chip
->reg
->im1
);
195 if (chip
->ioh
== OKISEMI_ML7223n_IOH
)
196 iowrite32(chip
->pch_gpio_reg
.gpio_use_sel_reg
, &chip
->reg
->gpio_use_sel
);
199 static int pch_gpio_to_irq(struct gpio_chip
*gpio
, unsigned int offset
)
201 struct pch_gpio
*chip
= gpiochip_get_data(gpio
);
203 return chip
->irq_base
+ offset
;
206 static void pch_gpio_setup(struct pch_gpio
*chip
)
208 struct gpio_chip
*gpio
= &chip
->gpio
;
210 gpio
->label
= dev_name(chip
->dev
);
211 gpio
->parent
= chip
->dev
;
212 gpio
->owner
= THIS_MODULE
;
213 gpio
->direction_input
= pch_gpio_direction_input
;
214 gpio
->get
= pch_gpio_get
;
215 gpio
->direction_output
= pch_gpio_direction_output
;
216 gpio
->set
= pch_gpio_set
;
218 gpio
->ngpio
= gpio_pins
[chip
->ioh
];
219 gpio
->can_sleep
= false;
220 gpio
->to_irq
= pch_gpio_to_irq
;
223 static int pch_irq_type(struct irq_data
*d
, unsigned int type
)
225 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
226 struct pch_gpio
*chip
= gc
->private;
230 int ch
, irq
= d
->irq
;
232 ch
= irq
- chip
->irq_base
;
233 if (irq
< chip
->irq_base
+ 8) {
234 im_reg
= &chip
->reg
->im0
;
237 im_reg
= &chip
->reg
->im1
;
240 dev_dbg(chip
->dev
, "irq=%d type=%d ch=%d pos=%d\n", irq
, type
, ch
, im_pos
);
243 case IRQ_TYPE_EDGE_RISING
:
244 val
= PCH_EDGE_RISING
;
246 case IRQ_TYPE_EDGE_FALLING
:
247 val
= PCH_EDGE_FALLING
;
249 case IRQ_TYPE_EDGE_BOTH
:
252 case IRQ_TYPE_LEVEL_HIGH
:
255 case IRQ_TYPE_LEVEL_LOW
:
262 spin_lock_irqsave(&chip
->spinlock
, flags
);
264 /* Set interrupt mode */
265 im
= ioread32(im_reg
) & ~(PCH_IM_MASK
<< (im_pos
* 4));
266 iowrite32(im
| (val
<< (im_pos
* 4)), im_reg
);
268 /* And the handler */
269 if (type
& IRQ_TYPE_LEVEL_MASK
)
270 irq_set_handler_locked(d
, handle_level_irq
);
271 else if (type
& IRQ_TYPE_EDGE_BOTH
)
272 irq_set_handler_locked(d
, handle_edge_irq
);
274 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
278 static void pch_irq_unmask(struct irq_data
*d
)
280 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
281 struct pch_gpio
*chip
= gc
->private;
283 iowrite32(BIT(d
->irq
- chip
->irq_base
), &chip
->reg
->imaskclr
);
286 static void pch_irq_mask(struct irq_data
*d
)
288 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
289 struct pch_gpio
*chip
= gc
->private;
291 iowrite32(BIT(d
->irq
- chip
->irq_base
), &chip
->reg
->imask
);
294 static void pch_irq_ack(struct irq_data
*d
)
296 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
297 struct pch_gpio
*chip
= gc
->private;
299 iowrite32(BIT(d
->irq
- chip
->irq_base
), &chip
->reg
->iclr
);
302 static irqreturn_t
pch_gpio_handler(int irq
, void *dev_id
)
304 struct pch_gpio
*chip
= dev_id
;
305 unsigned long reg_val
= ioread32(&chip
->reg
->istatus
);
308 dev_vdbg(chip
->dev
, "irq=%d status=0x%lx\n", irq
, reg_val
);
310 reg_val
&= BIT(gpio_pins
[chip
->ioh
]) - 1;
312 for_each_set_bit(i
, ®_val
, gpio_pins
[chip
->ioh
])
313 generic_handle_irq(chip
->irq_base
+ i
);
315 return IRQ_RETVAL(reg_val
);
318 static int pch_gpio_alloc_generic_chip(struct pch_gpio
*chip
,
319 unsigned int irq_start
,
322 struct irq_chip_generic
*gc
;
323 struct irq_chip_type
*ct
;
326 gc
= devm_irq_alloc_generic_chip(chip
->dev
, "pch_gpio", 1, irq_start
,
327 chip
->base
, handle_simple_irq
);
334 ct
->chip
.irq_ack
= pch_irq_ack
;
335 ct
->chip
.irq_mask
= pch_irq_mask
;
336 ct
->chip
.irq_unmask
= pch_irq_unmask
;
337 ct
->chip
.irq_set_type
= pch_irq_type
;
339 rv
= devm_irq_setup_generic_chip(chip
->dev
, gc
, IRQ_MSK(num
),
340 IRQ_GC_INIT_MASK_CACHE
,
341 IRQ_NOREQUEST
| IRQ_NOPROBE
, 0);
346 static int pch_gpio_probe(struct pci_dev
*pdev
,
347 const struct pci_device_id
*id
)
350 struct pch_gpio
*chip
;
353 chip
= devm_kzalloc(&pdev
->dev
, sizeof(*chip
), GFP_KERNEL
);
357 chip
->dev
= &pdev
->dev
;
358 ret
= pcim_enable_device(pdev
);
360 dev_err(&pdev
->dev
, "pci_enable_device FAILED");
364 ret
= pcim_iomap_regions(pdev
, BIT(1), KBUILD_MODNAME
);
366 dev_err(&pdev
->dev
, "pci_request_regions FAILED-%d", ret
);
370 chip
->base
= pcim_iomap_table(pdev
)[1];
372 if (pdev
->device
== 0x8803)
373 chip
->ioh
= INTEL_EG20T_PCH
;
374 else if (pdev
->device
== 0x8014)
375 chip
->ioh
= OKISEMI_ML7223m_IOH
;
376 else if (pdev
->device
== 0x8043)
377 chip
->ioh
= OKISEMI_ML7223n_IOH
;
379 chip
->reg
= chip
->base
;
380 pci_set_drvdata(pdev
, chip
);
381 spin_lock_init(&chip
->spinlock
);
382 pch_gpio_setup(chip
);
384 ret
= devm_gpiochip_add_data(&pdev
->dev
, &chip
->gpio
, chip
);
386 dev_err(&pdev
->dev
, "PCH gpio: Failed to register GPIO\n");
390 irq_base
= devm_irq_alloc_descs(&pdev
->dev
, -1, 0,
391 gpio_pins
[chip
->ioh
], NUMA_NO_NODE
);
393 dev_warn(&pdev
->dev
, "PCH gpio: Failed to get IRQ base num\n");
397 chip
->irq_base
= irq_base
;
399 /* Mask all interrupts, but enable them */
400 iowrite32(BIT(gpio_pins
[chip
->ioh
]) - 1, &chip
->reg
->imask
);
401 iowrite32(BIT(gpio_pins
[chip
->ioh
]) - 1, &chip
->reg
->ien
);
403 ret
= devm_request_irq(&pdev
->dev
, pdev
->irq
, pch_gpio_handler
,
404 IRQF_SHARED
, KBUILD_MODNAME
, chip
);
406 dev_err(&pdev
->dev
, "request_irq failed\n");
410 return pch_gpio_alloc_generic_chip(chip
, irq_base
, gpio_pins
[chip
->ioh
]);
413 static int __maybe_unused
pch_gpio_suspend(struct device
*dev
)
415 struct pch_gpio
*chip
= dev_get_drvdata(dev
);
418 spin_lock_irqsave(&chip
->spinlock
, flags
);
419 pch_gpio_save_reg_conf(chip
);
420 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
425 static int __maybe_unused
pch_gpio_resume(struct device
*dev
)
427 struct pch_gpio
*chip
= dev_get_drvdata(dev
);
430 spin_lock_irqsave(&chip
->spinlock
, flags
);
431 iowrite32(0x01, &chip
->reg
->reset
);
432 iowrite32(0x00, &chip
->reg
->reset
);
433 pch_gpio_restore_reg_conf(chip
);
434 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
439 static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops
, pch_gpio_suspend
, pch_gpio_resume
);
441 static const struct pci_device_id pch_gpio_pcidev_id
[] = {
442 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8803) },
443 { PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8014) },
444 { PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8043) },
445 { PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8803) },
448 MODULE_DEVICE_TABLE(pci
, pch_gpio_pcidev_id
);
450 static struct pci_driver pch_gpio_driver
= {
452 .id_table
= pch_gpio_pcidev_id
,
453 .probe
= pch_gpio_probe
,
455 .pm
= &pch_gpio_pm_ops
,
459 module_pci_driver(pch_gpio_driver
);
461 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
462 MODULE_LICENSE("GPL v2");