drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __AMDGPU_DM_H__
  27 #define __AMDGPU_DM_H__
  28
  29 #include <drm/drm_atomic.h>
  30 #include <drm/drm_connector.h>
  31 #include <drm/drm_crtc.h>
  32 #include <drm/drm_dp_mst_helper.h>
  33 #include <drm/drm_plane.h>
  34
  35 /*
  36  * This file contains the definition for amdgpu_display_manager
  37  * and its API for amdgpu driver's use.
  38  * This component provides all the display related functionality
  39  * and this is the only component that calls DAL API.
  40  * The API contained here intended for amdgpu driver use.
  41  * The API that is called directly from KMS framework is located
  42  * in amdgpu_dm_kms.h file
  43  */
  44
  45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
  46
  47 #define AMDGPU_DM_MAX_CRTC 6
  48
  49 /*
  50 #include "include/amdgpu_dal_power_if.h"
  51 #include "amdgpu_dm_irq.h"
  52 */
  53
  54 #include "irq_types.h"
  55 #include "signal_types.h"
  56 #include "amdgpu_dm_crc.h"
  57
  58 /* Forward declarations */
  59 struct amdgpu_device;
  60 struct drm_device;
  61 struct amdgpu_dm_irq_handler_data;
  62 struct dc;
  63 struct amdgpu_bo;
  64 struct dmub_srv;
  65
  66 struct common_irq_params {
  67         struct amdgpu_device *adev;
  68         enum dc_irq_source irq_src;
  69 };
  70
  71 /**
  72  * struct irq_list_head - Linked-list for low context IRQ handlers.
  73  *
  74  * @head: The list_head within &struct handler_data
  75  * @work: A work_struct containing the deferred handler work
  76  */
  77 struct irq_list_head {
  78         struct list_head head;
  79         /* In case this interrupt needs post-processing, 'work' will be queued*/
  80         struct work_struct work;
  81 };
  82
  83 /**
  84  * struct dm_compressor_info - Buffer info used by frame buffer compression
  85  * @cpu_addr: MMIO cpu addr
  86  * @bo_ptr: Pointer to the buffer object
  87  * @gpu_addr: MMIO gpu addr
  88  */
  89 struct dm_compressor_info {
  90         void *cpu_addr;
  91         struct amdgpu_bo *bo_ptr;
  92         uint64_t gpu_addr;
  93 };
  94
  95 /**
  96  * struct amdgpu_dm_backlight_caps - Information about backlight
  97  *
  98  * Describe the backlight support for ACPI or eDP AUX.
  99  */
 100 struct amdgpu_dm_backlight_caps {
 101         /**
 102          * @ext_caps: Keep the data struct with all the information about the
 103          * display support for HDR.
 104          */
 105         union dpcd_sink_ext_caps *ext_caps;
 106         /**
 107          * @aux_min_input_signal: Min brightness value supported by the display
 108          */
 109         u32 aux_min_input_signal;
 110         /**
 111          * @aux_max_input_signal: Max brightness value supported by the display
 112          * in nits.
 113          */
 114         u32 aux_max_input_signal;
 115         /**
 116          * @min_input_signal: minimum possible input in range 0-255.
 117          */
 118         int min_input_signal;
 119         /**
 120          * @max_input_signal: maximum possible input in range 0-255.
 121          */
 122         int max_input_signal;
 123         /**
 124          * @caps_valid: true if these values are from the ACPI interface.
 125          */
 126         bool caps_valid;
 127         /**
 128          * @aux_support: Describes if the display supports AUX backlight.
 129          */
 130         bool aux_support;
 131 };
 132
 133 /**
 134  * struct amdgpu_display_manager - Central amdgpu display manager device
 135  *
 136  * @dc: Display Core control structure
 137  * @adev: AMDGPU base driver structure
 138  * @ddev: DRM base driver structure
 139  * @display_indexes_num: Max number of display streams supported
 140  * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
 141  * @backlight_dev: Backlight control device
 142  * @backlight_link: Link on which to control backlight
 143  * @backlight_caps: Capabilities of the backlight device
 144  * @freesync_module: Module handling freesync calculations
 145  * @hdcp_workqueue: AMDGPU content protection queue
 146  * @fw_dmcu: Reference to DMCU firmware
 147  * @dmcu_fw_version: Version of the DMCU firmware
 148  * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
 149  * @cached_state: Caches device atomic state for suspend/resume
 150  * @cached_dc_state: Cached state of content streams
 151  * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
 152  * @force_timing_sync: set via debugfs. When set, indicates that all connected
 153  *                     displays will be forced to synchronize.
 154  */
 155 struct amdgpu_display_manager {
 156
 157         struct dc *dc;
 158
 159         /**
 160          * @dmub_srv:
 161          *
 162          * DMUB service, used for controlling the DMUB on hardware
 163          * that supports it. The pointer to the dmub_srv will be
 164          * NULL on hardware that does not support it.
 165          */
 166         struct dmub_srv *dmub_srv;
 167
 168         /**
 169          * @dmub_fb_info:
 170          *
 171          * Framebuffer regions for the DMUB.
 172          */
 173         struct dmub_srv_fb_info *dmub_fb_info;
 174
 175         /**
 176          * @dmub_fw:
 177          *
 178          * DMUB firmware, required on hardware that has DMUB support.
 179          */
 180         const struct firmware *dmub_fw;
 181
 182         /**
 183          * @dmub_bo:
 184          *
 185          * Buffer object for the DMUB.
 186          */
 187         struct amdgpu_bo *dmub_bo;
 188
 189         /**
 190          * @dmub_bo_gpu_addr:
 191          *
 192          * GPU virtual address for the DMUB buffer object.
 193          */
 194         u64 dmub_bo_gpu_addr;
 195
 196         /**
 197          * @dmub_bo_cpu_addr:
 198          *
 199          * CPU address for the DMUB buffer object.
 200          */
 201         void *dmub_bo_cpu_addr;
 202
 203         /**
 204          * @dmcub_fw_version:
 205          *
 206          * DMCUB firmware version.
 207          */
 208         uint32_t dmcub_fw_version;
 209
 210         /**
 211          * @cgs_device:
 212          *
 213          * The Common Graphics Services device. It provides an interface for
 214          * accessing registers.
 215          */
 216         struct cgs_device *cgs_device;
 217
 218         struct amdgpu_device *adev;
 219         struct drm_device *ddev;
 220         u16 display_indexes_num;
 221
 222         /**
 223          * @atomic_obj:
 224          *
 225          * In combination with &dm_atomic_state it helps manage
 226          * global atomic state that doesn't map cleanly into existing
 227          * drm resources, like &dc_context.
 228          */
 229         struct drm_private_obj atomic_obj;
 230
 231         /**
 232          * @dc_lock:
 233          *
 234          * Guards access to DC functions that can issue register write
 235          * sequences.
 236          */
 237         struct mutex dc_lock;
 238
 239         /**
 240          * @audio_lock:
 241          *
 242          * Guards access to audio instance changes.
 243          */
 244         struct mutex audio_lock;
 245
 246         /**
 247          * @audio_component:
 248          *
 249          * Used to notify ELD changes to sound driver.
 250          */
 251         struct drm_audio_component *audio_component;
 252
 253         /**
 254          * @audio_registered:
 255          *
 256          * True if the audio component has been registered
 257          * successfully, false otherwise.
 258          */
 259         bool audio_registered;
 260
 261         /**
 262          * @irq_handler_list_low_tab:
 263          *
 264          * Low priority IRQ handler table.
 265          *
 266          * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
 267          * source. Low priority IRQ handlers are deferred to a workqueue to be
 268          * processed. Hence, they can sleep.
 269          *
 270          * Note that handlers are called in the same order as they were
 271          * registered (FIFO).
 272          */
 273         struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
 274
 275         /**
 276          * @irq_handler_list_high_tab:
 277          *
 278          * High priority IRQ handler table.
 279          *
 280          * It is a n*m table, same as &irq_handler_list_low_tab. However,
 281          * handlers in this table are not deferred and are called immediately.
 282          */
 283         struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
 284
 285         /**
 286          * @pflip_params:
 287          *
 288          * Page flip IRQ parameters, passed to registered handlers when
 289          * triggered.
 290          */
 291         struct common_irq_params
 292         pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
 293
 294         /**
 295          * @vblank_params:
 296          *
 297          * Vertical blanking IRQ parameters, passed to registered handlers when
 298          * triggered.
 299          */
 300         struct common_irq_params
 301         vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
 302
 303         /**
 304          * @vupdate_params:
 305          *
 306          * Vertical update IRQ parameters, passed to registered handlers when
 307          * triggered.
 308          */
 309         struct common_irq_params
 310         vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
 311
 312         spinlock_t irq_handler_list_table_lock;
 313
 314         struct backlight_device *backlight_dev;
 315
 316         const struct dc_link *backlight_link;
 317         struct amdgpu_dm_backlight_caps backlight_caps;
 318
 319         struct mod_freesync *freesync_module;
 320 #ifdef CONFIG_DRM_AMD_DC_HDCP
 321         struct hdcp_workqueue *hdcp_workqueue;
 322 #endif
 323
 324         struct drm_atomic_state *cached_state;
 325         struct dc_state *cached_dc_state;
 326
 327         struct dm_compressor_info compressor;
 328
 329         const struct firmware *fw_dmcu;
 330         uint32_t dmcu_fw_version;
 331         /**
 332          * @soc_bounding_box:
 333          *
 334          * gpu_info FW provided soc bounding box struct or 0 if not
 335          * available in FW
 336          */
 337         const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
 338
 339 #ifdef CONFIG_DEBUG_FS
 340         /**
 341          * @crc_win_x_start_property:
 342          *
 343          * X start of the crc calculation window
 344          */
 345         struct drm_property *crc_win_x_start_property;
 346         /**
 347          * @crc_win_y_start_property:
 348          *
 349          * Y start of the crc calculation window
 350          */
 351         struct drm_property *crc_win_y_start_property;
 352         /**
 353          * @crc_win_x_end_property:
 354          *
 355          * X end of the crc calculation window
 356          */
 357         struct drm_property *crc_win_x_end_property;
 358         /**
 359          * @crc_win_y_end_property:
 360          *
 361          * Y end of the crc calculation window
 362          */
 363         struct drm_property *crc_win_y_end_property;
 364 #endif
 365         /**
 366          * @mst_encoders:
 367          *
 368          * fake encoders used for DP MST.
 369          */
 370         struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
 371         bool force_timing_sync;
 372 };
 373
 374 enum dsc_clock_force_state {
 375         DSC_CLK_FORCE_DEFAULT = 0,
 376         DSC_CLK_FORCE_ENABLE,
 377         DSC_CLK_FORCE_DISABLE,
 378 };
 379
 380 struct dsc_preferred_settings {
 381         enum dsc_clock_force_state dsc_force_enable;
 382         uint32_t dsc_num_slices_v;
 383         uint32_t dsc_num_slices_h;
 384         uint32_t dsc_bits_per_pixel;
 385 };
 386
 387 struct amdgpu_dm_connector {
 388
 389         struct drm_connector base;
 390         uint32_t connector_id;
 391
 392         /* we need to mind the EDID between detect
 393            and get modes due to analog/digital/tvencoder */
 394         struct edid *edid;
 395
 396         /* shared with amdgpu */
 397         struct amdgpu_hpd hpd;
 398
 399         /* number of modes generated from EDID at 'dc_sink' */
 400         int num_modes;
 401
 402         /* The 'old' sink - before an HPD.
 403          * The 'current' sink is in dc_link->sink. */
 404         struct dc_sink *dc_sink;
 405         struct dc_link *dc_link;
 406         struct dc_sink *dc_em_sink;
 407
 408         /* DM only */
 409         struct drm_dp_mst_topology_mgr mst_mgr;
 410         struct amdgpu_dm_dp_aux dm_dp_aux;
 411         struct drm_dp_mst_port *port;
 412         struct amdgpu_dm_connector *mst_port;
 413         struct drm_dp_aux *dsc_aux;
 414
 415         /* TODO see if we can merge with ddc_bus or make a dm_connector */
 416         struct amdgpu_i2c_adapter *i2c;
 417
 418         /* Monitor range limits */
 419         int min_vfreq ;
 420         int max_vfreq ;
 421         int pixel_clock_mhz;
 422
 423         /* Audio instance - protected by audio_lock. */
 424         int audio_inst;
 425
 426         struct mutex hpd_lock;
 427
 428         bool fake_enable;
 429 #ifdef CONFIG_DEBUG_FS
 430         uint32_t debugfs_dpcd_address;
 431         uint32_t debugfs_dpcd_size;
 432 #endif
 433         bool force_yuv420_output;
 434         struct dsc_preferred_settings dsc_settings;
 435 };
 436
 437 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
 438
 439 extern const struct amdgpu_ip_block_version dm_ip_block;
 440
 441 struct amdgpu_framebuffer;
 442 struct amdgpu_display_manager;
 443 struct dc_validation_set;
 444 struct dc_plane_state;
 445
 446 struct dm_plane_state {
 447         struct drm_plane_state base;
 448         struct dc_plane_state *dc_state;
 449 };
 450
 451 #ifdef CONFIG_DEBUG_FS
 452 struct crc_rec {
 453         uint16_t x_start;
 454         uint16_t y_start;
 455         uint16_t x_end;
 456         uint16_t y_end;
 457         };
 458 #endif
 459
 460 struct dm_crtc_state {
 461         struct drm_crtc_state base;
 462         struct dc_stream_state *stream;
 463
 464         bool cm_has_degamma;
 465         bool cm_is_degamma_srgb;
 466
 467         int update_type;
 468         int active_planes;
 469
 470         int crc_skip_count;
 471         enum amdgpu_dm_pipe_crc_source crc_src;
 472
 473         bool freesync_timing_changed;
 474         bool freesync_vrr_info_changed;
 475
 476         bool dsc_force_changed;
 477         bool vrr_supported;
 478         struct mod_freesync_config freesync_config;
 479         struct dc_info_packet vrr_infopacket;
 480
 481         int abm_level;
 482 #ifdef CONFIG_DEBUG_FS
 483         struct crc_rec crc_window;
 484 #endif
 485 };
 486
 487 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
 488
 489 struct dm_atomic_state {
 490         struct drm_private_state base;
 491
 492         struct dc_state *context;
 493 };
 494
 495 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
 496
 497 struct dm_connector_state {
 498         struct drm_connector_state base;
 499
 500         enum amdgpu_rmx_type scaling;
 501         uint8_t underscan_vborder;
 502         uint8_t underscan_hborder;
 503         bool underscan_enable;
 504         bool freesync_capable;
 505 #ifdef CONFIG_DRM_AMD_DC_HDCP
 506         bool update_hdcp;
 507 #endif
 508         uint8_t abm_level;
 509         int vcpi_slots;
 510         uint64_t pbn;
 511 };
 512
 513 #define to_dm_connector_state(x)\
 514         container_of((x), struct dm_connector_state, base)
 515
 516 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
 517 struct drm_connector_state *
 518 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
 519 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
 520                                             struct drm_connector_state *state,
 521                                             struct drm_property *property,
 522                                             uint64_t val);
 523
 524 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
 525                                             const struct drm_connector_state *state,
 526                                             struct drm_property *property,
 527                                             uint64_t *val);
 528
 529 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
 530
 531 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
 532                                      struct amdgpu_dm_connector *aconnector,
 533                                      int connector_type,
 534                                      struct dc_link *link,
 535                                      int link_index);
 536
 537 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
 538                                    struct drm_display_mode *mode);
 539
 540 void dm_restore_drm_connector_state(struct drm_device *dev,
 541                                     struct drm_connector *connector);
 542
 543 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
 544                                         struct edid *edid);
 545
 546 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
 547
 548 #define MAX_COLOR_LUT_ENTRIES 4096
 549 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
 550 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
 551
 552 void amdgpu_dm_init_color_mod(void);
 553 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
 554 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
 555                                       struct dc_plane_state *dc_plane_state);
 556
 557 void amdgpu_dm_update_connector_after_detect(
 558                 struct amdgpu_dm_connector *aconnector);
 559
 560 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
 561
 562 #endif /* __AMDGPU_DM_H__ */