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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / bios / bios_parser2.c
blob670c26583817817eb5b24d3a80e0806fbe65deee
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "ObjectID.h"
31 #include "atomfirmware.h"
32
33 #include "dc_bios_types.h"
34 #include "include/grph_object_ctrl_defs.h"
35 #include "include/bios_parser_interface.h"
36 #include "include/i2caux_interface.h"
37 #include "include/logger_interface.h"
38
39 #include "command_table2.h"
40
41 #include "bios_parser_helper.h"
42 #include "command_table_helper2.h"
43 #include "bios_parser2.h"
44 #include "bios_parser_types_internal2.h"
45 #include "bios_parser_interface.h"
46
47 #include "bios_parser_common.h"
48
49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */
50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT
51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05
52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */
53
54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \
56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */
60
61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \
63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */
67
68 #define DC_LOGGER \
69 bp->base.ctx->logger
70
71 #define LAST_RECORD_TYPE 0xff
72 #define SMU9_SYSPLL0_ID 0
73
74 struct i2c_id_config_access {
75 uint8_t bfI2C_LineMux:4;
76 uint8_t bfHW_EngineID:3;
77 uint8_t bfHW_Capable:1;
78 uint8_t ucAccess;
79 };
80
81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
82 struct atom_i2c_record *record,
83 struct graphics_object_i2c_info *info);
84
85 static enum bp_result bios_parser_get_firmware_info(
86 struct dc_bios *dcb,
87 struct dc_firmware_info *info);
88
89 static enum bp_result bios_parser_get_encoder_cap_info(
90 struct dc_bios *dcb,
91 struct graphics_object_id object_id,
92 struct bp_encoder_cap_info *info);
93
94 static enum bp_result get_firmware_info_v3_1(
95 struct bios_parser *bp,
96 struct dc_firmware_info *info);
97
98 static enum bp_result get_firmware_info_v3_2(
99 struct bios_parser *bp,
100 struct dc_firmware_info *info);
101
102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
103 struct atom_display_object_path_v2 *object);
104
105 static struct atom_encoder_caps_record *get_encoder_cap_record(
106 struct bios_parser *bp,
107 struct atom_display_object_path_v2 *object);
108
109 #define BIOS_IMAGE_SIZE_OFFSET 2
110 #define BIOS_IMAGE_SIZE_UNIT 512
111
112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
113
114 static void bios_parser2_destruct(struct bios_parser *bp)
115 {
116 kfree(bp->base.bios_local_image);
117 kfree(bp->base.integrated_info);
118 }
119
120 static void firmware_parser_destroy(struct dc_bios **dcb)
121 {
122 struct bios_parser *bp = BP_FROM_DCB(*dcb);
123
124 if (!bp) {
125 BREAK_TO_DEBUGGER();
126 return;
127 }
128
129 bios_parser2_destruct(bp);
130
131 kfree(bp);
132 *dcb = NULL;
133 }
134
135 static void get_atom_data_table_revision(
136 struct atom_common_table_header *atom_data_tbl,
137 struct atom_data_revision *tbl_revision)
138 {
139 if (!tbl_revision)
140 return;
141
142 /* initialize the revision to 0 which is invalid revision */
143 tbl_revision->major = 0;
144 tbl_revision->minor = 0;
145
146 if (!atom_data_tbl)
147 return;
148
149 tbl_revision->major =
150 (uint32_t) atom_data_tbl->format_revision & 0x3f;
151 tbl_revision->minor =
152 (uint32_t) atom_data_tbl->content_revision & 0x3f;
153 }
154
155 /* BIOS oject table displaypath is per connector.
156 * There is extra path not for connector. BIOS fill its encoderid as 0
157 */
158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
159 {
160 struct bios_parser *bp = BP_FROM_DCB(dcb);
161 unsigned int count = 0;
162 unsigned int i;
163
164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
166 count++;
167 }
168 return count;
169 }
170
171 static struct graphics_object_id bios_parser_get_connector_id(
172 struct dc_bios *dcb,
173 uint8_t i)
174 {
175 struct bios_parser *bp = BP_FROM_DCB(dcb);
176 struct graphics_object_id object_id = dal_graphics_object_id_init(
177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
178 struct object_info_table *tbl = &bp->object_info_tbl;
179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
180
181 if (v1_4->number_of_path > i) {
182 /* If display_objid is generic object id, the encoderObj
183 * /extencoderobjId should be 0
184 */
185 if (v1_4->display_path[i].encoderobjid != 0 &&
186 v1_4->display_path[i].display_objid != 0)
187 object_id = object_id_from_bios_object_id(
188 v1_4->display_path[i].display_objid);
189 }
190
191 return object_id;
192 }
193
194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
195 struct graphics_object_id object_id, uint32_t index,
196 struct graphics_object_id *src_object_id)
197 {
198 struct bios_parser *bp = BP_FROM_DCB(dcb);
199 unsigned int i;
200 enum bp_result bp_result = BP_RESULT_BADINPUT;
201 struct graphics_object_id obj_id = {0};
202 struct object_info_table *tbl = &bp->object_info_tbl;
203
204 if (!src_object_id)
205 return bp_result;
206
207 switch (object_id.type) {
208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
210 */
211 case OBJECT_TYPE_ENCODER:
212 /* TODO: since num of src must be less than 2.
213 * If found in for loop, should break.
214 * DAL2 implementation may be changed too
215 */
216 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
217 obj_id = object_id_from_bios_object_id(
218 tbl->v1_4->display_path[i].encoderobjid);
219 if (object_id.type == obj_id.type &&
220 object_id.id == obj_id.id &&
221 object_id.enum_id ==
222 obj_id.enum_id) {
223 *src_object_id =
224 object_id_from_bios_object_id(0x1100);
225 /* break; */
226 }
227 }
228 bp_result = BP_RESULT_OK;
229 break;
230 case OBJECT_TYPE_CONNECTOR:
231 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
232 obj_id = object_id_from_bios_object_id(
233 tbl->v1_4->display_path[i].display_objid);
234
235 if (object_id.type == obj_id.type &&
236 object_id.id == obj_id.id &&
237 object_id.enum_id == obj_id.enum_id) {
238 *src_object_id =
239 object_id_from_bios_object_id(
240 tbl->v1_4->display_path[i].encoderobjid);
241 /* break; */
242 }
243 }
244 bp_result = BP_RESULT_OK;
245 break;
246 default:
247 break;
248 }
249
250 return bp_result;
251 }
252
253 /* from graphics_object_id, find display path which includes the object_id */
254 static struct atom_display_object_path_v2 *get_bios_object(
255 struct bios_parser *bp,
256 struct graphics_object_id id)
257 {
258 unsigned int i;
259 struct graphics_object_id obj_id = {0};
260
261 switch (id.type) {
262 case OBJECT_TYPE_ENCODER:
263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
264 obj_id = object_id_from_bios_object_id(
265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
266 if (id.type == obj_id.type && id.id == obj_id.id
267 && id.enum_id == obj_id.enum_id)
268 return &bp->object_info_tbl.v1_4->display_path[i];
269 }
270 fallthrough;
271 case OBJECT_TYPE_CONNECTOR:
272 case OBJECT_TYPE_GENERIC:
273 /* Both Generic and Connector Object ID
274 * will be stored on display_objid
275 */
276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
277 obj_id = object_id_from_bios_object_id(
278 bp->object_info_tbl.v1_4->display_path[i].display_objid);
279 if (id.type == obj_id.type && id.id == obj_id.id
280 && id.enum_id == obj_id.enum_id)
281 return &bp->object_info_tbl.v1_4->display_path[i];
282 }
283 fallthrough;
284 default:
285 return NULL;
286 }
287 }
288
289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
290 struct graphics_object_id id,
291 struct graphics_object_i2c_info *info)
292 {
293 uint32_t offset;
294 struct atom_display_object_path_v2 *object;
295 struct atom_common_record_header *header;
296 struct atom_i2c_record *record;
297 struct atom_i2c_record dummy_record = {0};
298 struct bios_parser *bp = BP_FROM_DCB(dcb);
299
300 if (!info)
301 return BP_RESULT_BADINPUT;
302
303 if (id.type == OBJECT_TYPE_GENERIC) {
304 dummy_record.i2c_id = id.id;
305
306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
307 return BP_RESULT_OK;
308 else
309 return BP_RESULT_NORECORD;
310 }
311
312 object = get_bios_object(bp, id);
313
314 if (!object)
315 return BP_RESULT_BADINPUT;
316
317 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
318
319 for (;;) {
320 header = GET_IMAGE(struct atom_common_record_header, offset);
321
322 if (!header)
323 return BP_RESULT_BADBIOSTABLE;
324
325 if (header->record_type == LAST_RECORD_TYPE ||
326 !header->record_size)
327 break;
328
329 if (header->record_type == ATOM_I2C_RECORD_TYPE
330 && sizeof(struct atom_i2c_record) <=
331 header->record_size) {
332 /* get the I2C info */
333 record = (struct atom_i2c_record *) header;
334
335 if (get_gpio_i2c_info(bp, record, info) ==
336 BP_RESULT_OK)
337 return BP_RESULT_OK;
338 }
339
340 offset += header->record_size;
341 }
342
343 return BP_RESULT_NORECORD;
344 }
345
346 static enum bp_result get_gpio_i2c_info(
347 struct bios_parser *bp,
348 struct atom_i2c_record *record,
349 struct graphics_object_i2c_info *info)
350 {
351 struct atom_gpio_pin_lut_v2_1 *header;
352 uint32_t count = 0;
353 unsigned int table_index = 0;
354 bool find_valid = false;
355
356 if (!info)
357 return BP_RESULT_BADINPUT;
358
359 /* get the GPIO_I2C info */
360 if (!DATA_TABLES(gpio_pin_lut))
361 return BP_RESULT_BADBIOSTABLE;
362
363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
364 DATA_TABLES(gpio_pin_lut));
365 if (!header)
366 return BP_RESULT_BADBIOSTABLE;
367
368 if (sizeof(struct atom_common_table_header) +
369 sizeof(struct atom_gpio_pin_assignment) >
370 le16_to_cpu(header->table_header.structuresize))
371 return BP_RESULT_BADBIOSTABLE;
372
373 /* TODO: is version change? */
374 if (header->table_header.content_revision != 1)
375 return BP_RESULT_UNSUPPORTED;
376
377 /* get data count */
378 count = (le16_to_cpu(header->table_header.structuresize)
379 - sizeof(struct atom_common_table_header))
380 / sizeof(struct atom_gpio_pin_assignment);
381
382 for (table_index = 0; table_index < count; table_index++) {
383 if (((record->i2c_id & I2C_HW_CAP) == (
384 header->gpio_pin[table_index].gpio_id &
385 I2C_HW_CAP)) &&
386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
387 (header->gpio_pin[table_index].gpio_id &
388 I2C_HW_ENGINE_ID_MASK)) &&
389 ((record->i2c_id & I2C_HW_LANE_MUX) ==
390 (header->gpio_pin[table_index].gpio_id &
391 I2C_HW_LANE_MUX))) {
392 /* still valid */
393 find_valid = true;
394 break;
395 }
396 }
397
398 /* If we don't find the entry that we are looking for then
399 * we will return BP_Result_BadBiosTable.
400 */
401 if (find_valid == false)
402 return BP_RESULT_BADBIOSTABLE;
403
404 /* get the GPIO_I2C_INFO */
405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
408 info->i2c_slave_address = record->i2c_slave_addr;
409
410 /* TODO: check how to get register offset for en, Y, etc. */
411 info->gpio_info.clk_a_register_index =
412 le16_to_cpu(
413 header->gpio_pin[table_index].data_a_reg_index);
414 info->gpio_info.clk_a_shift =
415 header->gpio_pin[table_index].gpio_bitshift;
416
417 return BP_RESULT_OK;
418 }
419
420 static enum bp_result bios_parser_get_hpd_info(
421 struct dc_bios *dcb,
422 struct graphics_object_id id,
423 struct graphics_object_hpd_info *info)
424 {
425 struct bios_parser *bp = BP_FROM_DCB(dcb);
426 struct atom_display_object_path_v2 *object;
427 struct atom_hpd_int_record *record = NULL;
428
429 if (!info)
430 return BP_RESULT_BADINPUT;
431
432 object = get_bios_object(bp, id);
433
434 if (!object)
435 return BP_RESULT_BADINPUT;
436
437 record = get_hpd_record(bp, object);
438
439 if (record != NULL) {
440 info->hpd_int_gpio_uid = record->pin_id;
441 info->hpd_active = record->plugin_pin_state;
442 return BP_RESULT_OK;
443 }
444
445 return BP_RESULT_NORECORD;
446 }
447
448 static struct atom_hpd_int_record *get_hpd_record(
449 struct bios_parser *bp,
450 struct atom_display_object_path_v2 *object)
451 {
452 struct atom_common_record_header *header;
453 uint32_t offset;
454
455 if (!object) {
456 BREAK_TO_DEBUGGER(); /* Invalid object */
457 return NULL;
458 }
459
460 offset = le16_to_cpu(object->disp_recordoffset)
461 + bp->object_info_tbl_offset;
462
463 for (;;) {
464 header = GET_IMAGE(struct atom_common_record_header, offset);
465
466 if (!header)
467 return NULL;
468
469 if (header->record_type == LAST_RECORD_TYPE ||
470 !header->record_size)
471 break;
472
473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
474 && sizeof(struct atom_hpd_int_record) <=
475 header->record_size)
476 return (struct atom_hpd_int_record *) header;
477
478 offset += header->record_size;
479 }
480
481 return NULL;
482 }
483
484 /**
485 * bios_parser_get_gpio_pin_info
486 * Get GpioPin information of input gpio id
487 *
488 * @param gpio_id, GPIO ID
489 * @param info, GpioPin information structure
490 * @return Bios parser result code
491 * @note
492 * to get the GPIO PIN INFO, we need:
493 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
494 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
495 * to get the registerA offset/mask
496 */
497 static enum bp_result bios_parser_get_gpio_pin_info(
498 struct dc_bios *dcb,
499 uint32_t gpio_id,
500 struct gpio_pin_info *info)
501 {
502 struct bios_parser *bp = BP_FROM_DCB(dcb);
503 struct atom_gpio_pin_lut_v2_1 *header;
504 uint32_t count = 0;
505 uint32_t i = 0;
506
507 if (!DATA_TABLES(gpio_pin_lut))
508 return BP_RESULT_BADBIOSTABLE;
509
510 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
511 DATA_TABLES(gpio_pin_lut));
512 if (!header)
513 return BP_RESULT_BADBIOSTABLE;
514
515 if (sizeof(struct atom_common_table_header) +
516 sizeof(struct atom_gpio_pin_assignment)
517 > le16_to_cpu(header->table_header.structuresize))
518 return BP_RESULT_BADBIOSTABLE;
519
520 if (header->table_header.content_revision != 1)
521 return BP_RESULT_UNSUPPORTED;
522
523 /* Temporary hard code gpio pin info */
524 #if defined(FOR_SIMNOW_BOOT)
525 {
526 struct atom_gpio_pin_assignment gpio_pin[8] = {
527 {0x5db5, 0, 0, 1, 0},
528 {0x5db5, 8, 8, 2, 0},
529 {0x5db5, 0x10, 0x10, 3, 0},
530 {0x5db5, 0x18, 0x14, 4, 0},
531 {0x5db5, 0x1A, 0x18, 5, 0},
532 {0x5db5, 0x1C, 0x1C, 6, 0},
533 };
534
535 count = 6;
536 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
537 }
538 #else
539 count = (le16_to_cpu(header->table_header.structuresize)
540 - sizeof(struct atom_common_table_header))
541 / sizeof(struct atom_gpio_pin_assignment);
542 #endif
543 for (i = 0; i < count; ++i) {
544 if (header->gpio_pin[i].gpio_id != gpio_id)
545 continue;
546
547 info->offset =
548 (uint32_t) le16_to_cpu(
549 header->gpio_pin[i].data_a_reg_index);
550 info->offset_y = info->offset + 2;
551 info->offset_en = info->offset + 1;
552 info->offset_mask = info->offset - 1;
553
554 info->mask = (uint32_t) (1 <<
555 header->gpio_pin[i].gpio_bitshift);
556 info->mask_y = info->mask + 2;
557 info->mask_en = info->mask + 1;
558 info->mask_mask = info->mask - 1;
559
560 return BP_RESULT_OK;
561 }
562
563 return BP_RESULT_NORECORD;
564 }
565
566 static struct device_id device_type_from_device_id(uint16_t device_id)
567 {
568
569 struct device_id result_device_id;
570
571 result_device_id.raw_device_tag = device_id;
572
573 switch (device_id) {
574 case ATOM_DISPLAY_LCD1_SUPPORT:
575 result_device_id.device_type = DEVICE_TYPE_LCD;
576 result_device_id.enum_id = 1;
577 break;
578
579 case ATOM_DISPLAY_DFP1_SUPPORT:
580 result_device_id.device_type = DEVICE_TYPE_DFP;
581 result_device_id.enum_id = 1;
582 break;
583
584 case ATOM_DISPLAY_DFP2_SUPPORT:
585 result_device_id.device_type = DEVICE_TYPE_DFP;
586 result_device_id.enum_id = 2;
587 break;
588
589 case ATOM_DISPLAY_DFP3_SUPPORT:
590 result_device_id.device_type = DEVICE_TYPE_DFP;
591 result_device_id.enum_id = 3;
592 break;
593
594 case ATOM_DISPLAY_DFP4_SUPPORT:
595 result_device_id.device_type = DEVICE_TYPE_DFP;
596 result_device_id.enum_id = 4;
597 break;
598
599 case ATOM_DISPLAY_DFP5_SUPPORT:
600 result_device_id.device_type = DEVICE_TYPE_DFP;
601 result_device_id.enum_id = 5;
602 break;
603
604 case ATOM_DISPLAY_DFP6_SUPPORT:
605 result_device_id.device_type = DEVICE_TYPE_DFP;
606 result_device_id.enum_id = 6;
607 break;
608
609 default:
610 BREAK_TO_DEBUGGER(); /* Invalid device Id */
611 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
612 result_device_id.enum_id = 0;
613 }
614 return result_device_id;
615 }
616
617 static enum bp_result bios_parser_get_device_tag(
618 struct dc_bios *dcb,
619 struct graphics_object_id connector_object_id,
620 uint32_t device_tag_index,
621 struct connector_device_tag_info *info)
622 {
623 struct bios_parser *bp = BP_FROM_DCB(dcb);
624 struct atom_display_object_path_v2 *object;
625
626 if (!info)
627 return BP_RESULT_BADINPUT;
628
629 /* getBiosObject will return MXM object */
630 object = get_bios_object(bp, connector_object_id);
631
632 if (!object) {
633 BREAK_TO_DEBUGGER(); /* Invalid object id */
634 return BP_RESULT_BADINPUT;
635 }
636
637 info->acpi_device = 0; /* BIOS no longer provides this */
638 info->dev_id = device_type_from_device_id(object->device_tag);
639
640 return BP_RESULT_OK;
641 }
642
643 static enum bp_result get_ss_info_v4_1(
644 struct bios_parser *bp,
645 uint32_t id,
646 uint32_t index,
647 struct spread_spectrum_info *ss_info)
648 {
649 enum bp_result result = BP_RESULT_OK;
650 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
651 struct atom_smu_info_v3_3 *smu_info = NULL;
652
653 if (!ss_info)
654 return BP_RESULT_BADINPUT;
655
656 if (!DATA_TABLES(dce_info))
657 return BP_RESULT_BADBIOSTABLE;
658
659 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
660 DATA_TABLES(dce_info));
661 if (!disp_cntl_tbl)
662 return BP_RESULT_BADBIOSTABLE;
663
664
665 ss_info->type.STEP_AND_DELAY_INFO = false;
666 ss_info->spread_percentage_divider = 1000;
667 /* BIOS no longer uses target clock. Always enable for now */
668 ss_info->target_clock_range = 0xffffffff;
669
670 switch (id) {
671 case AS_SIGNAL_TYPE_DVI:
672 ss_info->spread_spectrum_percentage =
673 disp_cntl_tbl->dvi_ss_percentage;
674 ss_info->spread_spectrum_range =
675 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
676 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
677 ss_info->type.CENTER_MODE = true;
678 break;
679 case AS_SIGNAL_TYPE_HDMI:
680 ss_info->spread_spectrum_percentage =
681 disp_cntl_tbl->hdmi_ss_percentage;
682 ss_info->spread_spectrum_range =
683 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
684 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
685 ss_info->type.CENTER_MODE = true;
686 break;
687 /* TODO LVDS not support anymore? */
688 case AS_SIGNAL_TYPE_DISPLAY_PORT:
689 ss_info->spread_spectrum_percentage =
690 disp_cntl_tbl->dp_ss_percentage;
691 ss_info->spread_spectrum_range =
692 disp_cntl_tbl->dp_ss_rate_10hz * 10;
693 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
694 ss_info->type.CENTER_MODE = true;
695 break;
696 case AS_SIGNAL_TYPE_GPU_PLL:
697 /* atom_firmware: DAL only get data from dce_info table.
698 * if data within smu_info is needed for DAL, VBIOS should
699 * copy it into dce_info
700 */
701 result = BP_RESULT_UNSUPPORTED;
702 break;
703 case AS_SIGNAL_TYPE_XGMI:
704 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
705 DATA_TABLES(smu_info));
706 if (!smu_info)
707 return BP_RESULT_BADBIOSTABLE;
708
709 ss_info->spread_spectrum_percentage =
710 smu_info->waflclk_ss_percentage;
711 ss_info->spread_spectrum_range =
712 smu_info->gpuclk_ss_rate_10hz * 10;
713 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
714 ss_info->type.CENTER_MODE = true;
715 break;
716 default:
717 result = BP_RESULT_UNSUPPORTED;
718 }
719
720 return result;
721 }
722
723 static enum bp_result get_ss_info_v4_2(
724 struct bios_parser *bp,
725 uint32_t id,
726 uint32_t index,
727 struct spread_spectrum_info *ss_info)
728 {
729 enum bp_result result = BP_RESULT_OK;
730 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
731 struct atom_smu_info_v3_1 *smu_info = NULL;
732
733 if (!ss_info)
734 return BP_RESULT_BADINPUT;
735
736 if (!DATA_TABLES(dce_info))
737 return BP_RESULT_BADBIOSTABLE;
738
739 if (!DATA_TABLES(smu_info))
740 return BP_RESULT_BADBIOSTABLE;
741
742 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
743 DATA_TABLES(dce_info));
744 if (!disp_cntl_tbl)
745 return BP_RESULT_BADBIOSTABLE;
746
747 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
748 if (!smu_info)
749 return BP_RESULT_BADBIOSTABLE;
750
751 ss_info->type.STEP_AND_DELAY_INFO = false;
752 ss_info->spread_percentage_divider = 1000;
753 /* BIOS no longer uses target clock. Always enable for now */
754 ss_info->target_clock_range = 0xffffffff;
755
756 switch (id) {
757 case AS_SIGNAL_TYPE_DVI:
758 ss_info->spread_spectrum_percentage =
759 disp_cntl_tbl->dvi_ss_percentage;
760 ss_info->spread_spectrum_range =
761 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
762 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
763 ss_info->type.CENTER_MODE = true;
764 break;
765 case AS_SIGNAL_TYPE_HDMI:
766 ss_info->spread_spectrum_percentage =
767 disp_cntl_tbl->hdmi_ss_percentage;
768 ss_info->spread_spectrum_range =
769 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
770 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
771 ss_info->type.CENTER_MODE = true;
772 break;
773 /* TODO LVDS not support anymore? */
774 case AS_SIGNAL_TYPE_DISPLAY_PORT:
775 ss_info->spread_spectrum_percentage =
776 smu_info->gpuclk_ss_percentage;
777 ss_info->spread_spectrum_range =
778 smu_info->gpuclk_ss_rate_10hz * 10;
779 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
780 ss_info->type.CENTER_MODE = true;
781 break;
782 case AS_SIGNAL_TYPE_GPU_PLL:
783 /* atom_firmware: DAL only get data from dce_info table.
784 * if data within smu_info is needed for DAL, VBIOS should
785 * copy it into dce_info
786 */
787 result = BP_RESULT_UNSUPPORTED;
788 break;
789 default:
790 result = BP_RESULT_UNSUPPORTED;
791 }
792
793 return result;
794 }
795
796 /**
797 * bios_parser_get_spread_spectrum_info
798 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
799 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
800 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
801 * ver 3.1,
802 * there is only one entry for each signal /ss id. However, there is
803 * no planning of supporting multiple spread Sprectum entry for EverGreen
804 * @param [in] this
805 * @param [in] signal, ASSignalType to be converted to info index
806 * @param [in] index, number of entries that match the converted info index
807 * @param [out] ss_info, sprectrum information structure,
808 * @return Bios parser result code
809 */
810 static enum bp_result bios_parser_get_spread_spectrum_info(
811 struct dc_bios *dcb,
812 enum as_signal_type signal,
813 uint32_t index,
814 struct spread_spectrum_info *ss_info)
815 {
816 struct bios_parser *bp = BP_FROM_DCB(dcb);
817 enum bp_result result = BP_RESULT_UNSUPPORTED;
818 struct atom_common_table_header *header;
819 struct atom_data_revision tbl_revision;
820
821 if (!ss_info) /* check for bad input */
822 return BP_RESULT_BADINPUT;
823
824 if (!DATA_TABLES(dce_info))
825 return BP_RESULT_UNSUPPORTED;
826
827 header = GET_IMAGE(struct atom_common_table_header,
828 DATA_TABLES(dce_info));
829 get_atom_data_table_revision(header, &tbl_revision);
830
831 switch (tbl_revision.major) {
832 case 4:
833 switch (tbl_revision.minor) {
834 case 1:
835 return get_ss_info_v4_1(bp, signal, index, ss_info);
836 case 2:
837 case 3:
838 return get_ss_info_v4_2(bp, signal, index, ss_info);
839 default:
840 break;
841 }
842 break;
843 default:
844 break;
845 }
846 /* there can not be more then one entry for SS Info table */
847 return result;
848 }
849
850 static enum bp_result get_soc_bb_info_v4_4(
851 struct bios_parser *bp,
852 struct bp_soc_bb_info *soc_bb_info)
853 {
854 enum bp_result result = BP_RESULT_OK;
855 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
856
857 if (!soc_bb_info)
858 return BP_RESULT_BADINPUT;
859
860 if (!DATA_TABLES(dce_info))
861 return BP_RESULT_BADBIOSTABLE;
862
863 if (!DATA_TABLES(smu_info))
864 return BP_RESULT_BADBIOSTABLE;
865
866 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
867 DATA_TABLES(dce_info));
868 if (!disp_cntl_tbl)
869 return BP_RESULT_BADBIOSTABLE;
870
871 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
872 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
873 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
874
875 return result;
876 }
877
878 static enum bp_result bios_parser_get_soc_bb_info(
879 struct dc_bios *dcb,
880 struct bp_soc_bb_info *soc_bb_info)
881 {
882 struct bios_parser *bp = BP_FROM_DCB(dcb);
883 enum bp_result result = BP_RESULT_UNSUPPORTED;
884 struct atom_common_table_header *header;
885 struct atom_data_revision tbl_revision;
886
887 if (!soc_bb_info) /* check for bad input */
888 return BP_RESULT_BADINPUT;
889
890 if (!DATA_TABLES(dce_info))
891 return BP_RESULT_UNSUPPORTED;
892
893 header = GET_IMAGE(struct atom_common_table_header,
894 DATA_TABLES(dce_info));
895 get_atom_data_table_revision(header, &tbl_revision);
896
897 switch (tbl_revision.major) {
898 case 4:
899 switch (tbl_revision.minor) {
900 case 1:
901 case 2:
902 case 3:
903 break;
904 case 4:
905 result = get_soc_bb_info_v4_4(bp, soc_bb_info);
906 break;
907 default:
908 break;
909 }
910 break;
911 default:
912 break;
913 }
914
915 return result;
916 }
917
918 static enum bp_result get_embedded_panel_info_v2_1(
919 struct bios_parser *bp,
920 struct embedded_panel_info *info)
921 {
922 struct lcd_info_v2_1 *lvds;
923
924 if (!info)
925 return BP_RESULT_BADINPUT;
926
927 if (!DATA_TABLES(lcd_info))
928 return BP_RESULT_UNSUPPORTED;
929
930 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
931
932 if (!lvds)
933 return BP_RESULT_BADBIOSTABLE;
934
935 /* TODO: previous vv1_3, should v2_1 */
936 if (!((lvds->table_header.format_revision == 2)
937 && (lvds->table_header.content_revision >= 1)))
938 return BP_RESULT_UNSUPPORTED;
939
940 memset(info, 0, sizeof(struct embedded_panel_info));
941
942 /* We need to convert from 10KHz units into KHz units */
943 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
944 /* usHActive does not include borders, according to VBIOS team */
945 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
946 /* usHBlanking_Time includes borders, so we should really be
947 * subtractingborders duing this translation, but LVDS generally
948 * doesn't have borders, so we should be okay leaving this as is for
949 * now. May need to revisit if we ever have LVDS with borders
950 */
951 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
952 /* usVActive does not include borders, according to VBIOS team*/
953 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
954 /* usVBlanking_Time includes borders, so we should really be
955 * subtracting borders duing this translation, but LVDS generally
956 * doesn't have borders, so we should be okay leaving this as is for
957 * now. May need to revisit if we ever have LVDS with borders
958 */
959 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
960 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
961 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
962 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
963 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
964 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
965 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
966
967 /* not provided by VBIOS */
968 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
969
970 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
971 & ATOM_HSYNC_POLARITY);
972 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
973 & ATOM_VSYNC_POLARITY);
974
975 /* not provided by VBIOS */
976 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
977
978 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
979 & ATOM_H_REPLICATIONBY2);
980 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
981 & ATOM_V_REPLICATIONBY2);
982 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
983 & ATOM_COMPOSITESYNC);
984 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
985
986 /* not provided by VBIOS*/
987 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
988 /* not provided by VBIOS*/
989 info->ss_id = 0;
990
991 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
992
993 return BP_RESULT_OK;
994 }
995
996 static enum bp_result bios_parser_get_embedded_panel_info(
997 struct dc_bios *dcb,
998 struct embedded_panel_info *info)
999 {
1000 struct bios_parser
1001 *bp = BP_FROM_DCB(dcb);
1002 struct atom_common_table_header *header;
1003 struct atom_data_revision tbl_revision;
1004
1005 if (!DATA_TABLES(lcd_info))
1006 return BP_RESULT_FAILURE;
1007
1008 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
1009
1010 if (!header)
1011 return BP_RESULT_BADBIOSTABLE;
1012
1013 get_atom_data_table_revision(header, &tbl_revision);
1014
1015 switch (tbl_revision.major) {
1016 case 2:
1017 switch (tbl_revision.minor) {
1018 case 1:
1019 return get_embedded_panel_info_v2_1(bp, info);
1020 default:
1021 break;
1022 }
1023 break;
1024 default:
1025 break;
1026 }
1027
1028 return BP_RESULT_FAILURE;
1029 }
1030
1031 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1032 {
1033 enum dal_device_type device_type = device_id.device_type;
1034 uint32_t enum_id = device_id.enum_id;
1035
1036 switch (device_type) {
1037 case DEVICE_TYPE_LCD:
1038 switch (enum_id) {
1039 case 1:
1040 return ATOM_DISPLAY_LCD1_SUPPORT;
1041 default:
1042 break;
1043 }
1044 break;
1045 case DEVICE_TYPE_DFP:
1046 switch (enum_id) {
1047 case 1:
1048 return ATOM_DISPLAY_DFP1_SUPPORT;
1049 case 2:
1050 return ATOM_DISPLAY_DFP2_SUPPORT;
1051 case 3:
1052 return ATOM_DISPLAY_DFP3_SUPPORT;
1053 case 4:
1054 return ATOM_DISPLAY_DFP4_SUPPORT;
1055 case 5:
1056 return ATOM_DISPLAY_DFP5_SUPPORT;
1057 case 6:
1058 return ATOM_DISPLAY_DFP6_SUPPORT;
1059 default:
1060 break;
1061 }
1062 break;
1063 default:
1064 break;
1065 }
1066
1067 /* Unidentified device ID, return empty support mask. */
1068 return 0;
1069 }
1070
1071 static bool bios_parser_is_device_id_supported(
1072 struct dc_bios *dcb,
1073 struct device_id id)
1074 {
1075 struct bios_parser *bp = BP_FROM_DCB(dcb);
1076
1077 uint32_t mask = get_support_mask_for_device_id(id);
1078
1079 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
1080 mask) != 0;
1081 }
1082
1083 static uint32_t bios_parser_get_ss_entry_number(
1084 struct dc_bios *dcb,
1085 enum as_signal_type signal)
1086 {
1087 /* TODO: DAL2 atomfirmware implementation does not need this.
1088 * why DAL3 need this?
1089 */
1090 return 1;
1091 }
1092
1093 static enum bp_result bios_parser_transmitter_control(
1094 struct dc_bios *dcb,
1095 struct bp_transmitter_control *cntl)
1096 {
1097 struct bios_parser *bp = BP_FROM_DCB(dcb);
1098
1099 if (!bp->cmd_tbl.transmitter_control)
1100 return BP_RESULT_FAILURE;
1101
1102 return bp->cmd_tbl.transmitter_control(bp, cntl);
1103 }
1104
1105 static enum bp_result bios_parser_encoder_control(
1106 struct dc_bios *dcb,
1107 struct bp_encoder_control *cntl)
1108 {
1109 struct bios_parser *bp = BP_FROM_DCB(dcb);
1110
1111 if (!bp->cmd_tbl.dig_encoder_control)
1112 return BP_RESULT_FAILURE;
1113
1114 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1115 }
1116
1117 static enum bp_result bios_parser_set_pixel_clock(
1118 struct dc_bios *dcb,
1119 struct bp_pixel_clock_parameters *bp_params)
1120 {
1121 struct bios_parser *bp = BP_FROM_DCB(dcb);
1122
1123 if (!bp->cmd_tbl.set_pixel_clock)
1124 return BP_RESULT_FAILURE;
1125
1126 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1127 }
1128
1129 static enum bp_result bios_parser_set_dce_clock(
1130 struct dc_bios *dcb,
1131 struct bp_set_dce_clock_parameters *bp_params)
1132 {
1133 struct bios_parser *bp = BP_FROM_DCB(dcb);
1134
1135 if (!bp->cmd_tbl.set_dce_clock)
1136 return BP_RESULT_FAILURE;
1137
1138 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1139 }
1140
1141 static enum bp_result bios_parser_program_crtc_timing(
1142 struct dc_bios *dcb,
1143 struct bp_hw_crtc_timing_parameters *bp_params)
1144 {
1145 struct bios_parser *bp = BP_FROM_DCB(dcb);
1146
1147 if (!bp->cmd_tbl.set_crtc_timing)
1148 return BP_RESULT_FAILURE;
1149
1150 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1151 }
1152
1153 static enum bp_result bios_parser_enable_crtc(
1154 struct dc_bios *dcb,
1155 enum controller_id id,
1156 bool enable)
1157 {
1158 struct bios_parser *bp = BP_FROM_DCB(dcb);
1159
1160 if (!bp->cmd_tbl.enable_crtc)
1161 return BP_RESULT_FAILURE;
1162
1163 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1164 }
1165
1166 static enum bp_result bios_parser_enable_disp_power_gating(
1167 struct dc_bios *dcb,
1168 enum controller_id controller_id,
1169 enum bp_pipe_control_action action)
1170 {
1171 struct bios_parser *bp = BP_FROM_DCB(dcb);
1172
1173 if (!bp->cmd_tbl.enable_disp_power_gating)
1174 return BP_RESULT_FAILURE;
1175
1176 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1177 action);
1178 }
1179
1180 static enum bp_result bios_parser_enable_lvtma_control(
1181 struct dc_bios *dcb,
1182 uint8_t uc_pwr_on)
1183 {
1184 struct bios_parser *bp = BP_FROM_DCB(dcb);
1185
1186 if (!bp->cmd_tbl.enable_lvtma_control)
1187 return BP_RESULT_FAILURE;
1188
1189 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on);
1190 }
1191
1192 static bool bios_parser_is_accelerated_mode(
1193 struct dc_bios *dcb)
1194 {
1195 return bios_is_accelerated_mode(dcb);
1196 }
1197
1198 /**
1199 * bios_parser_set_scratch_critical_state
1200 *
1201 * @brief
1202 * update critical state bit in VBIOS scratch register
1203 *
1204 * @param
1205 * bool - to set or reset state
1206 */
1207 static void bios_parser_set_scratch_critical_state(
1208 struct dc_bios *dcb,
1209 bool state)
1210 {
1211 bios_set_scratch_critical_state(dcb, state);
1212 }
1213
1214 static enum bp_result bios_parser_get_firmware_info(
1215 struct dc_bios *dcb,
1216 struct dc_firmware_info *info)
1217 {
1218 struct bios_parser *bp = BP_FROM_DCB(dcb);
1219 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1220 struct atom_common_table_header *header;
1221
1222 struct atom_data_revision revision;
1223
1224 if (info && DATA_TABLES(firmwareinfo)) {
1225 header = GET_IMAGE(struct atom_common_table_header,
1226 DATA_TABLES(firmwareinfo));
1227 get_atom_data_table_revision(header, &revision);
1228 switch (revision.major) {
1229 case 3:
1230 switch (revision.minor) {
1231 case 1:
1232 result = get_firmware_info_v3_1(bp, info);
1233 break;
1234 case 2:
1235 case 3:
1236 case 4:
1237 result = get_firmware_info_v3_2(bp, info);
1238 break;
1239 default:
1240 break;
1241 }
1242 break;
1243 default:
1244 break;
1245 }
1246 }
1247
1248 return result;
1249 }
1250
1251 static enum bp_result get_firmware_info_v3_1(
1252 struct bios_parser *bp,
1253 struct dc_firmware_info *info)
1254 {
1255 struct atom_firmware_info_v3_1 *firmware_info;
1256 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1257
1258 if (!info)
1259 return BP_RESULT_BADINPUT;
1260
1261 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1262 DATA_TABLES(firmwareinfo));
1263
1264 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1265 DATA_TABLES(dce_info));
1266
1267 if (!firmware_info || !dce_info)
1268 return BP_RESULT_BADBIOSTABLE;
1269
1270 memset(info, 0, sizeof(*info));
1271
1272 /* Pixel clock pll information. */
1273 /* We need to convert from 10KHz units into KHz units */
1274 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1275 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1276
1277 /* 27MHz for Vega10: */
1278 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1279
1280 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1281 if (info->pll_info.crystal_frequency == 0)
1282 info->pll_info.crystal_frequency = 27000;
1283 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1284 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1285 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1286
1287 /* Get GPU PLL VCO Clock */
1288
1289 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1290 /* VBIOS gives in 10KHz */
1291 info->smu_gpu_pll_output_freq =
1292 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1293 }
1294
1295 info->oem_i2c_present = false;
1296
1297 return BP_RESULT_OK;
1298 }
1299
1300 static enum bp_result get_firmware_info_v3_2(
1301 struct bios_parser *bp,
1302 struct dc_firmware_info *info)
1303 {
1304 struct atom_firmware_info_v3_2 *firmware_info;
1305 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1306 struct atom_common_table_header *header;
1307 struct atom_data_revision revision;
1308 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1309 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1310
1311 if (!info)
1312 return BP_RESULT_BADINPUT;
1313
1314 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1315 DATA_TABLES(firmwareinfo));
1316
1317 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1318 DATA_TABLES(dce_info));
1319
1320 if (!firmware_info || !dce_info)
1321 return BP_RESULT_BADBIOSTABLE;
1322
1323 memset(info, 0, sizeof(*info));
1324
1325 header = GET_IMAGE(struct atom_common_table_header,
1326 DATA_TABLES(smu_info));
1327 get_atom_data_table_revision(header, &revision);
1328
1329 if (revision.minor == 2) {
1330 /* Vega12 */
1331 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1332 DATA_TABLES(smu_info));
1333
1334 if (!smu_info_v3_2)
1335 return BP_RESULT_BADBIOSTABLE;
1336
1337 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1338 } else if (revision.minor == 3) {
1339 /* Vega20 */
1340 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1341 DATA_TABLES(smu_info));
1342
1343 if (!smu_info_v3_3)
1344 return BP_RESULT_BADBIOSTABLE;
1345
1346 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1347 }
1348
1349 // We need to convert from 10KHz units into KHz units.
1350 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1351
1352 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1353 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1354 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1355 if (info->pll_info.crystal_frequency == 0) {
1356 if (revision.minor == 2)
1357 info->pll_info.crystal_frequency = 27000;
1358 else if (revision.minor == 3)
1359 info->pll_info.crystal_frequency = 100000;
1360 }
1361 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1362 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1363 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1364
1365 /* Get GPU PLL VCO Clock */
1366 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1367 if (revision.minor == 2)
1368 info->smu_gpu_pll_output_freq =
1369 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1370 else if (revision.minor == 3)
1371 info->smu_gpu_pll_output_freq =
1372 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1373 }
1374
1375 if (firmware_info->board_i2c_feature_id == 0x2) {
1376 info->oem_i2c_present = true;
1377 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1378 } else {
1379 info->oem_i2c_present = false;
1380 }
1381
1382 return BP_RESULT_OK;
1383 }
1384
1385 static enum bp_result bios_parser_get_encoder_cap_info(
1386 struct dc_bios *dcb,
1387 struct graphics_object_id object_id,
1388 struct bp_encoder_cap_info *info)
1389 {
1390 struct bios_parser *bp = BP_FROM_DCB(dcb);
1391 struct atom_display_object_path_v2 *object;
1392 struct atom_encoder_caps_record *record = NULL;
1393
1394 if (!info)
1395 return BP_RESULT_BADINPUT;
1396
1397 object = get_bios_object(bp, object_id);
1398
1399 if (!object)
1400 return BP_RESULT_BADINPUT;
1401
1402 record = get_encoder_cap_record(bp, object);
1403 if (!record)
1404 return BP_RESULT_NORECORD;
1405
1406 info->DP_HBR2_CAP = (record->encodercaps &
1407 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
1408 info->DP_HBR2_EN = (record->encodercaps &
1409 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
1410 info->DP_HBR3_EN = (record->encodercaps &
1411 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
1412 info->HDMI_6GB_EN = (record->encodercaps &
1413 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
1414 info->DP_IS_USB_C = (record->encodercaps &
1415 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
1416
1417 return BP_RESULT_OK;
1418 }
1419
1420
1421 static struct atom_encoder_caps_record *get_encoder_cap_record(
1422 struct bios_parser *bp,
1423 struct atom_display_object_path_v2 *object)
1424 {
1425 struct atom_common_record_header *header;
1426 uint32_t offset;
1427
1428 if (!object) {
1429 BREAK_TO_DEBUGGER(); /* Invalid object */
1430 return NULL;
1431 }
1432
1433 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
1434
1435 for (;;) {
1436 header = GET_IMAGE(struct atom_common_record_header, offset);
1437
1438 if (!header)
1439 return NULL;
1440
1441 offset += header->record_size;
1442
1443 if (header->record_type == LAST_RECORD_TYPE ||
1444 !header->record_size)
1445 break;
1446
1447 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
1448 continue;
1449
1450 if (sizeof(struct atom_encoder_caps_record) <=
1451 header->record_size)
1452 return (struct atom_encoder_caps_record *)header;
1453 }
1454
1455 return NULL;
1456 }
1457
1458 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
1459 struct bios_parser *bp,
1460 struct atom_display_object_path_v2 *object)
1461 {
1462 struct atom_common_record_header *header;
1463 uint32_t offset;
1464
1465 if (!object) {
1466 BREAK_TO_DEBUGGER(); /* Invalid object */
1467 return NULL;
1468 }
1469
1470 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
1471
1472 for (;;) {
1473 header = GET_IMAGE(struct atom_common_record_header, offset);
1474
1475 if (!header)
1476 return NULL;
1477
1478 offset += header->record_size;
1479
1480 if (header->record_type == LAST_RECORD_TYPE ||
1481 !header->record_size)
1482 break;
1483
1484 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE)
1485 continue;
1486
1487 if (sizeof(struct atom_disp_connector_caps_record) <=
1488 header->record_size)
1489 return (struct atom_disp_connector_caps_record *)header;
1490 }
1491
1492 return NULL;
1493 }
1494
1495 static enum bp_result bios_parser_get_disp_connector_caps_info(
1496 struct dc_bios *dcb,
1497 struct graphics_object_id object_id,
1498 struct bp_disp_connector_caps_info *info)
1499 {
1500 struct bios_parser *bp = BP_FROM_DCB(dcb);
1501 struct atom_display_object_path_v2 *object;
1502 struct atom_disp_connector_caps_record *record = NULL;
1503
1504 if (!info)
1505 return BP_RESULT_BADINPUT;
1506
1507 object = get_bios_object(bp, object_id);
1508
1509 if (!object)
1510 return BP_RESULT_BADINPUT;
1511
1512 record = get_disp_connector_caps_record(bp, object);
1513 if (!record)
1514 return BP_RESULT_NORECORD;
1515
1516 info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
1517 ? 1 : 0;
1518 info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
1519 ? 1 : 0;
1520
1521 return BP_RESULT_OK;
1522 }
1523
1524 static enum bp_result get_vram_info_v23(
1525 struct bios_parser *bp,
1526 struct dc_vram_info *info)
1527 {
1528 struct atom_vram_info_header_v2_3 *info_v23;
1529 enum bp_result result = BP_RESULT_OK;
1530
1531 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
1532 DATA_TABLES(vram_info));
1533
1534 if (info_v23 == NULL)
1535 return BP_RESULT_BADBIOSTABLE;
1536
1537 info->num_chans = info_v23->vram_module[0].channel_num;
1538 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
1539
1540 return result;
1541 }
1542
1543 static enum bp_result get_vram_info_v24(
1544 struct bios_parser *bp,
1545 struct dc_vram_info *info)
1546 {
1547 struct atom_vram_info_header_v2_4 *info_v24;
1548 enum bp_result result = BP_RESULT_OK;
1549
1550 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
1551 DATA_TABLES(vram_info));
1552
1553 if (info_v24 == NULL)
1554 return BP_RESULT_BADBIOSTABLE;
1555
1556 info->num_chans = info_v24->vram_module[0].channel_num;
1557 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
1558
1559 return result;
1560 }
1561
1562 static enum bp_result get_vram_info_v25(
1563 struct bios_parser *bp,
1564 struct dc_vram_info *info)
1565 {
1566 struct atom_vram_info_header_v2_5 *info_v25;
1567 enum bp_result result = BP_RESULT_OK;
1568
1569 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
1570 DATA_TABLES(vram_info));
1571
1572 if (info_v25 == NULL)
1573 return BP_RESULT_BADBIOSTABLE;
1574
1575 info->num_chans = info_v25->vram_module[0].channel_num;
1576 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
1577
1578 return result;
1579 }
1580
1581 /*
1582 * get_integrated_info_v11
1583 *
1584 * @brief
1585 * Get V8 integrated BIOS information
1586 *
1587 * @param
1588 * bios_parser *bp - [in]BIOS parser handler to get master data table
1589 * integrated_info *info - [out] store and output integrated info
1590 *
1591 * @return
1592 * enum bp_result - BP_RESULT_OK if information is available,
1593 * BP_RESULT_BADBIOSTABLE otherwise.
1594 */
1595 static enum bp_result get_integrated_info_v11(
1596 struct bios_parser *bp,
1597 struct integrated_info *info)
1598 {
1599 struct atom_integrated_system_info_v1_11 *info_v11;
1600 uint32_t i;
1601
1602 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
1603 DATA_TABLES(integratedsysteminfo));
1604
1605 if (info_v11 == NULL)
1606 return BP_RESULT_BADBIOSTABLE;
1607
1608 info->gpu_cap_info =
1609 le32_to_cpu(info_v11->gpucapinfo);
1610 /*
1611 * system_config: Bit[0] = 0 : PCIE power gating disabled
1612 * = 1 : PCIE power gating enabled
1613 * Bit[1] = 0 : DDR-PLL shut down disabled
1614 * = 1 : DDR-PLL shut down enabled
1615 * Bit[2] = 0 : DDR-PLL power down disabled
1616 * = 1 : DDR-PLL power down enabled
1617 */
1618 info->system_config = le32_to_cpu(info_v11->system_config);
1619 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
1620 info->memory_type = info_v11->memorytype;
1621 info->ma_channel_number = info_v11->umachannelnumber;
1622 info->lvds_ss_percentage =
1623 le16_to_cpu(info_v11->lvds_ss_percentage);
1624 info->dp_ss_control =
1625 le16_to_cpu(info_v11->reserved1);
1626 info->lvds_sspread_rate_in_10hz =
1627 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
1628 info->hdmi_ss_percentage =
1629 le16_to_cpu(info_v11->hdmi_ss_percentage);
1630 info->hdmi_sspread_rate_in_10hz =
1631 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
1632 info->dvi_ss_percentage =
1633 le16_to_cpu(info_v11->dvi_ss_percentage);
1634 info->dvi_sspread_rate_in_10_hz =
1635 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
1636 info->lvds_misc = info_v11->lvds_misc;
1637 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1638 info->ext_disp_conn_info.gu_id[i] =
1639 info_v11->extdispconninfo.guid[i];
1640 }
1641
1642 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1643 info->ext_disp_conn_info.path[i].device_connector_id =
1644 object_id_from_bios_object_id(
1645 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
1646
1647 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1648 object_id_from_bios_object_id(
1649 le16_to_cpu(
1650 info_v11->extdispconninfo.path[i].ext_encoder_objid));
1651
1652 info->ext_disp_conn_info.path[i].device_tag =
1653 le16_to_cpu(
1654 info_v11->extdispconninfo.path[i].device_tag);
1655 info->ext_disp_conn_info.path[i].device_acpi_enum =
1656 le16_to_cpu(
1657 info_v11->extdispconninfo.path[i].device_acpi_enum);
1658 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1659 info_v11->extdispconninfo.path[i].auxddclut_index;
1660 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1661 info_v11->extdispconninfo.path[i].hpdlut_index;
1662 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1663 info_v11->extdispconninfo.path[i].channelmapping;
1664 info->ext_disp_conn_info.path[i].caps =
1665 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
1666 }
1667 info->ext_disp_conn_info.checksum =
1668 info_v11->extdispconninfo.checksum;
1669
1670 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
1671 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
1672 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1673 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1674 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1675 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1676 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1677 }
1678 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
1679 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1680 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1681 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1682 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1683 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1684 }
1685
1686 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
1687 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
1688 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1689 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1690 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1691 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1692 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1693 }
1694 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
1695 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1696 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1697 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1698 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1699 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1700 }
1701
1702 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
1703 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
1704 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1705 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1706 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1707 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1708 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1709 }
1710 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
1711 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1712 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1713 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1714 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1715 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1716 }
1717
1718 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
1719 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
1720 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1721 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1722 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1723 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1724 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1725 }
1726 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
1727 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1728 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1729 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1730 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1731 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1732 }
1733
1734
1735 /** TODO - review **/
1736 #if 0
1737 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
1738 * 10;
1739 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
1740 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
1741
1742 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1743 /* Convert [10KHz] into [KHz] */
1744 info->disp_clk_voltage[i].max_supported_clk =
1745 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
1746 ulMaximumSupportedCLK) * 10;
1747 info->disp_clk_voltage[i].voltage_index =
1748 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
1749 }
1750
1751 info->boot_up_req_display_vector =
1752 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
1753 info->boot_up_nb_voltage =
1754 le16_to_cpu(info_v11->usBootUpNBVoltage);
1755 info->ext_disp_conn_info_offset =
1756 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
1757 info->gmc_restore_reset_time =
1758 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
1759 info->minimum_n_clk =
1760 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
1761 for (i = 1; i < 4; ++i)
1762 info->minimum_n_clk =
1763 info->minimum_n_clk <
1764 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
1765 info->minimum_n_clk : le32_to_cpu(
1766 info_v11->ulNbpStateNClkFreq[i]);
1767
1768 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
1769 info->ddr_dll_power_up_time =
1770 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
1771 info->ddr_pll_power_up_time =
1772 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
1773 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
1774 info->max_lvds_pclk_freq_in_single_link =
1775 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1776 info->max_lvds_pclk_freq_in_single_link =
1777 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1778 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
1779 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
1780 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
1781 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
1782 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
1783 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
1784 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
1785 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
1786 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
1787 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
1788 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
1789 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
1790 info->lvds_off_to_on_delay_in_4ms =
1791 info_v11->ucLVDSOffToOnDelay_in4Ms;
1792 info->lvds_bit_depth_control_val =
1793 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
1794
1795 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
1796 /* Convert [10KHz] into [KHz] */
1797 info->avail_s_clk[i].supported_s_clk =
1798 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
1799 * 10;
1800 info->avail_s_clk[i].voltage_index =
1801 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
1802 info->avail_s_clk[i].voltage_id =
1803 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
1804 }
1805 #endif /* TODO*/
1806
1807 return BP_RESULT_OK;
1808 }
1809
1810 static enum bp_result get_integrated_info_v2_1(
1811 struct bios_parser *bp,
1812 struct integrated_info *info)
1813 {
1814 struct atom_integrated_system_info_v2_1 *info_v2_1;
1815 uint32_t i;
1816
1817 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
1818 DATA_TABLES(integratedsysteminfo));
1819
1820 if (info_v2_1 == NULL)
1821 return BP_RESULT_BADBIOSTABLE;
1822
1823 info->gpu_cap_info =
1824 le32_to_cpu(info_v2_1->gpucapinfo);
1825 /*
1826 * system_config: Bit[0] = 0 : PCIE power gating disabled
1827 * = 1 : PCIE power gating enabled
1828 * Bit[1] = 0 : DDR-PLL shut down disabled
1829 * = 1 : DDR-PLL shut down enabled
1830 * Bit[2] = 0 : DDR-PLL power down disabled
1831 * = 1 : DDR-PLL power down enabled
1832 */
1833 info->system_config = le32_to_cpu(info_v2_1->system_config);
1834 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
1835 info->memory_type = info_v2_1->memorytype;
1836 info->ma_channel_number = info_v2_1->umachannelnumber;
1837 info->dp_ss_control =
1838 le16_to_cpu(info_v2_1->reserved1);
1839
1840 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1841 info->ext_disp_conn_info.gu_id[i] =
1842 info_v2_1->extdispconninfo.guid[i];
1843 }
1844
1845 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1846 info->ext_disp_conn_info.path[i].device_connector_id =
1847 object_id_from_bios_object_id(
1848 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
1849
1850 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1851 object_id_from_bios_object_id(
1852 le16_to_cpu(
1853 info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
1854
1855 info->ext_disp_conn_info.path[i].device_tag =
1856 le16_to_cpu(
1857 info_v2_1->extdispconninfo.path[i].device_tag);
1858 info->ext_disp_conn_info.path[i].device_acpi_enum =
1859 le16_to_cpu(
1860 info_v2_1->extdispconninfo.path[i].device_acpi_enum);
1861 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1862 info_v2_1->extdispconninfo.path[i].auxddclut_index;
1863 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1864 info_v2_1->extdispconninfo.path[i].hpdlut_index;
1865 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1866 info_v2_1->extdispconninfo.path[i].channelmapping;
1867 info->ext_disp_conn_info.path[i].caps =
1868 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
1869 }
1870
1871 info->ext_disp_conn_info.checksum =
1872 info_v2_1->extdispconninfo.checksum;
1873 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
1874 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
1875 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1876 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1877 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1878 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1879 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1880 }
1881 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
1882 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1883 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1884 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1885 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1886 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1887 }
1888 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
1889 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
1890 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1891 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1892 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1893 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1894 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1895 }
1896 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
1897 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1898 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1899 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1900 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1901 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1902 }
1903 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
1904 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
1905 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1906 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1907 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1908 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1909 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1910 }
1911 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
1912 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1913 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1914 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1915 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1916 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1917 }
1918 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
1919 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
1920 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1921 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1922 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1923 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1924 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1925 }
1926 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
1927 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1928 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1929 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1930 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1931 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1932 }
1933
1934 info->edp1_info.edp_backlight_pwm_hz =
1935 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
1936 info->edp1_info.edp_ss_percentage =
1937 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
1938 info->edp1_info.edp_ss_rate_10hz =
1939 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
1940 info->edp1_info.edp_pwr_on_off_delay =
1941 info_v2_1->edp1_info.edp_pwr_on_off_delay;
1942 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
1943 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
1944 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
1945 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
1946 info->edp1_info.edp_panel_bpc =
1947 info_v2_1->edp1_info.edp_panel_bpc;
1948 info->edp1_info.edp_bootup_bl_level =
1949
1950 info->edp2_info.edp_backlight_pwm_hz =
1951 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
1952 info->edp2_info.edp_ss_percentage =
1953 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
1954 info->edp2_info.edp_ss_rate_10hz =
1955 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
1956 info->edp2_info.edp_pwr_on_off_delay =
1957 info_v2_1->edp2_info.edp_pwr_on_off_delay;
1958 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
1959 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
1960 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
1961 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
1962 info->edp2_info.edp_panel_bpc =
1963 info_v2_1->edp2_info.edp_panel_bpc;
1964 info->edp2_info.edp_bootup_bl_level =
1965 info_v2_1->edp2_info.edp_bootup_bl_level;
1966
1967 return BP_RESULT_OK;
1968 }
1969
1970 /*
1971 * construct_integrated_info
1972 *
1973 * @brief
1974 * Get integrated BIOS information based on table revision
1975 *
1976 * @param
1977 * bios_parser *bp - [in]BIOS parser handler to get master data table
1978 * integrated_info *info - [out] store and output integrated info
1979 *
1980 * @return
1981 * enum bp_result - BP_RESULT_OK if information is available,
1982 * BP_RESULT_BADBIOSTABLE otherwise.
1983 */
1984 static enum bp_result construct_integrated_info(
1985 struct bios_parser *bp,
1986 struct integrated_info *info)
1987 {
1988 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1989
1990 struct atom_common_table_header *header;
1991 struct atom_data_revision revision;
1992 uint32_t i;
1993 uint32_t j;
1994
1995 if (info && DATA_TABLES(integratedsysteminfo)) {
1996 header = GET_IMAGE(struct atom_common_table_header,
1997 DATA_TABLES(integratedsysteminfo));
1998
1999 get_atom_data_table_revision(header, &revision);
2000
2001 switch (revision.major) {
2002 case 1:
2003 switch (revision.minor) {
2004 case 11:
2005 case 12:
2006 result = get_integrated_info_v11(bp, info);
2007 break;
2008 default:
2009 return result;
2010 }
2011 break;
2012 case 2:
2013 switch (revision.minor) {
2014 case 1:
2015 result = get_integrated_info_v2_1(bp, info);
2016 break;
2017 default:
2018 return result;
2019 }
2020 break;
2021 default:
2022 return result;
2023 }
2024 }
2025
2026 if (result != BP_RESULT_OK)
2027 return result;
2028
2029 /* Sort voltage table from low to high*/
2030 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
2031 for (j = i; j > 0; --j) {
2032 if (info->disp_clk_voltage[j].max_supported_clk <
2033 info->disp_clk_voltage[j-1].max_supported_clk
2034 ) {
2035 /* swap j and j - 1*/
2036 swap(info->disp_clk_voltage[j - 1],
2037 info->disp_clk_voltage[j]);
2038 }
2039 }
2040 }
2041
2042 return result;
2043 }
2044
2045 static enum bp_result bios_parser_get_vram_info(
2046 struct dc_bios *dcb,
2047 struct dc_vram_info *info)
2048 {
2049 struct bios_parser *bp = BP_FROM_DCB(dcb);
2050 enum bp_result result = BP_RESULT_BADBIOSTABLE;
2051 struct atom_common_table_header *header;
2052 struct atom_data_revision revision;
2053
2054 if (info && DATA_TABLES(vram_info)) {
2055 header = GET_IMAGE(struct atom_common_table_header,
2056 DATA_TABLES(vram_info));
2057
2058 get_atom_data_table_revision(header, &revision);
2059
2060 switch (revision.major) {
2061 case 2:
2062 switch (revision.minor) {
2063 case 3:
2064 result = get_vram_info_v23(bp, info);
2065 break;
2066 case 4:
2067 result = get_vram_info_v24(bp, info);
2068 break;
2069 case 5:
2070 result = get_vram_info_v25(bp, info);
2071 break;
2072 default:
2073 break;
2074 }
2075 break;
2076
2077 default:
2078 return result;
2079 }
2080
2081 }
2082 return result;
2083 }
2084
2085 static struct integrated_info *bios_parser_create_integrated_info(
2086 struct dc_bios *dcb)
2087 {
2088 struct bios_parser *bp = BP_FROM_DCB(dcb);
2089 struct integrated_info *info = NULL;
2090
2091 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
2092
2093 if (info == NULL) {
2094 ASSERT_CRITICAL(0);
2095 return NULL;
2096 }
2097
2098 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
2099 return info;
2100
2101 kfree(info);
2102
2103 return NULL;
2104 }
2105
2106 static enum bp_result update_slot_layout_info(
2107 struct dc_bios *dcb,
2108 unsigned int i,
2109 struct slot_layout_info *slot_layout_info)
2110 {
2111 unsigned int record_offset;
2112 unsigned int j;
2113 struct atom_display_object_path_v2 *object;
2114 struct atom_bracket_layout_record *record;
2115 struct atom_common_record_header *record_header;
2116 enum bp_result result;
2117 struct bios_parser *bp;
2118 struct object_info_table *tbl;
2119 struct display_object_info_table_v1_4 *v1_4;
2120
2121 record = NULL;
2122 record_header = NULL;
2123 result = BP_RESULT_NORECORD;
2124
2125 bp = BP_FROM_DCB(dcb);
2126 tbl = &bp->object_info_tbl;
2127 v1_4 = tbl->v1_4;
2128
2129 object = &v1_4->display_path[i];
2130 record_offset = (unsigned int)
2131 (object->disp_recordoffset) +
2132 (unsigned int)(bp->object_info_tbl_offset);
2133
2134 for (;;) {
2135
2136 record_header = (struct atom_common_record_header *)
2137 GET_IMAGE(struct atom_common_record_header,
2138 record_offset);
2139 if (record_header == NULL) {
2140 result = BP_RESULT_BADBIOSTABLE;
2141 break;
2142 }
2143
2144 /* the end of the list */
2145 if (record_header->record_type == 0xff ||
2146 record_header->record_size == 0) {
2147 break;
2148 }
2149
2150 if (record_header->record_type ==
2151 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
2152 sizeof(struct atom_bracket_layout_record)
2153 <= record_header->record_size) {
2154 record = (struct atom_bracket_layout_record *)
2155 (record_header);
2156 result = BP_RESULT_OK;
2157 break;
2158 }
2159
2160 record_offset += record_header->record_size;
2161 }
2162
2163 /* return if the record not found */
2164 if (result != BP_RESULT_OK)
2165 return result;
2166
2167 /* get slot sizes */
2168 slot_layout_info->length = record->bracketlen;
2169 slot_layout_info->width = record->bracketwidth;
2170
2171 /* get info for each connector in the slot */
2172 slot_layout_info->num_of_connectors = record->conn_num;
2173 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
2174 slot_layout_info->connectors[j].connector_type =
2175 (enum connector_layout_type)
2176 (record->conn_info[j].connector_type);
2177 switch (record->conn_info[j].connector_type) {
2178 case CONNECTOR_TYPE_DVI_D:
2179 slot_layout_info->connectors[j].connector_type =
2180 CONNECTOR_LAYOUT_TYPE_DVI_D;
2181 slot_layout_info->connectors[j].length =
2182 CONNECTOR_SIZE_DVI;
2183 break;
2184
2185 case CONNECTOR_TYPE_HDMI:
2186 slot_layout_info->connectors[j].connector_type =
2187 CONNECTOR_LAYOUT_TYPE_HDMI;
2188 slot_layout_info->connectors[j].length =
2189 CONNECTOR_SIZE_HDMI;
2190 break;
2191
2192 case CONNECTOR_TYPE_DISPLAY_PORT:
2193 slot_layout_info->connectors[j].connector_type =
2194 CONNECTOR_LAYOUT_TYPE_DP;
2195 slot_layout_info->connectors[j].length =
2196 CONNECTOR_SIZE_DP;
2197 break;
2198
2199 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
2200 slot_layout_info->connectors[j].connector_type =
2201 CONNECTOR_LAYOUT_TYPE_MINI_DP;
2202 slot_layout_info->connectors[j].length =
2203 CONNECTOR_SIZE_MINI_DP;
2204 break;
2205
2206 default:
2207 slot_layout_info->connectors[j].connector_type =
2208 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
2209 slot_layout_info->connectors[j].length =
2210 CONNECTOR_SIZE_UNKNOWN;
2211 }
2212
2213 slot_layout_info->connectors[j].position =
2214 record->conn_info[j].position;
2215 slot_layout_info->connectors[j].connector_id =
2216 object_id_from_bios_object_id(
2217 record->conn_info[j].connectorobjid);
2218 }
2219 return result;
2220 }
2221
2222
2223 static enum bp_result get_bracket_layout_record(
2224 struct dc_bios *dcb,
2225 unsigned int bracket_layout_id,
2226 struct slot_layout_info *slot_layout_info)
2227 {
2228 unsigned int i;
2229 struct bios_parser *bp = BP_FROM_DCB(dcb);
2230 enum bp_result result;
2231 struct object_info_table *tbl;
2232 struct display_object_info_table_v1_4 *v1_4;
2233
2234 if (slot_layout_info == NULL) {
2235 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
2236 return BP_RESULT_BADINPUT;
2237 }
2238 tbl = &bp->object_info_tbl;
2239 v1_4 = tbl->v1_4;
2240
2241 result = BP_RESULT_NORECORD;
2242 for (i = 0; i < v1_4->number_of_path; ++i) {
2243
2244 if (bracket_layout_id ==
2245 v1_4->display_path[i].display_objid) {
2246 result = update_slot_layout_info(dcb, i,
2247 slot_layout_info);
2248 break;
2249 }
2250 }
2251 return result;
2252 }
2253
2254 static enum bp_result bios_get_board_layout_info(
2255 struct dc_bios *dcb,
2256 struct board_layout_info *board_layout_info)
2257 {
2258 unsigned int i;
2259 enum bp_result record_result;
2260
2261 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
2262 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
2263 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
2264 0, 0
2265 };
2266
2267 if (board_layout_info == NULL) {
2268 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
2269 return BP_RESULT_BADINPUT;
2270 }
2271
2272 board_layout_info->num_of_slots = 0;
2273
2274 for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
2275 record_result = get_bracket_layout_record(dcb,
2276 slot_index_to_vbios_id[i],
2277 &board_layout_info->slots[i]);
2278
2279 if (record_result == BP_RESULT_NORECORD && i > 0)
2280 break; /* no more slots present in bios */
2281 else if (record_result != BP_RESULT_OK)
2282 return record_result; /* fail */
2283
2284 ++board_layout_info->num_of_slots;
2285 }
2286
2287 /* all data is valid */
2288 board_layout_info->is_number_of_slots_valid = 1;
2289 board_layout_info->is_slots_size_valid = 1;
2290 board_layout_info->is_connector_offsets_valid = 1;
2291 board_layout_info->is_connector_lengths_valid = 1;
2292
2293 return BP_RESULT_OK;
2294 }
2295
2296
2297 static uint16_t bios_parser_pack_data_tables(
2298 struct dc_bios *dcb,
2299 void *dst)
2300 {
2301 #ifdef PACK_BIOS_DATA
2302 struct bios_parser *bp = BP_FROM_DCB(dcb);
2303 struct atom_rom_header_v2_2 *rom_header = NULL;
2304 struct atom_rom_header_v2_2 *packed_rom_header = NULL;
2305 struct atom_common_table_header *data_tbl_header = NULL;
2306 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL;
2307 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL;
2308 struct atom_data_revision tbl_rev = {0};
2309 uint16_t *rom_header_offset = NULL;
2310 const uint8_t *bios = bp->base.bios;
2311 uint8_t *bios_dst = (uint8_t *)dst;
2312 uint16_t packed_rom_header_offset;
2313 uint16_t packed_masterdatatable_offset;
2314 uint16_t packed_data_tbl_offset;
2315 uint16_t data_tbl_offset;
2316 unsigned int i;
2317
2318 rom_header_offset =
2319 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2320
2321 if (!rom_header_offset)
2322 return 0;
2323
2324 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
2325
2326 if (!rom_header)
2327 return 0;
2328
2329 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
2330 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
2331 return 0;
2332
2333 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev);
2334 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1))
2335 return 0;
2336
2337 packed_rom_header_offset =
2338 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset);
2339
2340 packed_masterdatatable_offset =
2341 packed_rom_header_offset + rom_header->table_header.structuresize;
2342
2343 packed_data_tbl_offset =
2344 packed_masterdatatable_offset +
2345 bp->master_data_tbl->table_header.structuresize;
2346
2347 packed_rom_header =
2348 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset);
2349
2350 packed_master_data_tbl =
2351 (struct atom_master_data_table_v2_1 *)(bios_dst +
2352 packed_masterdatatable_offset);
2353
2354 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2355
2356 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) =
2357 packed_rom_header_offset;
2358
2359 memcpy(bios_dst + packed_rom_header_offset, rom_header,
2360 rom_header->table_header.structuresize);
2361
2362 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset;
2363
2364 memcpy(&packed_master_data_tbl->table_header,
2365 &bp->master_data_tbl->table_header,
2366 sizeof(bp->master_data_tbl->table_header));
2367
2368 data_tbl_list = &bp->master_data_tbl->listOfdatatables;
2369
2370 /* Each data table offset in data table list is 2 bytes,
2371 * we can use that to iterate through listOfdatatables
2372 * without knowing the name of each member.
2373 */
2374 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) {
2375 data_tbl_offset = *((uint16_t *)data_tbl_list + i);
2376
2377 if (data_tbl_offset) {
2378 data_tbl_header =
2379 (struct atom_common_table_header *)(bios + data_tbl_offset);
2380
2381 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header,
2382 data_tbl_header->structuresize);
2383
2384 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) =
2385 packed_data_tbl_offset;
2386
2387 packed_data_tbl_offset += data_tbl_header->structuresize;
2388 } else {
2389 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0;
2390 }
2391 }
2392 return packed_data_tbl_offset;
2393 #endif
2394 // TODO: There is data bytes alignment issue, disable it for now.
2395 return 0;
2396 }
2397
2398 static struct atom_dc_golden_table_v1 *bios_get_golden_table(
2399 struct bios_parser *bp,
2400 uint32_t rev_major,
2401 uint32_t rev_minor,
2402 uint16_t *dc_golden_table_ver)
2403 {
2404 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;
2405 uint32_t dc_golden_offset = 0;
2406 *dc_golden_table_ver = 0;
2407
2408 if (!DATA_TABLES(dce_info))
2409 return NULL;
2410
2411 /* ver.4.4 or higher */
2412 switch (rev_major) {
2413 case 4:
2414 switch (rev_minor) {
2415 case 4:
2416 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
2417 DATA_TABLES(dce_info));
2418 if (!disp_cntl_tbl_4_4)
2419 return NULL;
2420 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
2421 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
2422 break;
2423 }
2424 break;
2425 }
2426
2427 if (!dc_golden_offset)
2428 return NULL;
2429
2430 if (*dc_golden_table_ver != 1)
2431 return NULL;
2432
2433 return GET_IMAGE(struct atom_dc_golden_table_v1,
2434 dc_golden_offset);
2435 }
2436
2437 static enum bp_result bios_get_atom_dc_golden_table(
2438 struct dc_bios *dcb)
2439 {
2440 struct bios_parser *bp = BP_FROM_DCB(dcb);
2441 enum bp_result result = BP_RESULT_OK;
2442 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;
2443 struct atom_common_table_header *header;
2444 struct atom_data_revision tbl_revision;
2445 uint16_t dc_golden_table_ver = 0;
2446
2447 header = GET_IMAGE(struct atom_common_table_header,
2448 DATA_TABLES(dce_info));
2449 if (!header)
2450 return BP_RESULT_UNSUPPORTED;
2451
2452 get_atom_data_table_revision(header, &tbl_revision);
2453
2454 atom_dc_golden_table = bios_get_golden_table(bp,
2455 tbl_revision.major,
2456 tbl_revision.minor,
2457 &dc_golden_table_ver);
2458
2459 if (!atom_dc_golden_table)
2460 return BP_RESULT_UNSUPPORTED;
2461
2462 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;
2463 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;
2464 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;
2465 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;
2466 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;
2467 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;
2468 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;
2469 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;
2470 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;
2471 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;
2472
2473 return result;
2474 }
2475
2476
2477 static const struct dc_vbios_funcs vbios_funcs = {
2478 .get_connectors_number = bios_parser_get_connectors_number,
2479
2480 .get_connector_id = bios_parser_get_connector_id,
2481
2482 .get_src_obj = bios_parser_get_src_obj,
2483
2484 .get_i2c_info = bios_parser_get_i2c_info,
2485
2486 .get_hpd_info = bios_parser_get_hpd_info,
2487
2488 .get_device_tag = bios_parser_get_device_tag,
2489
2490 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
2491
2492 .get_ss_entry_number = bios_parser_get_ss_entry_number,
2493
2494 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
2495
2496 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
2497
2498 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
2499
2500 .is_device_id_supported = bios_parser_is_device_id_supported,
2501
2502 .is_accelerated_mode = bios_parser_is_accelerated_mode,
2503
2504 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
2505
2506
2507 /* COMMANDS */
2508 .encoder_control = bios_parser_encoder_control,
2509
2510 .transmitter_control = bios_parser_transmitter_control,
2511
2512 .enable_crtc = bios_parser_enable_crtc,
2513
2514 .set_pixel_clock = bios_parser_set_pixel_clock,
2515
2516 .set_dce_clock = bios_parser_set_dce_clock,
2517
2518 .program_crtc_timing = bios_parser_program_crtc_timing,
2519
2520 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
2521
2522 .bios_parser_destroy = firmware_parser_destroy,
2523
2524 .get_board_layout_info = bios_get_board_layout_info,
2525 .pack_data_tables = bios_parser_pack_data_tables,
2526
2527 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
2528
2529 .enable_lvtma_control = bios_parser_enable_lvtma_control,
2530
2531 .get_soc_bb_info = bios_parser_get_soc_bb_info,
2532
2533 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
2534 };
2535
2536 static bool bios_parser2_construct(
2537 struct bios_parser *bp,
2538 struct bp_init_data *init,
2539 enum dce_version dce_version)
2540 {
2541 uint16_t *rom_header_offset = NULL;
2542 struct atom_rom_header_v2_2 *rom_header = NULL;
2543 struct display_object_info_table_v1_4 *object_info_tbl;
2544 struct atom_data_revision tbl_rev = {0};
2545
2546 if (!init)
2547 return false;
2548
2549 if (!init->bios)
2550 return false;
2551
2552 bp->base.funcs = &vbios_funcs;
2553 bp->base.bios = init->bios;
2554 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
2555
2556 bp->base.ctx = init->ctx;
2557
2558 bp->base.bios_local_image = NULL;
2559
2560 rom_header_offset =
2561 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2562
2563 if (!rom_header_offset)
2564 return false;
2565
2566 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
2567
2568 if (!rom_header)
2569 return false;
2570
2571 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
2572 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
2573 return false;
2574
2575 bp->master_data_tbl =
2576 GET_IMAGE(struct atom_master_data_table_v2_1,
2577 rom_header->masterdatatable_offset);
2578
2579 if (!bp->master_data_tbl)
2580 return false;
2581
2582 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
2583
2584 if (!bp->object_info_tbl_offset)
2585 return false;
2586
2587 object_info_tbl =
2588 GET_IMAGE(struct display_object_info_table_v1_4,
2589 bp->object_info_tbl_offset);
2590
2591 if (!object_info_tbl)
2592 return false;
2593
2594 get_atom_data_table_revision(&object_info_tbl->table_header,
2595 &bp->object_info_tbl.revision);
2596
2597 if (bp->object_info_tbl.revision.major == 1
2598 && bp->object_info_tbl.revision.minor >= 4) {
2599 struct display_object_info_table_v1_4 *tbl_v1_4;
2600
2601 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
2602 bp->object_info_tbl_offset);
2603 if (!tbl_v1_4)
2604 return false;
2605
2606 bp->object_info_tbl.v1_4 = tbl_v1_4;
2607 } else
2608 return false;
2609
2610 dal_firmware_parser_init_cmd_tbl(bp);
2611 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
2612
2613 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
2614 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
2615 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
2616
2617 return true;
2618 }
2619
2620 struct dc_bios *firmware_parser_create(
2621 struct bp_init_data *init,
2622 enum dce_version dce_version)
2623 {
2624 struct bios_parser *bp = NULL;
2625
2626 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
2627 if (!bp)
2628 return NULL;
2629
2630 if (bios_parser2_construct(bp, init, dce_version))
2631 return &bp->base;
2632
2633 kfree(bp);
2634 return NULL;
2635 }
2636
2637
Linux with added FPC-III support