WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dc_stream.h
blobb7910976b81a74ab2ef78bc39fae2fc112e98afd
1 /*
2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: AMD
26 #ifndef DC_STREAM_H_
27 #define DC_STREAM_H_
29 #include "dc_types.h"
30 #include "grph_object_defs.h"
32 /*******************************************************************************
33 * Stream Interfaces
34 ******************************************************************************/
35 struct timing_sync_info {
36 int group_id;
37 int group_size;
38 bool master;
41 struct dc_stream_status {
42 int primary_otg_inst;
43 int stream_enc_inst;
44 int plane_count;
45 int audio_inst;
46 struct timing_sync_info timing_sync_info;
47 struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
48 bool is_abm_supported;
51 // TODO: References to this needs to be removed..
52 struct freesync_context {
53 bool dummy;
56 enum hubp_dmdata_mode {
57 DMDATA_SW_MODE,
58 DMDATA_HW_MODE
61 struct dc_dmdata_attributes {
62 /* Specifies whether dynamic meta data will be updated by software
63 * or has to be fetched by hardware (DMA mode)
65 enum hubp_dmdata_mode dmdata_mode;
66 /* Specifies if current dynamic meta data is to be used only for the current frame */
67 bool dmdata_repeat;
68 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */
69 uint32_t dmdata_size;
70 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
71 bool dmdata_updated;
72 /* If hardware mode is used, the base address where DMDATA surface is located */
73 PHYSICAL_ADDRESS_LOC address;
74 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
75 bool dmdata_qos_mode;
76 /* If qos_mode = 1, this is the QOS value to be used: */
77 uint32_t dmdata_qos_level;
78 /* Specifies the value in unit of REFCLK cycles to be added to the
79 * current time to produce the Amortized deadline for Dynamic Metadata chunk request
81 uint32_t dmdata_dl_delta;
82 /* An unbounded array of uint32s, represents software dmdata to be loaded */
83 uint32_t *dmdata_sw_data;
86 struct dc_writeback_info {
87 bool wb_enabled;
88 int dwb_pipe_inst;
89 struct dc_dwb_params dwb_params;
90 struct mcif_buf_params mcif_buf_params;
91 struct mcif_warmup_params mcif_warmup_params;
92 /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */
93 struct dc_plane_state *writeback_source_plane;
94 /* source MPCC instance. for use by internally by dc */
95 int mpcc_inst;
98 struct dc_writeback_update {
99 unsigned int num_wb_info;
100 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
103 enum vertical_interrupt_ref_point {
104 START_V_UPDATE = 0,
105 START_V_SYNC,
106 INVALID_POINT
108 //For now, only v_update interrupt is used.
109 //START_V_BLANK,
110 //START_V_ACTIVE
113 struct periodic_interrupt_config {
114 enum vertical_interrupt_ref_point ref_point;
115 int lines_offset;
118 union stream_update_flags {
119 struct {
120 uint32_t scaling:1;
121 uint32_t out_tf:1;
122 uint32_t out_csc:1;
123 uint32_t abm_level:1;
124 uint32_t dpms_off:1;
125 uint32_t gamut_remap:1;
126 uint32_t wb_update:1;
127 uint32_t dsc_changed : 1;
128 } bits;
130 uint32_t raw;
133 struct dc_stream_state {
134 // sink is deprecated, new code should not reference
135 // this pointer
136 struct dc_sink *sink;
138 struct dc_link *link;
139 struct dc_panel_patch sink_patches;
140 union display_content_support content_support;
141 struct dc_crtc_timing timing;
142 struct dc_crtc_timing_adjust adjust;
143 struct dc_info_packet vrr_infopacket;
144 struct dc_info_packet vsc_infopacket;
145 struct dc_info_packet vsp_infopacket;
147 struct rect src; /* composition area */
148 struct rect dst; /* stream addressable area */
150 // TODO: References to this needs to be removed..
151 struct freesync_context freesync_ctx;
153 struct audio_info audio_info;
155 struct dc_info_packet hdr_static_metadata;
156 PHYSICAL_ADDRESS_LOC dmdata_address;
157 bool use_dynamic_meta;
159 struct dc_transfer_func *out_transfer_func;
160 struct colorspace_transform gamut_remap_matrix;
161 struct dc_csc_transform csc_color_matrix;
163 enum dc_color_space output_color_space;
164 enum dc_dither_option dither_option;
166 enum view_3d_format view_format;
168 bool use_vsc_sdp_for_colorimetry;
169 bool ignore_msa_timing_param;
170 bool converter_disable_audio;
171 uint8_t qs_bit;
172 uint8_t qy_bit;
174 /* TODO: custom INFO packets */
175 /* TODO: ABM info (DMCU) */
176 /* TODO: CEA VIC */
178 /* DMCU info */
179 unsigned int abm_level;
181 struct periodic_interrupt_config periodic_interrupt0;
182 struct periodic_interrupt_config periodic_interrupt1;
184 /* from core_stream struct */
185 struct dc_context *ctx;
187 /* used by DCP and FMT */
188 struct bit_depth_reduction_params bit_depth_params;
189 struct clamping_and_pixel_encoding_params clamping;
191 int phy_pix_clk;
192 enum signal_type signal;
193 bool dpms_off;
195 void *dm_stream_context;
197 struct dc_cursor_attributes cursor_attributes;
198 struct dc_cursor_position cursor_position;
199 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
201 /* from stream struct */
202 struct kref refcount;
204 struct crtc_trigger_info triggered_crtc_reset;
206 /* writeback */
207 unsigned int num_wb_info;
208 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
209 const struct dc_transfer_func *func_shaper;
210 const struct dc_3dlut *lut3d_func;
211 /* Computed state bits */
212 bool mode_changed : 1;
214 /* Output from DC when stream state is committed or altered
215 * DC may only access these values during:
216 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams
217 * values may not change outside of those calls
219 struct {
220 // For interrupt management, some hardware instance
221 // offsets need to be exposed to DM
222 uint8_t otg_offset;
223 } out;
225 bool apply_edp_fast_boot_optimization;
226 bool apply_seamless_boot_optimization;
228 uint32_t stream_id;
229 bool is_dsc_enabled;
230 union stream_update_flags update_flags;
233 #define ABM_LEVEL_IMMEDIATE_DISABLE 255
235 struct dc_stream_update {
236 struct dc_stream_state *stream;
238 struct rect src;
239 struct rect dst;
240 struct dc_transfer_func *out_transfer_func;
241 struct dc_info_packet *hdr_static_metadata;
242 unsigned int *abm_level;
244 struct periodic_interrupt_config *periodic_interrupt0;
245 struct periodic_interrupt_config *periodic_interrupt1;
247 struct dc_info_packet *vrr_infopacket;
248 struct dc_info_packet *vsc_infopacket;
249 struct dc_info_packet *vsp_infopacket;
251 bool *dpms_off;
252 bool integer_scaling_update;
254 struct colorspace_transform *gamut_remap;
255 enum dc_color_space *output_color_space;
256 enum dc_dither_option *dither_option;
258 struct dc_csc_transform *output_csc_transform;
260 struct dc_writeback_update *wb_update;
261 struct dc_dsc_config *dsc_config;
262 struct dc_transfer_func *func_shaper;
263 struct dc_3dlut *lut3d_func;
266 bool dc_is_stream_unchanged(
267 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
268 bool dc_is_stream_scaling_unchanged(
269 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
272 * Set up surface attributes and associate to a stream
273 * The surfaces parameter is an absolute set of all surface active for the stream.
274 * If no surfaces are provided, the stream will be blanked; no memory read.
275 * Any flip related attribute changes must be done through this interface.
277 * After this call:
278 * Surfaces attributes are programmed and configured to be composed into stream.
279 * This does not trigger a flip. No surface address is programmed.
282 void dc_commit_updates_for_stream(struct dc *dc,
283 struct dc_surface_update *srf_updates,
284 int surface_count,
285 struct dc_stream_state *stream,
286 struct dc_stream_update *stream_update,
287 struct dc_state *state);
289 * Log the current stream state.
291 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
293 uint8_t dc_get_current_stream_count(struct dc *dc);
294 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
295 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link);
298 * Return the current frame counter.
300 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
303 * Send dp sdp message.
305 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
306 const uint8_t *custom_sdp_message,
307 unsigned int sdp_message_size);
309 /* TODO: Return parsed values rather than direct register read
310 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos)
311 * being refactored properly to be dce-specific
313 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
314 uint32_t *v_blank_start,
315 uint32_t *v_blank_end,
316 uint32_t *h_position,
317 uint32_t *v_position);
319 enum dc_status dc_add_stream_to_ctx(
320 struct dc *dc,
321 struct dc_state *new_ctx,
322 struct dc_stream_state *stream);
324 enum dc_status dc_remove_stream_from_ctx(
325 struct dc *dc,
326 struct dc_state *new_ctx,
327 struct dc_stream_state *stream);
330 bool dc_add_plane_to_context(
331 const struct dc *dc,
332 struct dc_stream_state *stream,
333 struct dc_plane_state *plane_state,
334 struct dc_state *context);
336 bool dc_remove_plane_from_context(
337 const struct dc *dc,
338 struct dc_stream_state *stream,
339 struct dc_plane_state *plane_state,
340 struct dc_state *context);
342 bool dc_rem_all_planes_for_stream(
343 const struct dc *dc,
344 struct dc_stream_state *stream,
345 struct dc_state *context);
347 bool dc_add_all_planes_for_stream(
348 const struct dc *dc,
349 struct dc_stream_state *stream,
350 struct dc_plane_state * const *plane_states,
351 int plane_count,
352 struct dc_state *context);
354 bool dc_stream_add_writeback(struct dc *dc,
355 struct dc_stream_state *stream,
356 struct dc_writeback_info *wb_info);
358 bool dc_stream_remove_writeback(struct dc *dc,
359 struct dc_stream_state *stream,
360 uint32_t dwb_pipe_inst);
362 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
363 struct dc_state *state,
364 struct dc_stream_state *stream);
366 bool dc_stream_warmup_writeback(struct dc *dc,
367 int num_dwb,
368 struct dc_writeback_info *wb_info);
370 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
372 bool dc_stream_set_dynamic_metadata(struct dc *dc,
373 struct dc_stream_state *stream,
374 struct dc_dmdata_attributes *dmdata_attr);
376 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
379 * Set up streams and links associated to drive sinks
380 * The streams parameter is an absolute set of all active streams.
382 * After this call:
383 * Phy, Encoder, Timing Generator are programmed and enabled.
384 * New streams are enabled with blank stream; no memory read.
387 * Enable stereo when commit_streams is not required,
388 * for example, frame alternate.
390 void dc_enable_stereo(
391 struct dc *dc,
392 struct dc_state *context,
393 struct dc_stream_state *streams[],
394 uint8_t stream_count);
396 /* Triggers multi-stream synchronization. */
397 void dc_trigger_sync(struct dc *dc, struct dc_state *context);
399 enum surface_update_type dc_check_update_surfaces_for_stream(
400 struct dc *dc,
401 struct dc_surface_update *updates,
402 int surface_count,
403 struct dc_stream_update *stream_update,
404 const struct dc_stream_status *stream_status);
407 * Create a new default stream for the requested sink
409 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
411 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream);
413 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);
415 void dc_stream_retain(struct dc_stream_state *dc_stream);
416 void dc_stream_release(struct dc_stream_state *dc_stream);
418 struct dc_stream_status *dc_stream_get_status_from_state(
419 struct dc_state *state,
420 struct dc_stream_state *stream);
421 struct dc_stream_status *dc_stream_get_status(
422 struct dc_stream_state *dc_stream);
424 #ifndef TRIM_FSFT
425 bool dc_optimize_timing_for_fsft(
426 struct dc_stream_state *pStream,
427 unsigned int max_input_rate_in_khz);
428 #endif
430 /*******************************************************************************
431 * Cursor interfaces - To manages the cursor within a stream
432 ******************************************************************************/
433 /* TODO: Deprecated once we switch to dc_set_cursor_position */
434 bool dc_stream_set_cursor_attributes(
435 struct dc_stream_state *stream,
436 const struct dc_cursor_attributes *attributes);
438 bool dc_stream_set_cursor_position(
439 struct dc_stream_state *stream,
440 const struct dc_cursor_position *position);
443 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
444 struct dc_stream_state *stream,
445 struct dc_crtc_timing_adjust *adjust);
447 bool dc_stream_get_crtc_position(struct dc *dc,
448 struct dc_stream_state **stream,
449 int num_streams,
450 unsigned int *v_pos,
451 unsigned int *nom_v_pos);
453 bool dc_stream_configure_crc(struct dc *dc,
454 struct dc_stream_state *stream,
455 struct crc_params *crc_window,
456 bool enable,
457 bool continuous);
459 bool dc_stream_get_crc(struct dc *dc,
460 struct dc_stream_state *stream,
461 uint32_t *r_cr,
462 uint32_t *g_y,
463 uint32_t *b_cb);
465 void dc_stream_set_static_screen_params(struct dc *dc,
466 struct dc_stream_state **stream,
467 int num_streams,
468 const struct dc_static_screen_params *params);
470 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
471 enum dc_dynamic_expansion option);
473 void dc_stream_set_dither_option(struct dc_stream_state *stream,
474 enum dc_dither_option option);
476 bool dc_stream_set_gamut_remap(struct dc *dc,
477 const struct dc_stream_state *stream);
479 bool dc_stream_program_csc_matrix(struct dc *dc,
480 struct dc_stream_state *stream);
482 bool dc_stream_get_crtc_position(struct dc *dc,
483 struct dc_stream_state **stream,
484 int num_streams,
485 unsigned int *v_pos,
486 unsigned int *nom_v_pos);
488 #endif /* DC_STREAM_H_ */