drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

   1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19  * OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * Authors: AMD
  22  *
  23  */
  24
  25 #ifndef __DC_CLOCK_SOURCE_DCE_H__
  26 #define __DC_CLOCK_SOURCE_DCE_H__
  27
  28 #include "../inc/clock_source.h"
  29
  30 #define TO_DCE110_CLK_SRC(clk_src)\
  31         container_of(clk_src, struct dce110_clk_src, base)
  32
  33 #define CS_COMMON_REG_LIST_DCE_100_110(id) \
  34                 SRI(RESYNC_CNTL, PIXCLK, id), \
  35                 SRI(PLL_CNTL, BPHYC_PLL, id)
  36
  37 #define CS_COMMON_REG_LIST_DCE_80(id) \
  38                 SRI(RESYNC_CNTL, PIXCLK, id), \
  39                 SRI(PLL_CNTL, DCCG_PLL, id)
  40
  41 #define CS_COMMON_REG_LIST_DCE_112(id) \
  42                 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
  43
  44
  45 #define CS_SF(reg_name, field_name, post_fix)\
  46         .field_name = reg_name ## __ ## field_name ## post_fix
  47
  48 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
  49         CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
  50         CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
  51         CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
  52         CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
  53
  54 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
  55         CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
  56         CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
  57
  58 #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
  59                 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
  60                 SRII(PHASE, DP_DTO, 0),\
  61                 SRII(PHASE, DP_DTO, 1),\
  62                 SRII(PHASE, DP_DTO, 2),\
  63                 SRII(PHASE, DP_DTO, 3),\
  64                 SRII(PHASE, DP_DTO, 4),\
  65                 SRII(PHASE, DP_DTO, 5),\
  66                 SRII(MODULO, DP_DTO, 0),\
  67                 SRII(MODULO, DP_DTO, 1),\
  68                 SRII(MODULO, DP_DTO, 2),\
  69                 SRII(MODULO, DP_DTO, 3),\
  70                 SRII(MODULO, DP_DTO, 4),\
  71                 SRII(MODULO, DP_DTO, 5),\
  72                 SRII(PIXEL_RATE_CNTL, OTG, 0),\
  73                 SRII(PIXEL_RATE_CNTL, OTG, 1),\
  74                 SRII(PIXEL_RATE_CNTL, OTG, 2),\
  75                 SRII(PIXEL_RATE_CNTL, OTG, 3),\
  76                 SRII(PIXEL_RATE_CNTL, OTG, 4),\
  77                 SRII(PIXEL_RATE_CNTL, OTG, 5)
  78
  79 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
  80                 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
  81                 SRII(PHASE, DP_DTO, 0),\
  82                 SRII(PHASE, DP_DTO, 1),\
  83                 SRII(PHASE, DP_DTO, 2),\
  84                 SRII(PHASE, DP_DTO, 3),\
  85                 SRII(MODULO, DP_DTO, 0),\
  86                 SRII(MODULO, DP_DTO, 1),\
  87                 SRII(MODULO, DP_DTO, 2),\
  88                 SRII(MODULO, DP_DTO, 3),\
  89                 SRII(PIXEL_RATE_CNTL, OTG, 0),\
  90                 SRII(PIXEL_RATE_CNTL, OTG, 1),\
  91                 SRII(PIXEL_RATE_CNTL, OTG, 2),\
  92                 SRII(PIXEL_RATE_CNTL, OTG, 3)
  93
  94 #if defined(CONFIG_DRM_AMD_DC_DCN)
  95 #define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
  96                 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
  97                 SRII(PHASE, DP_DTO, 0),\
  98                 SRII(PHASE, DP_DTO, 1),\
  99                 SRII(PHASE, DP_DTO, 2),\
 100                 SRII(PHASE, DP_DTO, 3),\
 101                 SRII(MODULO, DP_DTO, 0),\
 102                 SRII(MODULO, DP_DTO, 1),\
 103                 SRII(MODULO, DP_DTO, 2),\
 104                 SRII(MODULO, DP_DTO, 3),\
 105                 SRII(PIXEL_RATE_CNTL, OTG, 0),\
 106                 SRII(PIXEL_RATE_CNTL, OTG, 1),\
 107                 SRII(PIXEL_RATE_CNTL, OTG, 2),\
 108                 SRII(PIXEL_RATE_CNTL, OTG, 3)
 109
 110 #define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \
 111                 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
 112                 SRII(PHASE, DP_DTO, 0),\
 113                 SRII(PHASE, DP_DTO, 1),\
 114                 SRII(PHASE, DP_DTO, 2),\
 115                 SRII(PHASE, DP_DTO, 3),\
 116                 SRII(MODULO, DP_DTO, 0),\
 117                 SRII(MODULO, DP_DTO, 1),\
 118                 SRII(MODULO, DP_DTO, 2),\
 119                 SRII(MODULO, DP_DTO, 3),\
 120                 SRII(PIXEL_RATE_CNTL, OTG, 0),\
 121                 SRII(PIXEL_RATE_CNTL, OTG, 1),\
 122                 SRII(PIXEL_RATE_CNTL, OTG, 2),\
 123                 SRII(PIXEL_RATE_CNTL, OTG, 3)
 124 #endif
 125
 126 #if defined(CONFIG_DRM_AMD_DC_DCN)
 127 #define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \
 128                 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
 129                 SRII(PHASE, DP_DTO, 0),\
 130                 SRII(PHASE, DP_DTO, 1),\
 131                 SRII(PHASE, DP_DTO, 2),\
 132                 SRII(PHASE, DP_DTO, 3),\
 133                 SRII(PHASE, DP_DTO, 4),\
 134                 SRII(MODULO, DP_DTO, 0),\
 135                 SRII(MODULO, DP_DTO, 1),\
 136                 SRII(MODULO, DP_DTO, 2),\
 137                 SRII(MODULO, DP_DTO, 3),\
 138                 SRII(MODULO, DP_DTO, 4),\
 139                 SRII(PIXEL_RATE_CNTL, OTG, 0),\
 140                 SRII(PIXEL_RATE_CNTL, OTG, 1),\
 141                 SRII(PIXEL_RATE_CNTL, OTG, 2),\
 142                 SRII(PIXEL_RATE_CNTL, OTG, 3),\
 143                 SRII(PIXEL_RATE_CNTL, OTG, 4)
 144
 145 #endif
 146 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
 147         CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
 148         CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
 149         CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
 150         CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
 151
 152 #if defined(CONFIG_DRM_AMD_DC_DCN)
 153
 154 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
 155                 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
 156                 SRII(PHASE, DP_DTO, 0),\
 157                 SRII(PHASE, DP_DTO, 1),\
 158                 SRII(PHASE, DP_DTO, 2),\
 159                 SRII(PHASE, DP_DTO, 3),\
 160                 SRII(MODULO, DP_DTO, 0),\
 161                 SRII(MODULO, DP_DTO, 1),\
 162                 SRII(MODULO, DP_DTO, 2),\
 163                 SRII(MODULO, DP_DTO, 3),\
 164                 SRII(PIXEL_RATE_CNTL, OTG, 0), \
 165                 SRII(PIXEL_RATE_CNTL, OTG, 1), \
 166                 SRII(PIXEL_RATE_CNTL, OTG, 2), \
 167                 SRII(PIXEL_RATE_CNTL, OTG, 3)
 168
 169 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
 170         CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
 171         CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
 172         CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
 173         CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
 174
 175 #endif
 176
 177 #define CS_REG_FIELD_LIST(type) \
 178         type PLL_REF_DIV_SRC; \
 179         type DCCG_DEEP_COLOR_CNTL1; \
 180         type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
 181         type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
 182         type PLL_POST_DIV_PIXCLK; \
 183         type PLL_REF_DIV; \
 184         type DP_DTO0_PHASE; \
 185         type DP_DTO0_MODULO; \
 186         type DP_DTO0_ENABLE;
 187
 188 struct dce110_clk_src_shift {
 189         CS_REG_FIELD_LIST(uint8_t)
 190 };
 191
 192 struct dce110_clk_src_mask{
 193         CS_REG_FIELD_LIST(uint32_t)
 194 };
 195
 196 struct dce110_clk_src_regs {
 197         uint32_t RESYNC_CNTL;
 198         uint32_t PIXCLK_RESYNC_CNTL;
 199         uint32_t PLL_CNTL;
 200
 201         /* below are for DTO.
 202          * todo: should probably use different struct to not waste space
 203          */
 204         uint32_t PHASE[MAX_PIPES];
 205         uint32_t MODULO[MAX_PIPES];
 206         uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
 207 };
 208
 209 struct dce110_clk_src {
 210         struct clock_source base;
 211         const struct dce110_clk_src_regs *regs;
 212         const struct dce110_clk_src_mask *cs_mask;
 213         const struct dce110_clk_src_shift *cs_shift;
 214         struct dc_bios *bios;
 215
 216         struct spread_spectrum_data *dp_ss_params;
 217         uint32_t dp_ss_params_cnt;
 218         struct spread_spectrum_data *hdmi_ss_params;
 219         uint32_t hdmi_ss_params_cnt;
 220         struct spread_spectrum_data *dvi_ss_params;
 221         uint32_t dvi_ss_params_cnt;
 222         struct spread_spectrum_data *lvds_ss_params;
 223         uint32_t lvds_ss_params_cnt;
 224
 225         uint32_t ext_clk_khz;
 226         uint32_t ref_freq_khz;
 227
 228         struct calc_pll_clock_source calc_pll;
 229         struct calc_pll_clock_source calc_pll_hdmi;
 230 };
 231
 232 bool dce110_clk_src_construct(
 233         struct dce110_clk_src *clk_src,
 234         struct dc_context *ctx,
 235         struct dc_bios *bios,
 236         enum clock_source_id,
 237         const struct dce110_clk_src_regs *regs,
 238         const struct dce110_clk_src_shift *cs_shift,
 239         const struct dce110_clk_src_mask *cs_mask);
 240
 241 bool dce112_clk_src_construct(
 242         struct dce110_clk_src *clk_src,
 243         struct dc_context *ctx,
 244         struct dc_bios *bios,
 245         enum clock_source_id id,
 246         const struct dce110_clk_src_regs *regs,
 247         const struct dce110_clk_src_shift *cs_shift,
 248         const struct dce110_clk_src_mask *cs_mask);
 249
 250 bool dcn20_clk_src_construct(
 251         struct dce110_clk_src *clk_src,
 252         struct dc_context *ctx,
 253         struct dc_bios *bios,
 254         enum clock_source_id id,
 255         const struct dce110_clk_src_regs *regs,
 256         const struct dce110_clk_src_shift *cs_shift,
 257         const struct dce110_clk_src_mask *cs_mask);
 258
 259 #if defined(CONFIG_DRM_AMD_DC_DCN)
 260 bool dcn3_clk_src_construct(
 261         struct dce110_clk_src *clk_src,
 262         struct dc_context *ctx,
 263         struct dc_bios *bios,
 264         enum clock_source_id id,
 265         const struct dce110_clk_src_regs *regs,
 266         const struct dce110_clk_src_shift *cs_shift,
 267         const struct dce110_clk_src_mask *cs_mask);
 268
 269 bool dcn301_clk_src_construct(
 270         struct dce110_clk_src *clk_src,
 271         struct dc_context *ctx,
 272         struct dc_bios *bios,
 273         enum clock_source_id id,
 274         const struct dce110_clk_src_regs *regs,
 275         const struct dce110_clk_src_shift *cs_shift,
 276         const struct dce110_clk_src_mask *cs_mask);
 277 #endif
 278
 279 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
 280 struct pixel_rate_range_table_entry {
 281         unsigned int range_min_khz;
 282         unsigned int range_max_khz;
 283         unsigned int target_pixel_rate_khz;
 284         unsigned short mult_factor;
 285         unsigned short div_factor;
 286 };
 287
 288 #if defined(CONFIG_DRM_AMD_DC_DCN)
 289 extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
 290 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
 291                 unsigned int pixel_rate_khz);
 292 #endif
 293
 294 #endif