drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #ifndef _DCE_DMCU_H_
  28 #define _DCE_DMCU_H_
  29
  30 #include "dmcu.h"
  31
  32 #define DMCU_COMMON_REG_LIST_DCE_BASE() \
  33         SR(DMCU_CTRL), \
  34         SR(DMCU_STATUS), \
  35         SR(DMCU_RAM_ACCESS_CTRL), \
  36         SR(DMCU_IRAM_WR_CTRL), \
  37         SR(DMCU_IRAM_WR_DATA), \
  38         SR(MASTER_COMM_DATA_REG1), \
  39         SR(MASTER_COMM_DATA_REG2), \
  40         SR(MASTER_COMM_DATA_REG3), \
  41         SR(MASTER_COMM_CMD_REG), \
  42         SR(MASTER_COMM_CNTL_REG), \
  43         SR(DMCU_IRAM_RD_CTRL), \
  44         SR(DMCU_IRAM_RD_DATA), \
  45         SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
  46         SR(SMU_INTERRUPT_CONTROL), \
  47         SR(DC_DMCU_SCRATCH)
  48
  49 #if defined(CONFIG_DRM_AMD_DC_SI)
  50 #define DMCU_DCE60_REG_LIST() \
  51         SR(DMCU_CTRL), \
  52         SR(DMCU_STATUS), \
  53         SR(DMCU_RAM_ACCESS_CTRL), \
  54         SR(DMCU_IRAM_WR_CTRL), \
  55         SR(DMCU_IRAM_WR_DATA), \
  56         SR(MASTER_COMM_DATA_REG1), \
  57         SR(MASTER_COMM_DATA_REG2), \
  58         SR(MASTER_COMM_DATA_REG3), \
  59         SR(MASTER_COMM_CMD_REG), \
  60         SR(MASTER_COMM_CNTL_REG), \
  61         SR(DMCU_IRAM_RD_CTRL), \
  62         SR(DMCU_IRAM_RD_DATA), \
  63         SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
  64         SR(DC_DMCU_SCRATCH)
  65 #endif
  66
  67 #define DMCU_DCE80_REG_LIST() \
  68         SR(DMCU_CTRL), \
  69         SR(DMCU_STATUS), \
  70         SR(DMCU_RAM_ACCESS_CTRL), \
  71         SR(DMCU_IRAM_WR_CTRL), \
  72         SR(DMCU_IRAM_WR_DATA), \
  73         SR(MASTER_COMM_DATA_REG1), \
  74         SR(MASTER_COMM_DATA_REG2), \
  75         SR(MASTER_COMM_DATA_REG3), \
  76         SR(MASTER_COMM_CMD_REG), \
  77         SR(MASTER_COMM_CNTL_REG), \
  78         SR(DMCU_IRAM_RD_CTRL), \
  79         SR(DMCU_IRAM_RD_DATA), \
  80         SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
  81         SR(SMU_INTERRUPT_CONTROL), \
  82         SR(DC_DMCU_SCRATCH)
  83
  84 #define DMCU_DCE110_COMMON_REG_LIST() \
  85         DMCU_COMMON_REG_LIST_DCE_BASE(), \
  86         SR(DCI_MEM_PWR_STATUS)
  87
  88 #define DMCU_DCN10_REG_LIST()\
  89         DMCU_COMMON_REG_LIST_DCE_BASE(), \
  90         SR(DMU_MEM_PWR_CNTL)
  91
  92 #define DMCU_DCN20_REG_LIST()\
  93         DMCU_DCN10_REG_LIST(), \
  94         SR(DMCUB_SCRATCH15)
  95
  96 #define DMCU_SF(reg_name, field_name, post_fix)\
  97         .field_name = reg_name ## __ ## field_name ## post_fix
  98
  99 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
 100         DMCU_SF(DMCU_CTRL, \
 101                         DMCU_ENABLE, mask_sh), \
 102         DMCU_SF(DMCU_STATUS, \
 103                         UC_IN_STOP_MODE, mask_sh), \
 104         DMCU_SF(DMCU_STATUS, \
 105                         UC_IN_RESET, mask_sh), \
 106         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 107                         IRAM_HOST_ACCESS_EN, mask_sh), \
 108         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 109                         IRAM_WR_ADDR_AUTO_INC, mask_sh), \
 110         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 111                         IRAM_RD_ADDR_AUTO_INC, mask_sh), \
 112         DMCU_SF(MASTER_COMM_CMD_REG, \
 113                         MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 114         DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
 115         DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
 116                         STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \
 117         DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
 118                         STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \
 119         DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
 120                         STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \
 121         DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
 122                         STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
 123         DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
 124
 125 #if defined(CONFIG_DRM_AMD_DC_SI)
 126 #define DMCU_MASK_SH_LIST_DCE60(mask_sh) \
 127         DMCU_SF(DMCU_CTRL, \
 128                         DMCU_ENABLE, mask_sh), \
 129         DMCU_SF(DMCU_STATUS, \
 130                         UC_IN_STOP_MODE, mask_sh), \
 131         DMCU_SF(DMCU_STATUS, \
 132                         UC_IN_RESET, mask_sh), \
 133         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 134                         IRAM_HOST_ACCESS_EN, mask_sh), \
 135         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 136                         IRAM_WR_ADDR_AUTO_INC, mask_sh), \
 137         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 138                         IRAM_RD_ADDR_AUTO_INC, mask_sh), \
 139         DMCU_SF(MASTER_COMM_CMD_REG, \
 140                         MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 141         DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
 142 #endif
 143
 144 #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
 145         DMCU_SF(DMCU_CTRL, \
 146                         DMCU_ENABLE, mask_sh), \
 147         DMCU_SF(DMCU_STATUS, \
 148                         UC_IN_STOP_MODE, mask_sh), \
 149         DMCU_SF(DMCU_STATUS, \
 150                         UC_IN_RESET, mask_sh), \
 151         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 152                         IRAM_HOST_ACCESS_EN, mask_sh), \
 153         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 154                         IRAM_WR_ADDR_AUTO_INC, mask_sh), \
 155         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 156                         IRAM_RD_ADDR_AUTO_INC, mask_sh), \
 157         DMCU_SF(MASTER_COMM_CMD_REG, \
 158                         MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 159         DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
 160         DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
 161
 162 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
 163         DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 164         DMCU_SF(DCI_MEM_PWR_STATUS, \
 165                 DMCU_IRAM_MEM_PWR_STATE, mask_sh)
 166
 167 #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \
 168         DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 169         DMCU_SF(DMU_MEM_PWR_CNTL, \
 170                         DMCU_IRAM_MEM_PWR_STATE, mask_sh)
 171
 172 #define DMCU_REG_FIELD_LIST(type) \
 173         type DMCU_IRAM_MEM_PWR_STATE; \
 174         type IRAM_HOST_ACCESS_EN; \
 175         type IRAM_WR_ADDR_AUTO_INC; \
 176         type IRAM_RD_ADDR_AUTO_INC; \
 177         type DMCU_ENABLE; \
 178         type UC_IN_STOP_MODE; \
 179         type UC_IN_RESET; \
 180         type MASTER_COMM_CMD_REG_BYTE0; \
 181         type MASTER_COMM_INTERRUPT; \
 182         type DPHY_RX_FAST_TRAINING_CAPABLE; \
 183         type DPHY_LOAD_BS_COUNT; \
 184         type STATIC_SCREEN1_INT_TO_UC_EN; \
 185         type STATIC_SCREEN2_INT_TO_UC_EN; \
 186         type STATIC_SCREEN3_INT_TO_UC_EN; \
 187         type STATIC_SCREEN4_INT_TO_UC_EN; \
 188         type DP_SEC_GSP0_LINE_NUM; \
 189         type DP_SEC_GSP0_PRIORITY; \
 190         type DC_SMU_INT_ENABLE
 191
 192 struct dce_dmcu_shift {
 193         DMCU_REG_FIELD_LIST(uint8_t);
 194 };
 195
 196 struct dce_dmcu_mask {
 197         DMCU_REG_FIELD_LIST(uint32_t);
 198 };
 199
 200 struct dce_dmcu_registers {
 201         uint32_t DMCU_CTRL;
 202         uint32_t DMCU_STATUS;
 203         uint32_t DMCU_RAM_ACCESS_CTRL;
 204         uint32_t DCI_MEM_PWR_STATUS;
 205         uint32_t DMU_MEM_PWR_CNTL;
 206         uint32_t DMCU_IRAM_WR_CTRL;
 207         uint32_t DMCU_IRAM_WR_DATA;
 208
 209         uint32_t MASTER_COMM_DATA_REG1;
 210         uint32_t MASTER_COMM_DATA_REG2;
 211         uint32_t MASTER_COMM_DATA_REG3;
 212         uint32_t MASTER_COMM_CMD_REG;
 213         uint32_t MASTER_COMM_CNTL_REG;
 214         uint32_t DMCU_IRAM_RD_CTRL;
 215         uint32_t DMCU_IRAM_RD_DATA;
 216         uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
 217         uint32_t SMU_INTERRUPT_CONTROL;
 218         uint32_t DC_DMCU_SCRATCH;
 219         uint32_t DMCUB_SCRATCH15;
 220 };
 221
 222 struct dce_dmcu {
 223         struct dmcu base;
 224         const struct dce_dmcu_registers *regs;
 225         const struct dce_dmcu_shift *dmcu_shift;
 226         const struct dce_dmcu_mask *dmcu_mask;
 227 };
 228
 229 /*******************************************************************
 230  *   MASTER_COMM_DATA_REG1   Bit position    Data
 231  *                           7:0                    hyst_frames[7:0]
 232  *                           14:8               hyst_lines[6:0]
 233  *                           15             RFB_UPDATE_AUTO_EN
 234  *                           18:16              phy_num[2:0]
 235  *                           21:19              dcp_sel[2:0]
 236  *                           22             phy_type
 237  *                           23             frame_cap_ind
 238  *                           26:24              aux_chan[2:0]
 239  *                           30:27              aux_repeat[3:0]
 240  *                           31:31              reserved[31:31]
 241  ******************************************************************/
 242 union dce_dmcu_psr_config_data_reg1 {
 243         struct {
 244                 unsigned int timehyst_frames:8;                  /*[7:0]*/
 245                 unsigned int hyst_lines:7;                       /*[14:8]*/
 246                 unsigned int rfb_update_auto_en:1;               /*[15:15]*/
 247                 unsigned int dp_port_num:3;                      /*[18:16]*/
 248                 unsigned int dcp_sel:3;                          /*[21:19]*/
 249                 unsigned int phy_type:1;                         /*[22:22]*/
 250                 unsigned int frame_cap_ind:1;                    /*[23:23]*/
 251                 unsigned int aux_chan:3;                         /*[26:24]*/
 252                 unsigned int aux_repeat:4;                       /*[30:27]*/
 253                 unsigned int allow_smu_optimizations:1;         /*[31:31]*/
 254         } bits;
 255         unsigned int u32All;
 256 };
 257
 258 /*******************************************************************
 259  *   MASTER_COMM_DATA_REG2
 260  *******************************************************************/
 261 union dce_dmcu_psr_config_data_reg2 {
 262         struct {
 263                 unsigned int dig_fe:3;                  /*[2:0]*/
 264                 unsigned int dig_be:3;                  /*[5:3]*/
 265                 unsigned int skip_wait_for_pll_lock:1;  /*[6:6]*/
 266                 unsigned int reserved:9;                /*[15:7]*/
 267                 unsigned int frame_delay:8;             /*[23:16]*/
 268                 unsigned int smu_phy_id:4;              /*[27:24]*/
 269                 unsigned int num_of_controllers:4;      /*[31:28]*/
 270         } bits;
 271         unsigned int u32All;
 272 };
 273
 274 /*******************************************************************
 275  *   MASTER_COMM_DATA_REG3
 276  *******************************************************************/
 277 union dce_dmcu_psr_config_data_reg3 {
 278         struct {
 279                 unsigned int psr_level:16;      /*[15:0]*/
 280                 unsigned int link_rate:4;       /*[19:16]*/
 281                 unsigned int reserved:12;        /*[31:20]*/
 282         } bits;
 283         unsigned int u32All;
 284 };
 285
 286 union dce_dmcu_psr_config_data_wait_loop_reg1 {
 287         struct {
 288                 unsigned int wait_loop:16; /* [15:0] */
 289                 unsigned int reserved:16; /* [31:16] */
 290         } bits;
 291         unsigned int u32;
 292 };
 293
 294 struct dmcu *dce_dmcu_create(
 295         struct dc_context *ctx,
 296         const struct dce_dmcu_registers *regs,
 297         const struct dce_dmcu_shift *dmcu_shift,
 298         const struct dce_dmcu_mask *dmcu_mask);
 299
 300 struct dmcu *dcn10_dmcu_create(
 301         struct dc_context *ctx,
 302         const struct dce_dmcu_registers *regs,
 303         const struct dce_dmcu_shift *dmcu_shift,
 304         const struct dce_dmcu_mask *dmcu_mask);
 305
 306 struct dmcu *dcn20_dmcu_create(
 307         struct dc_context *ctx,
 308         const struct dce_dmcu_registers *regs,
 309         const struct dce_dmcu_shift *dmcu_shift,
 310         const struct dce_dmcu_mask *dmcu_mask);
 311
 312 struct dmcu *dcn21_dmcu_create(
 313         struct dc_context *ctx,
 314         const struct dce_dmcu_registers *regs,
 315         const struct dce_dmcu_shift *dmcu_shift,
 316         const struct dce_dmcu_mask *dmcu_mask);
 317
 318 void dce_dmcu_destroy(struct dmcu **dmcu);
 319
 320 static const uint32_t abm_gain_stepsize = 0x0060;
 321
 322 #endif /* _DCE_ABM_H_ */