drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_PANEL_CNTL__DCE_H__
  27 #define __DC_PANEL_CNTL__DCE_H__
  28
  29 #include "panel_cntl.h"
  30
  31 /* set register offset with instance */
  32 #define DCE_PANEL_CNTL_SR(reg_name, block)\
  33         .reg_name = mm ## block ## _ ## reg_name
  34
  35 #define DCE_PANEL_CNTL_REG_LIST()\
  36         DCE_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
  37         DCE_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
  38         DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
  39         SR(BL_PWM_CNTL), \
  40         SR(BL_PWM_CNTL2), \
  41         SR(BL_PWM_PERIOD_CNTL), \
  42         SR(BL_PWM_GRP1_REG_LOCK), \
  43         SR(BIOS_SCRATCH_2)
  44
  45 #define DCN_PANEL_CNTL_SR(reg_name, block)\
  46         .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
  47                                         mm ## block ## _ ## reg_name
  48
  49 #define DCN_PANEL_CNTL_REG_LIST()\
  50         DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
  51         DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
  52         DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
  53         SR(BL_PWM_CNTL), \
  54         SR(BL_PWM_CNTL2), \
  55         SR(BL_PWM_PERIOD_CNTL), \
  56         SR(BL_PWM_GRP1_REG_LOCK), \
  57         NBIO_SR(BIOS_SCRATCH_2)
  58
  59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
  60         .field_name = reg_name ## __ ## field_name ## post_fix
  61
  62 #define DCE_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
  63         DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
  64         DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON_OVRD, mask_sh),\
  65         DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
  66         DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
  67         DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, mask_sh), \
  68         DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
  69         DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
  70         DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
  71         DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
  72         DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
  73         DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
  74         DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
  75         DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
  76         DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
  77         DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
  78
  79 #define DCE_PANEL_CNTL_REG_FIELD_LIST(type) \
  80         type LVTMA_BLON;\
  81         type LVTMA_BLON_OVRD;\
  82         type LVTMA_DIGON;\
  83         type LVTMA_DIGON_OVRD;\
  84         type LVTMA_PWRSEQ_TARGET_STATE; \
  85         type LVTMA_PWRSEQ_TARGET_STATE_R; \
  86         type BL_PWM_REF_DIV; \
  87         type BL_PWM_EN; \
  88         type BL_ACTIVE_INT_FRAC_CNT; \
  89         type BL_PWM_FRACTIONAL_EN; \
  90         type BL_PWM_PERIOD; \
  91         type BL_PWM_PERIOD_BITCNT; \
  92         type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
  93         type BL_PWM_GRP1_REG_LOCK; \
  94         type BL_PWM_GRP1_REG_UPDATE_PENDING
  95
  96 struct dce_panel_cntl_shift {
  97         DCE_PANEL_CNTL_REG_FIELD_LIST(uint8_t);
  98 };
  99
 100 struct dce_panel_cntl_mask {
 101         DCE_PANEL_CNTL_REG_FIELD_LIST(uint32_t);
 102 };
 103
 104 struct dce_panel_cntl_registers {
 105         uint32_t PWRSEQ_CNTL;
 106         uint32_t PWRSEQ_STATE;
 107         uint32_t BL_PWM_CNTL;
 108         uint32_t BL_PWM_CNTL2;
 109         uint32_t BL_PWM_PERIOD_CNTL;
 110         uint32_t BL_PWM_GRP1_REG_LOCK;
 111         uint32_t PWRSEQ_REF_DIV;
 112         uint32_t BIOS_SCRATCH_2;
 113 };
 114
 115 struct dce_panel_cntl {
 116         struct panel_cntl base;
 117         const struct dce_panel_cntl_registers *regs;
 118         const struct dce_panel_cntl_shift *shift;
 119         const struct dce_panel_cntl_mask *mask;
 120 };
 121
 122 void dce_panel_cntl_construct(
 123         struct dce_panel_cntl *panel_cntl,
 124         const struct panel_cntl_init_data *init_data,
 125         const struct dce_panel_cntl_registers *regs,
 126         const struct dce_panel_cntl_shift *shift,
 127         const struct dce_panel_cntl_mask *mask);
 128
 129 #endif /* __DC_PANEL_CNTL__DCE_H__ */