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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dce / dce_transform.c
blob130a0a0c8332918de5ce9541cad2cf4ca2537604
1 /*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dce_transform.h"
27 #include "reg_helper.h"
28 #include "opp.h"
29 #include "basics/conversion.h"
30 #include "dc.h"
31
32 #define REG(reg) \
33 (xfm_dce->regs->reg)
34
35 #undef FN
36 #define FN(reg_name, field_name) \
37 xfm_dce->xfm_shift->field_name, xfm_dce->xfm_mask->field_name
38
39 #define CTX \
40 xfm_dce->base.ctx
41 #define DC_LOGGER \
42 xfm_dce->base.ctx->logger
43
44 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
45 #define GAMUT_MATRIX_SIZE 12
46 #define SCL_PHASES 16
47
48 enum dcp_out_trunc_round_mode {
49 DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
50 DCP_OUT_TRUNC_ROUND_MODE_ROUND
51 };
52
53 enum dcp_out_trunc_round_depth {
54 DCP_OUT_TRUNC_ROUND_DEPTH_14BIT,
55 DCP_OUT_TRUNC_ROUND_DEPTH_13BIT,
56 DCP_OUT_TRUNC_ROUND_DEPTH_12BIT,
57 DCP_OUT_TRUNC_ROUND_DEPTH_11BIT,
58 DCP_OUT_TRUNC_ROUND_DEPTH_10BIT,
59 DCP_OUT_TRUNC_ROUND_DEPTH_9BIT,
60 DCP_OUT_TRUNC_ROUND_DEPTH_8BIT
61 };
62
63 /* defines the various methods of bit reduction available for use */
64 enum dcp_bit_depth_reduction_mode {
65 DCP_BIT_DEPTH_REDUCTION_MODE_DITHER,
66 DCP_BIT_DEPTH_REDUCTION_MODE_ROUND,
67 DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE,
68 DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED,
69 DCP_BIT_DEPTH_REDUCTION_MODE_INVALID
70 };
71
72 enum dcp_spatial_dither_mode {
73 DCP_SPATIAL_DITHER_MODE_AAAA,
74 DCP_SPATIAL_DITHER_MODE_A_AA_A,
75 DCP_SPATIAL_DITHER_MODE_AABBAABB,
76 DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC,
77 DCP_SPATIAL_DITHER_MODE_INVALID
78 };
79
80 enum dcp_spatial_dither_depth {
81 DCP_SPATIAL_DITHER_DEPTH_30BPP,
82 DCP_SPATIAL_DITHER_DEPTH_24BPP
83 };
84
85 enum csc_color_mode {
86 /* 00 - BITS2:0 Bypass */
87 CSC_COLOR_MODE_GRAPHICS_BYPASS,
88 /* 01 - hard coded coefficient TV RGB */
89 CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
90 /* 04 - programmable OUTPUT CSC coefficient */
91 CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
92 };
93
94 enum grph_color_adjust_option {
95 GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
96 GRPH_COLOR_MATRIX_SW
97 };
98
99 static const struct out_csc_color_matrix global_color_matrix[] = {
100 { COLOR_SPACE_SRGB,
101 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
102 { COLOR_SPACE_SRGB_LIMITED,
103 { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
104 { COLOR_SPACE_YCBCR601,
105 { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
106 0xF6B9, 0xE00, 0x1000} },
107 { COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
108 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
109 /* TODO: correct values below */
110 { COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
111 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
112 { COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
113 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
114 };
115
116 static bool setup_scaling_configuration(
117 struct dce_transform *xfm_dce,
118 const struct scaler_data *data)
119 {
120 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
121
122 if (data->taps.h_taps + data->taps.v_taps <= 2) {
123 /* Set bypass */
124 if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0)
125 REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0);
126 else
127 REG_UPDATE(SCL_MODE, SCL_MODE, 0);
128 return false;
129 }
130
131 REG_SET_2(SCL_TAP_CONTROL, 0,
132 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
133 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
134
135 if (data->format <= PIXEL_FORMAT_GRPH_END)
136 REG_UPDATE(SCL_MODE, SCL_MODE, 1);
137 else
138 REG_UPDATE(SCL_MODE, SCL_MODE, 2);
139
140 if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0)
141 REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1);
142
143 /* 1 - Replace out of bound pixels with edge */
144 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);
145
146 return true;
147 }
148
149 #if defined(CONFIG_DRM_AMD_DC_SI)
150 static bool dce60_setup_scaling_configuration(
151 struct dce_transform *xfm_dce,
152 const struct scaler_data *data)
153 {
154 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
155
156 if (data->taps.h_taps + data->taps.v_taps <= 2) {
157 /* Set bypass */
158
159 /* DCE6 has no SCL_MODE register, skip scale mode programming */
160
161 return false;
162 }
163
164 REG_SET_2(SCL_TAP_CONTROL, 0,
165 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
166 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
167
168 /* DCE6 has no SCL_MODE register, skip scale mode programming */
169
170 /* DCE6 has no SCL_BOUNDARY_MODE bit, skip replace out of bound pixels */
171
172 return true;
173 }
174 #endif
175
176 static void program_overscan(
177 struct dce_transform *xfm_dce,
178 const struct scaler_data *data)
179 {
180 int overscan_right = data->h_active
181 - data->recout.x - data->recout.width;
182 int overscan_bottom = data->v_active
183 - data->recout.y - data->recout.height;
184
185 if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
186 overscan_bottom += 2;
187 overscan_right += 2;
188 }
189
190 if (overscan_right < 0) {
191 BREAK_TO_DEBUGGER();
192 overscan_right = 0;
193 }
194 if (overscan_bottom < 0) {
195 BREAK_TO_DEBUGGER();
196 overscan_bottom = 0;
197 }
198
199 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0,
200 EXT_OVERSCAN_LEFT, data->recout.x,
201 EXT_OVERSCAN_RIGHT, overscan_right);
202 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0,
203 EXT_OVERSCAN_TOP, data->recout.y,
204 EXT_OVERSCAN_BOTTOM, overscan_bottom);
205 }
206
207 static void program_multi_taps_filter(
208 struct dce_transform *xfm_dce,
209 int taps,
210 const uint16_t *coeffs,
211 enum ram_filter_type filter_type)
212 {
213 int phase, pair;
214 int array_idx = 0;
215 int taps_pairs = (taps + 1) / 2;
216 int phases_to_program = SCL_PHASES / 2 + 1;
217
218 uint32_t power_ctl = 0;
219
220 if (!coeffs)
221 return;
222
223 /*We need to disable power gating on coeff memory to do programming*/
224 if (REG(DCFE_MEM_PWR_CTRL)) {
225 power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);
226 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);
227
228 REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10);
229 }
230 for (phase = 0; phase < phases_to_program; phase++) {
231 /*we always program N/2 + 1 phases, total phases N, but N/2-1 are just mirror
232 phase 0 is unique and phase N/2 is unique if N is even*/
233 for (pair = 0; pair < taps_pairs; pair++) {
234 uint16_t odd_coeff = 0;
235 uint16_t even_coeff = coeffs[array_idx];
236
237 REG_SET_3(SCL_COEF_RAM_SELECT, 0,
238 SCL_C_RAM_FILTER_TYPE, filter_type,
239 SCL_C_RAM_PHASE, phase,
240 SCL_C_RAM_TAP_PAIR_IDX, pair);
241
242 if (taps % 2 && pair == taps_pairs - 1)
243 array_idx++;
244 else {
245 odd_coeff = coeffs[array_idx + 1];
246 array_idx += 2;
247 }
248
249 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
250 SCL_C_RAM_EVEN_TAP_COEF_EN, 1,
251 SCL_C_RAM_EVEN_TAP_COEF, even_coeff,
252 SCL_C_RAM_ODD_TAP_COEF_EN, 1,
253 SCL_C_RAM_ODD_TAP_COEF, odd_coeff);
254 }
255 }
256
257 /*We need to restore power gating on coeff memory to initial state*/
258 if (REG(DCFE_MEM_PWR_CTRL))
259 REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
260 }
261
262 static void program_viewport(
263 struct dce_transform *xfm_dce,
264 const struct rect *view_port)
265 {
266 REG_SET_2(VIEWPORT_START, 0,
267 VIEWPORT_X_START, view_port->x,
268 VIEWPORT_Y_START, view_port->y);
269
270 REG_SET_2(VIEWPORT_SIZE, 0,
271 VIEWPORT_HEIGHT, view_port->height,
272 VIEWPORT_WIDTH, view_port->width);
273
274 /* TODO: add stereo support */
275 }
276
277 static void calculate_inits(
278 struct dce_transform *xfm_dce,
279 const struct scaler_data *data,
280 struct scl_ratios_inits *inits)
281 {
282 struct fixed31_32 h_init;
283 struct fixed31_32 v_init;
284
285 inits->h_int_scale_ratio =
286 dc_fixpt_u2d19(data->ratios.horz) << 5;
287 inits->v_int_scale_ratio =
288 dc_fixpt_u2d19(data->ratios.vert) << 5;
289
290 h_init =
291 dc_fixpt_div_int(
292 dc_fixpt_add(
293 data->ratios.horz,
294 dc_fixpt_from_int(data->taps.h_taps + 1)),
295 2);
296 inits->h_init.integer = dc_fixpt_floor(h_init);
297 inits->h_init.fraction = dc_fixpt_u0d19(h_init) << 5;
298
299 v_init =
300 dc_fixpt_div_int(
301 dc_fixpt_add(
302 data->ratios.vert,
303 dc_fixpt_from_int(data->taps.v_taps + 1)),
304 2);
305 inits->v_init.integer = dc_fixpt_floor(v_init);
306 inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;
307 }
308
309 #if defined(CONFIG_DRM_AMD_DC_SI)
310 static void dce60_calculate_inits(
311 struct dce_transform *xfm_dce,
312 const struct scaler_data *data,
313 struct sclh_ratios_inits *inits)
314 {
315 struct fixed31_32 v_init;
316
317 inits->h_int_scale_ratio =
318 dc_fixpt_u2d19(data->ratios.horz) << 5;
319 inits->v_int_scale_ratio =
320 dc_fixpt_u2d19(data->ratios.vert) << 5;
321
322 /* DCE6 h_init_luma setting inspired by DCE110 */
323 inits->h_init_luma.integer = 1;
324
325 /* DCE6 h_init_chroma setting inspired by DCE110 */
326 inits->h_init_chroma.integer = 1;
327
328 v_init =
329 dc_fixpt_div_int(
330 dc_fixpt_add(
331 data->ratios.vert,
332 dc_fixpt_from_int(data->taps.v_taps + 1)),
333 2);
334 inits->v_init.integer = dc_fixpt_floor(v_init);
335 inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;
336 }
337 #endif
338
339 static void program_scl_ratios_inits(
340 struct dce_transform *xfm_dce,
341 struct scl_ratios_inits *inits)
342 {
343
344 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
345 SCL_H_SCALE_RATIO, inits->h_int_scale_ratio);
346
347 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
348 SCL_V_SCALE_RATIO, inits->v_int_scale_ratio);
349
350 REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
351 SCL_H_INIT_INT, inits->h_init.integer,
352 SCL_H_INIT_FRAC, inits->h_init.fraction);
353
354 REG_SET_2(SCL_VERT_FILTER_INIT, 0,
355 SCL_V_INIT_INT, inits->v_init.integer,
356 SCL_V_INIT_FRAC, inits->v_init.fraction);
357
358 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
359 }
360
361 #if defined(CONFIG_DRM_AMD_DC_SI)
362 static void dce60_program_scl_ratios_inits(
363 struct dce_transform *xfm_dce,
364 struct sclh_ratios_inits *inits)
365 {
366
367 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
368 SCL_H_SCALE_RATIO, inits->h_int_scale_ratio);
369
370 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
371 SCL_V_SCALE_RATIO, inits->v_int_scale_ratio);
372
373 /* DCE6 has SCL_HORZ_FILTER_INIT_RGB_LUMA register */
374 REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0,
375 SCL_H_INIT_INT_RGB_Y, inits->h_init_luma.integer,
376 SCL_H_INIT_FRAC_RGB_Y, inits->h_init_luma.fraction);
377
378 /* DCE6 has SCL_HORZ_FILTER_INIT_CHROMA register */
379 REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0,
380 SCL_H_INIT_INT_CBCR, inits->h_init_chroma.integer,
381 SCL_H_INIT_FRAC_CBCR, inits->h_init_chroma.fraction);
382
383 REG_SET_2(SCL_VERT_FILTER_INIT, 0,
384 SCL_V_INIT_INT, inits->v_init.integer,
385 SCL_V_INIT_FRAC, inits->v_init.fraction);
386
387 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
388 }
389 #endif
390
391 static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio)
392 {
393 if (taps == 4)
394 return get_filter_4tap_16p(ratio);
395 else if (taps == 3)
396 return get_filter_3tap_16p(ratio);
397 else if (taps == 2)
398 return get_filter_2tap_16p();
399 else if (taps == 1)
400 return NULL;
401 else {
402 /* should never happen, bug */
403 BREAK_TO_DEBUGGER();
404 return NULL;
405 }
406 }
407
408 static void dce_transform_set_scaler(
409 struct transform *xfm,
410 const struct scaler_data *data)
411 {
412 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
413 bool is_scaling_required;
414 bool filter_updated = false;
415 const uint16_t *coeffs_v, *coeffs_h;
416
417 /*Use all three pieces of memory always*/
418 REG_SET_2(LB_MEMORY_CTRL, 0,
419 LB_MEMORY_CONFIG, 0,
420 LB_MEMORY_SIZE, xfm_dce->lb_memory_size);
421
422 /* Clear SCL_F_SHARP_CONTROL value to 0 */
423 REG_WRITE(SCL_F_SHARP_CONTROL, 0);
424
425 /* 1. Program overscan */
426 program_overscan(xfm_dce, data);
427
428 /* 2. Program taps and configuration */
429 is_scaling_required = setup_scaling_configuration(xfm_dce, data);
430
431 if (is_scaling_required) {
432 /* 3. Calculate and program ratio, filter initialization */
433 struct scl_ratios_inits inits = { 0 };
434
435 calculate_inits(xfm_dce, data, &inits);
436
437 program_scl_ratios_inits(xfm_dce, &inits);
438
439 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert);
440 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz);
441
442 if (coeffs_v != xfm_dce->filter_v || coeffs_h != xfm_dce->filter_h) {
443 /* 4. Program vertical filters */
444 if (xfm_dce->filter_v == NULL)
445 REG_SET(SCL_VERT_FILTER_CONTROL, 0,
446 SCL_V_2TAP_HARDCODE_COEF_EN, 0);
447 program_multi_taps_filter(
448 xfm_dce,
449 data->taps.v_taps,
450 coeffs_v,
451 FILTER_TYPE_RGB_Y_VERTICAL);
452 program_multi_taps_filter(
453 xfm_dce,
454 data->taps.v_taps,
455 coeffs_v,
456 FILTER_TYPE_ALPHA_VERTICAL);
457
458 /* 5. Program horizontal filters */
459 if (xfm_dce->filter_h == NULL)
460 REG_SET(SCL_HORZ_FILTER_CONTROL, 0,
461 SCL_H_2TAP_HARDCODE_COEF_EN, 0);
462 program_multi_taps_filter(
463 xfm_dce,
464 data->taps.h_taps,
465 coeffs_h,
466 FILTER_TYPE_RGB_Y_HORIZONTAL);
467 program_multi_taps_filter(
468 xfm_dce,
469 data->taps.h_taps,
470 coeffs_h,
471 FILTER_TYPE_ALPHA_HORIZONTAL);
472
473 xfm_dce->filter_v = coeffs_v;
474 xfm_dce->filter_h = coeffs_h;
475 filter_updated = true;
476 }
477 }
478
479 /* 6. Program the viewport */
480 program_viewport(xfm_dce, &data->viewport);
481
482 /* 7. Set bit to flip to new coefficient memory */
483 if (filter_updated)
484 REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1);
485
486 REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en);
487 }
488
489 #if defined(CONFIG_DRM_AMD_DC_SI)
490 static void dce60_transform_set_scaler(
491 struct transform *xfm,
492 const struct scaler_data *data)
493 {
494 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
495 bool is_scaling_required;
496 bool filter_updated = false;
497 const uint16_t *coeffs_v, *coeffs_h;
498
499 /*Use whole line buffer memory always*/
500 REG_SET(DC_LB_MEMORY_SPLIT, 0,
501 DC_LB_MEMORY_CONFIG, 0);
502
503 REG_SET(DC_LB_MEM_SIZE, 0,
504 DC_LB_MEM_SIZE, xfm_dce->lb_memory_size);
505
506 /* Clear SCL_F_SHARP_CONTROL value to 0 */
507 REG_WRITE(SCL_F_SHARP_CONTROL, 0);
508
509 /* 1. Program overscan */
510 program_overscan(xfm_dce, data);
511
512 /* 2. Program taps and configuration */
513 is_scaling_required = dce60_setup_scaling_configuration(xfm_dce, data);
514
515 if (is_scaling_required) {
516 /* 3. Calculate and program ratio, DCE6 filter initialization */
517 struct sclh_ratios_inits inits = { 0 };
518
519 /* DCE6 has specific calculate_inits() function */
520 dce60_calculate_inits(xfm_dce, data, &inits);
521
522 /* DCE6 has specific program_scl_ratios_inits() function */
523 dce60_program_scl_ratios_inits(xfm_dce, &inits);
524
525 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert);
526 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz);
527
528 if (coeffs_v != xfm_dce->filter_v || coeffs_h != xfm_dce->filter_h) {
529 /* 4. Program vertical filters */
530 if (xfm_dce->filter_v == NULL)
531 REG_SET(SCL_VERT_FILTER_CONTROL, 0,
532 SCL_V_2TAP_HARDCODE_COEF_EN, 0);
533 program_multi_taps_filter(
534 xfm_dce,
535 data->taps.v_taps,
536 coeffs_v,
537 FILTER_TYPE_RGB_Y_VERTICAL);
538 program_multi_taps_filter(
539 xfm_dce,
540 data->taps.v_taps,
541 coeffs_v,
542 FILTER_TYPE_ALPHA_VERTICAL);
543
544 /* 5. Program horizontal filters */
545 if (xfm_dce->filter_h == NULL)
546 REG_SET(SCL_HORZ_FILTER_CONTROL, 0,
547 SCL_H_2TAP_HARDCODE_COEF_EN, 0);
548 program_multi_taps_filter(
549 xfm_dce,
550 data->taps.h_taps,
551 coeffs_h,
552 FILTER_TYPE_RGB_Y_HORIZONTAL);
553 program_multi_taps_filter(
554 xfm_dce,
555 data->taps.h_taps,
556 coeffs_h,
557 FILTER_TYPE_ALPHA_HORIZONTAL);
558
559 xfm_dce->filter_v = coeffs_v;
560 xfm_dce->filter_h = coeffs_h;
561 filter_updated = true;
562 }
563 }
564
565 /* 6. Program the viewport */
566 program_viewport(xfm_dce, &data->viewport);
567
568 /* DCE6 has no SCL_COEF_UPDATE_COMPLETE bit to flip to new coefficient memory */
569
570 /* DCE6 DATA_FORMAT register does not support ALPHA_EN */
571 }
572 #endif
573
574 /*****************************************************************************
575 * set_clamp
576 *
577 * @param depth : bit depth to set the clamp to (should match denorm)
578 *
579 * @brief
580 * Programs clamp according to panel bit depth.
581 *
582 *******************************************************************************/
583 static void set_clamp(
584 struct dce_transform *xfm_dce,
585 enum dc_color_depth depth)
586 {
587 int clamp_max = 0;
588
589 /* At the clamp block the data will be MSB aligned, so we set the max
590 * clamp accordingly.
591 * For example, the max value for 6 bits MSB aligned (14 bit bus) would
592 * be "11 1111 0000 0000" in binary, so 0x3F00.
593 */
594 switch (depth) {
595 case COLOR_DEPTH_666:
596 /* 6bit MSB aligned on 14 bit bus '11 1111 0000 0000' */
597 clamp_max = 0x3F00;
598 break;
599 case COLOR_DEPTH_888:
600 /* 8bit MSB aligned on 14 bit bus '11 1111 1100 0000' */
601 clamp_max = 0x3FC0;
602 break;
603 case COLOR_DEPTH_101010:
604 /* 10bit MSB aligned on 14 bit bus '11 1111 1111 1100' */
605 clamp_max = 0x3FFC;
606 break;
607 case COLOR_DEPTH_121212:
608 /* 12bit MSB aligned on 14 bit bus '11 1111 1111 1111' */
609 clamp_max = 0x3FFF;
610 break;
611 default:
612 clamp_max = 0x3FC0;
613 BREAK_TO_DEBUGGER(); /* Invalid clamp bit depth */
614 }
615 REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0,
616 OUT_CLAMP_MIN_B_CB, 0,
617 OUT_CLAMP_MAX_B_CB, clamp_max);
618
619 REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0,
620 OUT_CLAMP_MIN_G_Y, 0,
621 OUT_CLAMP_MAX_G_Y, clamp_max);
622
623 REG_SET_2(OUT_CLAMP_CONTROL_R_CR, 0,
624 OUT_CLAMP_MIN_R_CR, 0,
625 OUT_CLAMP_MAX_R_CR, clamp_max);
626 }
627
628 /*******************************************************************************
629 * set_round
630 *
631 * @brief
632 * Programs Round/Truncate
633 *
634 * @param [in] mode :round or truncate
635 * @param [in] depth :bit depth to round/truncate to
636 OUT_ROUND_TRUNC_MODE 3:0 0xA Output data round or truncate mode
637 POSSIBLE VALUES:
638 00 - truncate to u0.12
639 01 - truncate to u0.11
640 02 - truncate to u0.10
641 03 - truncate to u0.9
642 04 - truncate to u0.8
643 05 - reserved
644 06 - truncate to u0.14
645 07 - truncate to u0.13 set_reg_field_value(
646 value,
647 clamp_max,
648 OUT_CLAMP_CONTROL_R_CR,
649 OUT_CLAMP_MAX_R_CR);
650 08 - round to u0.12
651 09 - round to u0.11
652 10 - round to u0.10
653 11 - round to u0.9
654 12 - round to u0.8
655 13 - reserved
656 14 - round to u0.14
657 15 - round to u0.13
658
659 ******************************************************************************/
660 static void set_round(
661 struct dce_transform *xfm_dce,
662 enum dcp_out_trunc_round_mode mode,
663 enum dcp_out_trunc_round_depth depth)
664 {
665 int depth_bits = 0;
666 int mode_bit = 0;
667
668 /* set up bit depth */
669 switch (depth) {
670 case DCP_OUT_TRUNC_ROUND_DEPTH_14BIT:
671 depth_bits = 6;
672 break;
673 case DCP_OUT_TRUNC_ROUND_DEPTH_13BIT:
674 depth_bits = 7;
675 break;
676 case DCP_OUT_TRUNC_ROUND_DEPTH_12BIT:
677 depth_bits = 0;
678 break;
679 case DCP_OUT_TRUNC_ROUND_DEPTH_11BIT:
680 depth_bits = 1;
681 break;
682 case DCP_OUT_TRUNC_ROUND_DEPTH_10BIT:
683 depth_bits = 2;
684 break;
685 case DCP_OUT_TRUNC_ROUND_DEPTH_9BIT:
686 depth_bits = 3;
687 break;
688 case DCP_OUT_TRUNC_ROUND_DEPTH_8BIT:
689 depth_bits = 4;
690 break;
691 default:
692 depth_bits = 4;
693 BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_depth */
694 }
695
696 /* set up round or truncate */
697 switch (mode) {
698 case DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE:
699 mode_bit = 0;
700 break;
701 case DCP_OUT_TRUNC_ROUND_MODE_ROUND:
702 mode_bit = 1;
703 break;
704 default:
705 BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_mode */
706 }
707
708 depth_bits |= mode_bit << 3;
709
710 REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits);
711 }
712
713 /*****************************************************************************
714 * set_dither
715 *
716 * @brief
717 * Programs Dither
718 *
719 * @param [in] dither_enable : enable dither
720 * @param [in] dither_mode : dither mode to set
721 * @param [in] dither_depth : bit depth to dither to
722 * @param [in] frame_random_enable : enable frame random
723 * @param [in] rgb_random_enable : enable rgb random
724 * @param [in] highpass_random_enable : enable highpass random
725 *
726 ******************************************************************************/
727
728 static void set_dither(
729 struct dce_transform *xfm_dce,
730 bool dither_enable,
731 enum dcp_spatial_dither_mode dither_mode,
732 enum dcp_spatial_dither_depth dither_depth,
733 bool frame_random_enable,
734 bool rgb_random_enable,
735 bool highpass_random_enable)
736 {
737 int dither_depth_bits = 0;
738 int dither_mode_bits = 0;
739
740 switch (dither_mode) {
741 case DCP_SPATIAL_DITHER_MODE_AAAA:
742 dither_mode_bits = 0;
743 break;
744 case DCP_SPATIAL_DITHER_MODE_A_AA_A:
745 dither_mode_bits = 1;
746 break;
747 case DCP_SPATIAL_DITHER_MODE_AABBAABB:
748 dither_mode_bits = 2;
749 break;
750 case DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC:
751 dither_mode_bits = 3;
752 break;
753 default:
754 /* Invalid dcp_spatial_dither_mode */
755 BREAK_TO_DEBUGGER();
756 }
757
758 switch (dither_depth) {
759 case DCP_SPATIAL_DITHER_DEPTH_30BPP:
760 dither_depth_bits = 0;
761 break;
762 case DCP_SPATIAL_DITHER_DEPTH_24BPP:
763 dither_depth_bits = 1;
764 break;
765 default:
766 /* Invalid dcp_spatial_dither_depth */
767 BREAK_TO_DEBUGGER();
768 }
769
770 /* write the register */
771 REG_SET_6(DCP_SPATIAL_DITHER_CNTL, 0,
772 DCP_SPATIAL_DITHER_EN, dither_enable,
773 DCP_SPATIAL_DITHER_MODE, dither_mode_bits,
774 DCP_SPATIAL_DITHER_DEPTH, dither_depth_bits,
775 DCP_FRAME_RANDOM_ENABLE, frame_random_enable,
776 DCP_RGB_RANDOM_ENABLE, rgb_random_enable,
777 DCP_HIGHPASS_RANDOM_ENABLE, highpass_random_enable);
778 }
779
780 /*****************************************************************************
781 * dce_transform_bit_depth_reduction_program
782 *
783 * @brief
784 * Programs the DCP bit depth reduction registers (Clamp, Round/Truncate,
785 * Dither) for dce
786 *
787 * @param depth : bit depth to set the clamp to (should match denorm)
788 *
789 ******************************************************************************/
790 static void program_bit_depth_reduction(
791 struct dce_transform *xfm_dce,
792 enum dc_color_depth depth,
793 const struct bit_depth_reduction_params *bit_depth_params)
794 {
795 enum dcp_out_trunc_round_depth trunc_round_depth;
796 enum dcp_out_trunc_round_mode trunc_mode;
797 bool spatial_dither_enable;
798
799 ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */
800
801 spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED;
802 /* Default to 12 bit truncation without rounding */
803 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT;
804 trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE;
805
806 if (bit_depth_params->flags.TRUNCATE_ENABLED) {
807 /* Don't enable dithering if truncation is enabled */
808 spatial_dither_enable = false;
809 trunc_mode = bit_depth_params->flags.TRUNCATE_MODE ?
810 DCP_OUT_TRUNC_ROUND_MODE_ROUND :
811 DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE;
812
813 if (bit_depth_params->flags.TRUNCATE_DEPTH == 0 ||
814 bit_depth_params->flags.TRUNCATE_DEPTH == 1)
815 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_8BIT;
816 else if (bit_depth_params->flags.TRUNCATE_DEPTH == 2)
817 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_10BIT;
818 else {
819 /*
820 * Invalid truncate/round depth. Setting here to 12bit
821 * to prevent use-before-initialize errors.
822 */
823 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT;
824 BREAK_TO_DEBUGGER();
825 }
826 }
827
828 set_clamp(xfm_dce, depth);
829 set_round(xfm_dce, trunc_mode, trunc_round_depth);
830 set_dither(xfm_dce,
831 spatial_dither_enable,
832 DCP_SPATIAL_DITHER_MODE_A_AA_A,
833 DCP_SPATIAL_DITHER_DEPTH_30BPP,
834 bit_depth_params->flags.FRAME_RANDOM,
835 bit_depth_params->flags.RGB_RANDOM,
836 bit_depth_params->flags.HIGHPASS_RANDOM);
837 }
838
839 #if defined(CONFIG_DRM_AMD_DC_SI)
840 /*****************************************************************************
841 * dce60_transform_bit_depth_reduction program
842 *
843 * @brief
844 * Programs the DCP bit depth reduction registers (Clamp, Round/Truncate,
845 * Dither) for dce
846 *
847 * @param depth : bit depth to set the clamp to (should match denorm)
848 *
849 ******************************************************************************/
850 static void dce60_program_bit_depth_reduction(
851 struct dce_transform *xfm_dce,
852 enum dc_color_depth depth,
853 const struct bit_depth_reduction_params *bit_depth_params)
854 {
855 enum dcp_out_trunc_round_depth trunc_round_depth;
856 enum dcp_out_trunc_round_mode trunc_mode;
857 bool spatial_dither_enable;
858
859 ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */
860
861 spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED;
862 /* Default to 12 bit truncation without rounding */
863 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT;
864 trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE;
865
866 if (bit_depth_params->flags.TRUNCATE_ENABLED) {
867 /* Don't enable dithering if truncation is enabled */
868 spatial_dither_enable = false;
869 trunc_mode = bit_depth_params->flags.TRUNCATE_MODE ?
870 DCP_OUT_TRUNC_ROUND_MODE_ROUND :
871 DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE;
872
873 if (bit_depth_params->flags.TRUNCATE_DEPTH == 0 ||
874 bit_depth_params->flags.TRUNCATE_DEPTH == 1)
875 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_8BIT;
876 else if (bit_depth_params->flags.TRUNCATE_DEPTH == 2)
877 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_10BIT;
878 else {
879 /*
880 * Invalid truncate/round depth. Setting here to 12bit
881 * to prevent use-before-initialize errors.
882 */
883 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT;
884 BREAK_TO_DEBUGGER();
885 }
886 }
887
888 /* DCE6 has no OUT_CLAMP_CONTROL_* registers - set_clamp() is skipped */
889 set_round(xfm_dce, trunc_mode, trunc_round_depth);
890 set_dither(xfm_dce,
891 spatial_dither_enable,
892 DCP_SPATIAL_DITHER_MODE_A_AA_A,
893 DCP_SPATIAL_DITHER_DEPTH_30BPP,
894 bit_depth_params->flags.FRAME_RANDOM,
895 bit_depth_params->flags.RGB_RANDOM,
896 bit_depth_params->flags.HIGHPASS_RANDOM);
897 }
898 #endif
899
900 static int dce_transform_get_max_num_of_supported_lines(
901 struct dce_transform *xfm_dce,
902 enum lb_pixel_depth depth,
903 int pixel_width)
904 {
905 int pixels_per_entries = 0;
906 int max_pixels_supports = 0;
907
908 ASSERT(pixel_width);
909
910 /* Find number of pixels that can fit into a single LB entry and
911 * take floor of the value since we cannot store a single pixel
912 * across multiple entries. */
913 switch (depth) {
914 case LB_PIXEL_DEPTH_18BPP:
915 pixels_per_entries = xfm_dce->lb_bits_per_entry / 18;
916 break;
917
918 case LB_PIXEL_DEPTH_24BPP:
919 pixels_per_entries = xfm_dce->lb_bits_per_entry / 24;
920 break;
921
922 case LB_PIXEL_DEPTH_30BPP:
923 pixels_per_entries = xfm_dce->lb_bits_per_entry / 30;
924 break;
925
926 case LB_PIXEL_DEPTH_36BPP:
927 pixels_per_entries = xfm_dce->lb_bits_per_entry / 36;
928 break;
929
930 default:
931 DC_LOG_WARNING("%s: Invalid LB pixel depth",
932 __func__);
933 BREAK_TO_DEBUGGER();
934 break;
935 }
936
937 ASSERT(pixels_per_entries);
938
939 max_pixels_supports =
940 pixels_per_entries *
941 xfm_dce->lb_memory_size;
942
943 return (max_pixels_supports / pixel_width);
944 }
945
946 static void set_denormalization(
947 struct dce_transform *xfm_dce,
948 enum dc_color_depth depth)
949 {
950 int denorm_mode = 0;
951
952 switch (depth) {
953 case COLOR_DEPTH_666:
954 /* 63/64 for 6 bit output color depth */
955 denorm_mode = 1;
956 break;
957 case COLOR_DEPTH_888:
958 /* Unity for 8 bit output color depth
959 * because prescale is disabled by default */
960 denorm_mode = 0;
961 break;
962 case COLOR_DEPTH_101010:
963 /* 1023/1024 for 10 bit output color depth */
964 denorm_mode = 3;
965 break;
966 case COLOR_DEPTH_121212:
967 /* 4095/4096 for 12 bit output color depth */
968 denorm_mode = 5;
969 break;
970 case COLOR_DEPTH_141414:
971 case COLOR_DEPTH_161616:
972 default:
973 /* not valid used case! */
974 break;
975 }
976
977 REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);
978 }
979
980 static void dce_transform_set_pixel_storage_depth(
981 struct transform *xfm,
982 enum lb_pixel_depth depth,
983 const struct bit_depth_reduction_params *bit_depth_params)
984 {
985 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
986 int pixel_depth, expan_mode;
987 enum dc_color_depth color_depth;
988
989 switch (depth) {
990 case LB_PIXEL_DEPTH_18BPP:
991 color_depth = COLOR_DEPTH_666;
992 pixel_depth = 2;
993 expan_mode = 1;
994 break;
995 case LB_PIXEL_DEPTH_24BPP:
996 color_depth = COLOR_DEPTH_888;
997 pixel_depth = 1;
998 expan_mode = 1;
999 break;
1000 case LB_PIXEL_DEPTH_30BPP:
1001 color_depth = COLOR_DEPTH_101010;
1002 pixel_depth = 0;
1003 expan_mode = 1;
1004 break;
1005 case LB_PIXEL_DEPTH_36BPP:
1006 color_depth = COLOR_DEPTH_121212;
1007 pixel_depth = 3;
1008 expan_mode = 0;
1009 break;
1010 default:
1011 color_depth = COLOR_DEPTH_101010;
1012 pixel_depth = 0;
1013 expan_mode = 1;
1014 BREAK_TO_DEBUGGER();
1015 break;
1016 }
1017
1018 set_denormalization(xfm_dce, color_depth);
1019 program_bit_depth_reduction(xfm_dce, color_depth, bit_depth_params);
1020
1021 REG_UPDATE_2(LB_DATA_FORMAT,
1022 PIXEL_DEPTH, pixel_depth,
1023 PIXEL_EXPAN_MODE, expan_mode);
1024
1025 if (!(xfm_dce->lb_pixel_depth_supported & depth)) {
1026 /*we should use unsupported capabilities
1027 * unless it is required by w/a*/
1028 DC_LOG_WARNING("%s: Capability not supported",
1029 __func__);
1030 }
1031 }
1032
1033 #if defined(CONFIG_DRM_AMD_DC_SI)
1034 static void dce60_transform_set_pixel_storage_depth(
1035 struct transform *xfm,
1036 enum lb_pixel_depth depth,
1037 const struct bit_depth_reduction_params *bit_depth_params)
1038 {
1039 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1040 int pixel_depth, expan_mode;
1041 enum dc_color_depth color_depth;
1042
1043 switch (depth) {
1044 case LB_PIXEL_DEPTH_18BPP:
1045 color_depth = COLOR_DEPTH_666;
1046 pixel_depth = 2;
1047 expan_mode = 1;
1048 break;
1049 case LB_PIXEL_DEPTH_24BPP:
1050 color_depth = COLOR_DEPTH_888;
1051 pixel_depth = 1;
1052 expan_mode = 1;
1053 break;
1054 case LB_PIXEL_DEPTH_30BPP:
1055 color_depth = COLOR_DEPTH_101010;
1056 pixel_depth = 0;
1057 expan_mode = 1;
1058 break;
1059 case LB_PIXEL_DEPTH_36BPP:
1060 color_depth = COLOR_DEPTH_121212;
1061 pixel_depth = 3;
1062 expan_mode = 0;
1063 break;
1064 default:
1065 color_depth = COLOR_DEPTH_101010;
1066 pixel_depth = 0;
1067 expan_mode = 1;
1068 BREAK_TO_DEBUGGER();
1069 break;
1070 }
1071
1072 set_denormalization(xfm_dce, color_depth);
1073 dce60_program_bit_depth_reduction(xfm_dce, color_depth, bit_depth_params);
1074
1075 /* DATA_FORMAT in DCE6 does not have PIXEL_DEPTH and PIXEL_EXPAN_MODE masks */
1076
1077 if (!(xfm_dce->lb_pixel_depth_supported & depth)) {
1078 /*we should use unsupported capabilities
1079 * unless it is required by w/a*/
1080 DC_LOG_WARNING("%s: Capability not supported",
1081 __func__);
1082 }
1083 }
1084 #endif
1085
1086 static void program_gamut_remap(
1087 struct dce_transform *xfm_dce,
1088 const uint16_t *reg_val)
1089 {
1090 if (reg_val) {
1091 REG_SET_2(GAMUT_REMAP_C11_C12, 0,
1092 GAMUT_REMAP_C11, reg_val[0],
1093 GAMUT_REMAP_C12, reg_val[1]);
1094 REG_SET_2(GAMUT_REMAP_C13_C14, 0,
1095 GAMUT_REMAP_C13, reg_val[2],
1096 GAMUT_REMAP_C14, reg_val[3]);
1097 REG_SET_2(GAMUT_REMAP_C21_C22, 0,
1098 GAMUT_REMAP_C21, reg_val[4],
1099 GAMUT_REMAP_C22, reg_val[5]);
1100 REG_SET_2(GAMUT_REMAP_C23_C24, 0,
1101 GAMUT_REMAP_C23, reg_val[6],
1102 GAMUT_REMAP_C24, reg_val[7]);
1103 REG_SET_2(GAMUT_REMAP_C31_C32, 0,
1104 GAMUT_REMAP_C31, reg_val[8],
1105 GAMUT_REMAP_C32, reg_val[9]);
1106 REG_SET_2(GAMUT_REMAP_C33_C34, 0,
1107 GAMUT_REMAP_C33, reg_val[10],
1108 GAMUT_REMAP_C34, reg_val[11]);
1109
1110 REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1);
1111 } else
1112 REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 0);
1113
1114 }
1115
1116 /**
1117 *****************************************************************************
1118 * Function: dal_transform_wide_gamut_set_gamut_remap
1119 *
1120 * @param [in] const struct xfm_grph_csc_adjustment *adjust
1121 *
1122 * @return
1123 * void
1124 *
1125 * @note calculate and apply color temperature adjustment to in Rgb color space
1126 *
1127 * @see
1128 *
1129 *****************************************************************************
1130 */
1131 static void dce_transform_set_gamut_remap(
1132 struct transform *xfm,
1133 const struct xfm_grph_csc_adjustment *adjust)
1134 {
1135 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1136 int i = 0;
1137
1138 if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
1139 /* Bypass if type is bypass or hw */
1140 program_gamut_remap(xfm_dce, NULL);
1141 else {
1142 struct fixed31_32 arr_matrix[GAMUT_MATRIX_SIZE];
1143 uint16_t arr_reg_val[GAMUT_MATRIX_SIZE];
1144
1145 for (i = 0; i < GAMUT_MATRIX_SIZE; i++)
1146 arr_matrix[i] = adjust->temperature_matrix[i];
1147
1148 convert_float_matrix(
1149 arr_reg_val, arr_matrix, GAMUT_MATRIX_SIZE);
1150
1151 program_gamut_remap(xfm_dce, arr_reg_val);
1152 }
1153 }
1154
1155 static uint32_t decide_taps(struct fixed31_32 ratio, uint32_t in_taps, bool chroma)
1156 {
1157 uint32_t taps;
1158
1159 if (IDENTITY_RATIO(ratio)) {
1160 return 1;
1161 } else if (in_taps != 0) {
1162 taps = in_taps;
1163 } else {
1164 taps = 4;
1165 }
1166
1167 if (chroma) {
1168 taps /= 2;
1169 if (taps < 2)
1170 taps = 2;
1171 }
1172
1173 return taps;
1174 }
1175
1176
1177 bool dce_transform_get_optimal_number_of_taps(
1178 struct transform *xfm,
1179 struct scaler_data *scl_data,
1180 const struct scaling_taps *in_taps)
1181 {
1182 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1183 int pixel_width = scl_data->viewport.width;
1184 int max_num_of_lines;
1185
1186 if (xfm_dce->prescaler_on &&
1187 (scl_data->viewport.width > scl_data->recout.width))
1188 pixel_width = scl_data->recout.width;
1189
1190 max_num_of_lines = dce_transform_get_max_num_of_supported_lines(
1191 xfm_dce,
1192 scl_data->lb_params.depth,
1193 pixel_width);
1194
1195 /* Fail if in_taps are impossible */
1196 if (in_taps->v_taps >= max_num_of_lines)
1197 return false;
1198
1199 /*
1200 * Set taps according to this policy (in this order)
1201 * - Use 1 for no scaling
1202 * - Use input taps
1203 * - Use 4 and reduce as required by line buffer size
1204 * - Decide chroma taps if chroma is scaled
1205 *
1206 * Ignore input chroma taps. Decide based on non-chroma
1207 */
1208 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false);
1209 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false);
1210 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true);
1211 scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true);
1212
1213 if (!IDENTITY_RATIO(scl_data->ratios.vert)) {
1214 /* reduce v_taps if needed but ensure we have at least two */
1215 if (in_taps->v_taps == 0
1216 && max_num_of_lines <= scl_data->taps.v_taps
1217 && scl_data->taps.v_taps > 1) {
1218 scl_data->taps.v_taps = max_num_of_lines - 1;
1219 }
1220
1221 if (scl_data->taps.v_taps <= 1)
1222 return false;
1223 }
1224
1225 if (!IDENTITY_RATIO(scl_data->ratios.vert_c)) {
1226 /* reduce chroma v_taps if needed but ensure we have at least two */
1227 if (max_num_of_lines <= scl_data->taps.v_taps_c && scl_data->taps.v_taps_c > 1) {
1228 scl_data->taps.v_taps_c = max_num_of_lines - 1;
1229 }
1230
1231 if (scl_data->taps.v_taps_c <= 1)
1232 return false;
1233 }
1234
1235 /* we've got valid taps */
1236 return true;
1237 }
1238
1239 static void dce_transform_reset(struct transform *xfm)
1240 {
1241 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1242
1243 xfm_dce->filter_h = NULL;
1244 xfm_dce->filter_v = NULL;
1245 }
1246
1247 static void program_color_matrix(
1248 struct dce_transform *xfm_dce,
1249 const struct out_csc_color_matrix *tbl_entry,
1250 enum grph_color_adjust_option options)
1251 {
1252 {
1253 REG_SET_2(OUTPUT_CSC_C11_C12, 0,
1254 OUTPUT_CSC_C11, tbl_entry->regval[0],
1255 OUTPUT_CSC_C12, tbl_entry->regval[1]);
1256 }
1257 {
1258 REG_SET_2(OUTPUT_CSC_C13_C14, 0,
1259 OUTPUT_CSC_C11, tbl_entry->regval[2],
1260 OUTPUT_CSC_C12, tbl_entry->regval[3]);
1261 }
1262 {
1263 REG_SET_2(OUTPUT_CSC_C21_C22, 0,
1264 OUTPUT_CSC_C11, tbl_entry->regval[4],
1265 OUTPUT_CSC_C12, tbl_entry->regval[5]);
1266 }
1267 {
1268 REG_SET_2(OUTPUT_CSC_C23_C24, 0,
1269 OUTPUT_CSC_C11, tbl_entry->regval[6],
1270 OUTPUT_CSC_C12, tbl_entry->regval[7]);
1271 }
1272 {
1273 REG_SET_2(OUTPUT_CSC_C31_C32, 0,
1274 OUTPUT_CSC_C11, tbl_entry->regval[8],
1275 OUTPUT_CSC_C12, tbl_entry->regval[9]);
1276 }
1277 {
1278 REG_SET_2(OUTPUT_CSC_C33_C34, 0,
1279 OUTPUT_CSC_C11, tbl_entry->regval[10],
1280 OUTPUT_CSC_C12, tbl_entry->regval[11]);
1281 }
1282 }
1283
1284 static bool configure_graphics_mode(
1285 struct dce_transform *xfm_dce,
1286 enum csc_color_mode config,
1287 enum graphics_csc_adjust_type csc_adjust_type,
1288 enum dc_color_space color_space)
1289 {
1290 REG_SET(OUTPUT_CSC_CONTROL, 0,
1291 OUTPUT_CSC_GRPH_MODE, 0);
1292
1293 if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
1294 if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {
1295 REG_SET(OUTPUT_CSC_CONTROL, 0,
1296 OUTPUT_CSC_GRPH_MODE, 4);
1297 } else {
1298
1299 switch (color_space) {
1300 case COLOR_SPACE_SRGB:
1301 /* by pass */
1302 REG_SET(OUTPUT_CSC_CONTROL, 0,
1303 OUTPUT_CSC_GRPH_MODE, 0);
1304 break;
1305 case COLOR_SPACE_SRGB_LIMITED:
1306 /* TV RGB */
1307 REG_SET(OUTPUT_CSC_CONTROL, 0,
1308 OUTPUT_CSC_GRPH_MODE, 1);
1309 break;
1310 case COLOR_SPACE_YCBCR601:
1311 case COLOR_SPACE_YCBCR601_LIMITED:
1312 /* YCbCr601 */
1313 REG_SET(OUTPUT_CSC_CONTROL, 0,
1314 OUTPUT_CSC_GRPH_MODE, 2);
1315 break;
1316 case COLOR_SPACE_YCBCR709:
1317 case COLOR_SPACE_YCBCR709_LIMITED:
1318 /* YCbCr709 */
1319 REG_SET(OUTPUT_CSC_CONTROL, 0,
1320 OUTPUT_CSC_GRPH_MODE, 3);
1321 break;
1322 default:
1323 return false;
1324 }
1325 }
1326 } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
1327 switch (color_space) {
1328 case COLOR_SPACE_SRGB:
1329 /* by pass */
1330 REG_SET(OUTPUT_CSC_CONTROL, 0,
1331 OUTPUT_CSC_GRPH_MODE, 0);
1332 break;
1333 case COLOR_SPACE_SRGB_LIMITED:
1334 /* TV RGB */
1335 REG_SET(OUTPUT_CSC_CONTROL, 0,
1336 OUTPUT_CSC_GRPH_MODE, 1);
1337 break;
1338 case COLOR_SPACE_YCBCR601:
1339 case COLOR_SPACE_YCBCR601_LIMITED:
1340 /* YCbCr601 */
1341 REG_SET(OUTPUT_CSC_CONTROL, 0,
1342 OUTPUT_CSC_GRPH_MODE, 2);
1343 break;
1344 case COLOR_SPACE_YCBCR709:
1345 case COLOR_SPACE_YCBCR709_LIMITED:
1346 /* YCbCr709 */
1347 REG_SET(OUTPUT_CSC_CONTROL, 0,
1348 OUTPUT_CSC_GRPH_MODE, 3);
1349 break;
1350 default:
1351 return false;
1352 }
1353
1354 } else
1355 /* by pass */
1356 REG_SET(OUTPUT_CSC_CONTROL, 0,
1357 OUTPUT_CSC_GRPH_MODE, 0);
1358
1359 return true;
1360 }
1361
1362 void dce110_opp_set_csc_adjustment(
1363 struct transform *xfm,
1364 const struct out_csc_color_matrix *tbl_entry)
1365 {
1366 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1367 enum csc_color_mode config =
1368 CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
1369
1370 program_color_matrix(
1371 xfm_dce, tbl_entry, GRPH_COLOR_MATRIX_SW);
1372
1373 /* We did everything ,now program DxOUTPUT_CSC_CONTROL */
1374 configure_graphics_mode(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
1375 tbl_entry->color_space);
1376 }
1377
1378 void dce110_opp_set_csc_default(
1379 struct transform *xfm,
1380 const struct default_adjustment *default_adjust)
1381 {
1382 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1383 enum csc_color_mode config =
1384 CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
1385
1386 if (default_adjust->force_hw_default == false) {
1387 const struct out_csc_color_matrix *elm;
1388 /* currently parameter not in use */
1389 enum grph_color_adjust_option option =
1390 GRPH_COLOR_MATRIX_HW_DEFAULT;
1391 uint32_t i;
1392 /*
1393 * HW default false we program locally defined matrix
1394 * HW default true we use predefined hw matrix and we
1395 * do not need to program matrix
1396 * OEM wants the HW default via runtime parameter.
1397 */
1398 option = GRPH_COLOR_MATRIX_SW;
1399
1400 for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
1401 elm = &global_color_matrix[i];
1402 if (elm->color_space != default_adjust->out_color_space)
1403 continue;
1404 /* program the matrix with default values from this
1405 * file */
1406 program_color_matrix(xfm_dce, elm, option);
1407 config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
1408 break;
1409 }
1410 }
1411
1412 /* configure the what we programmed :
1413 * 1. Default values from this file
1414 * 2. Use hardware default from ROM_A and we do not need to program
1415 * matrix */
1416
1417 configure_graphics_mode(xfm_dce, config,
1418 default_adjust->csc_adjust_type,
1419 default_adjust->out_color_space);
1420 }
1421
1422 static void program_pwl(struct dce_transform *xfm_dce,
1423 const struct pwl_params *params)
1424 {
1425 int retval;
1426 uint8_t max_tries = 10;
1427 uint8_t counter = 0;
1428 uint32_t i = 0;
1429 const struct pwl_result_data *rgb = params->rgb_resulted;
1430
1431 /* Power on LUT memory */
1432 if (REG(DCFE_MEM_PWR_CTRL))
1433 REG_UPDATE(DCFE_MEM_PWR_CTRL,
1434 DCP_REGAMMA_MEM_PWR_DIS, 1);
1435 else
1436 REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
1437 REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
1438
1439 while (counter < max_tries) {
1440 if (REG(DCFE_MEM_PWR_STATUS)) {
1441 REG_GET(DCFE_MEM_PWR_STATUS,
1442 DCP_REGAMMA_MEM_PWR_STATE,
1443 &retval);
1444
1445 if (retval == 0)
1446 break;
1447 ++counter;
1448 } else {
1449 REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
1450 REGAMMA_LUT_MEM_PWR_STATE,
1451 &retval);
1452
1453 if (retval == 0)
1454 break;
1455 ++counter;
1456 }
1457 }
1458
1459 if (counter == max_tries) {
1460 DC_LOG_WARNING("%s: regamma lut was not powered on "
1461 "in a timely manner,"
1462 " programming still proceeds\n",
1463 __func__);
1464 }
1465
1466 REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,
1467 REGAMMA_LUT_WRITE_EN_MASK, 7);
1468
1469 REG_WRITE(REGAMMA_LUT_INDEX, 0);
1470
1471 /* Program REGAMMA_LUT_DATA */
1472 while (i != params->hw_points_num) {
1473
1474 REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
1475 REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
1476 REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
1477 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
1478 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
1479 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
1480
1481 ++rgb;
1482 ++i;
1483 }
1484
1485 /* we are done with DCP LUT memory; re-enable low power mode */
1486 if (REG(DCFE_MEM_PWR_CTRL))
1487 REG_UPDATE(DCFE_MEM_PWR_CTRL,
1488 DCP_REGAMMA_MEM_PWR_DIS, 0);
1489 else
1490 REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
1491 REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
1492 }
1493
1494 static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce,
1495 const struct pwl_params *params)
1496 {
1497 const struct gamma_curve *curve;
1498
1499 REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
1500 REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x,
1501 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
1502
1503 REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
1504 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope);
1505
1506 REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
1507 REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x);
1508
1509 REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
1510 REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
1511 REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_slope);
1512
1513 curve = params->arr_curve_points;
1514
1515 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
1516 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1517 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1518 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1519 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1520 curve += 2;
1521
1522 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
1523 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1524 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1525 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1526 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1527 curve += 2;
1528
1529 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
1530 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1531 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1532 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1533 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1534 curve += 2;
1535
1536 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
1537 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1538 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1539 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1540 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1541 curve += 2;
1542
1543 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
1544 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1545 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1546 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1547 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1548 curve += 2;
1549
1550 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
1551 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1552 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1553 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1554 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1555 curve += 2;
1556
1557 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
1558 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1559 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1560 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1561 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1562 curve += 2;
1563
1564 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
1565 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1566 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1567 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1568 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1569 }
1570
1571
1572
1573 void dce110_opp_program_regamma_pwl(struct transform *xfm,
1574 const struct pwl_params *params)
1575 {
1576 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1577
1578 /* Setup regions */
1579 regamma_config_regions_and_segments(xfm_dce, params);
1580
1581 /* Program PWL */
1582 program_pwl(xfm_dce, params);
1583 }
1584
1585 void dce110_opp_power_on_regamma_lut(struct transform *xfm,
1586 bool power_on)
1587 {
1588 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1589
1590 if (REG(DCFE_MEM_PWR_CTRL))
1591 REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
1592 DCP_REGAMMA_MEM_PWR_DIS, power_on,
1593 DCP_LUT_MEM_PWR_DIS, power_on);
1594 else
1595 REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
1596 REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
1597 DCP_LUT_LIGHT_SLEEP_DIS, power_on);
1598
1599 }
1600
1601 void dce110_opp_set_regamma_mode(struct transform *xfm,
1602 enum opp_regamma mode)
1603 {
1604 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
1605
1606 REG_SET(REGAMMA_CONTROL, 0,
1607 GRPH_REGAMMA_MODE, mode);
1608 }
1609
1610 static const struct transform_funcs dce_transform_funcs = {
1611 .transform_reset = dce_transform_reset,
1612 .transform_set_scaler = dce_transform_set_scaler,
1613 .transform_set_gamut_remap = dce_transform_set_gamut_remap,
1614 .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
1615 .opp_set_csc_default = dce110_opp_set_csc_default,
1616 .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
1617 .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
1618 .opp_set_regamma_mode = dce110_opp_set_regamma_mode,
1619 .transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth,
1620 .transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps
1621 };
1622
1623 #if defined(CONFIG_DRM_AMD_DC_SI)
1624 static const struct transform_funcs dce60_transform_funcs = {
1625 .transform_reset = dce_transform_reset,
1626 .transform_set_scaler = dce60_transform_set_scaler,
1627 .transform_set_gamut_remap = dce_transform_set_gamut_remap,
1628 .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
1629 .opp_set_csc_default = dce110_opp_set_csc_default,
1630 .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
1631 .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
1632 .opp_set_regamma_mode = dce110_opp_set_regamma_mode,
1633 .transform_set_pixel_storage_depth = dce60_transform_set_pixel_storage_depth,
1634 .transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps
1635 };
1636 #endif
1637
1638 /*****************************************/
1639 /* Constructor, Destructor */
1640 /*****************************************/
1641
1642 void dce_transform_construct(
1643 struct dce_transform *xfm_dce,
1644 struct dc_context *ctx,
1645 uint32_t inst,
1646 const struct dce_transform_registers *regs,
1647 const struct dce_transform_shift *xfm_shift,
1648 const struct dce_transform_mask *xfm_mask)
1649 {
1650 xfm_dce->base.ctx = ctx;
1651
1652 xfm_dce->base.inst = inst;
1653 xfm_dce->base.funcs = &dce_transform_funcs;
1654
1655 xfm_dce->regs = regs;
1656 xfm_dce->xfm_shift = xfm_shift;
1657 xfm_dce->xfm_mask = xfm_mask;
1658
1659 xfm_dce->prescaler_on = true;
1660 xfm_dce->lb_pixel_depth_supported =
1661 LB_PIXEL_DEPTH_18BPP |
1662 LB_PIXEL_DEPTH_24BPP |
1663 LB_PIXEL_DEPTH_30BPP;
1664
1665 xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
1666 xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/
1667 }
1668
1669 #if defined(CONFIG_DRM_AMD_DC_SI)
1670 void dce60_transform_construct(
1671 struct dce_transform *xfm_dce,
1672 struct dc_context *ctx,
1673 uint32_t inst,
1674 const struct dce_transform_registers *regs,
1675 const struct dce_transform_shift *xfm_shift,
1676 const struct dce_transform_mask *xfm_mask)
1677 {
1678 xfm_dce->base.ctx = ctx;
1679
1680 xfm_dce->base.inst = inst;
1681 xfm_dce->base.funcs = &dce60_transform_funcs;
1682
1683 xfm_dce->regs = regs;
1684 xfm_dce->xfm_shift = xfm_shift;
1685 xfm_dce->xfm_mask = xfm_mask;
1686
1687 xfm_dce->prescaler_on = true;
1688 xfm_dce->lb_pixel_depth_supported =
1689 LB_PIXEL_DEPTH_18BPP |
1690 LB_PIXEL_DEPTH_24BPP |
1691 LB_PIXEL_DEPTH_30BPP;
1692
1693 xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
1694 xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/
1695 }
1696 #endif
Linux with added FPC-III support