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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dce100 / dce100_resource.c
blob8ab9d6c7980817e01e9edef156f6cf67080b00ef
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "link_encoder.h"
31 #include "stream_encoder.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "../virtual/virtual_stream_encoder.h"
36 #include "dce110/dce110_resource.h"
37 #include "dce110/dce110_timing_generator.h"
38 #include "irq/dce110/irq_service_dce110.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce/dce_ipp.h"
43 #include "dce/dce_transform.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_clock_source.h"
46 #include "dce/dce_audio.h"
47 #include "dce/dce_hwseq.h"
48 #include "dce100/dce100_hw_sequencer.h"
49 #include "dce/dce_panel_cntl.h"
50
51 #include "reg_helper.h"
52
53 #include "dce/dce_10_0_d.h"
54 #include "dce/dce_10_0_sh_mask.h"
55
56 #include "dce/dce_dmcu.h"
57 #include "dce/dce_aux.h"
58 #include "dce/dce_abm.h"
59 #include "dce/dce_i2c.h"
60
61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
62 #include "gmc/gmc_8_2_d.h"
63 #include "gmc/gmc_8_2_sh_mask.h"
64 #endif
65
66 #ifndef mmDP_DPHY_INTERNAL_CTRL
67 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
68 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
71 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
72 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
73 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
74 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
75 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
76 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
77 #endif
78
79 #ifndef mmBIOS_SCRATCH_2
80 #define mmBIOS_SCRATCH_2 0x05CB
81 #define mmBIOS_SCRATCH_3 0x05CC
82 #define mmBIOS_SCRATCH_6 0x05CF
83 #endif
84
85 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
86 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
87 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
88 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
89 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
90 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
91 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
92 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
93 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
94 #endif
95
96 #ifndef mmDP_DPHY_FAST_TRAINING
97 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
98 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
99 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
100 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
101 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
102 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
103 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
104 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
105 #endif
106
107 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
108 {
109 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
110 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
111 },
112 {
113 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
114 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
115 },
116 {
117 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
119 },
120 {
121 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
123 },
124 {
125 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
126 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
127 },
128 {
129 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
130 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
131 }
132 };
133
134 /* set register offset */
135 #define SR(reg_name)\
136 .reg_name = mm ## reg_name
137
138 /* set register offset with instance */
139 #define SRI(reg_name, block, id)\
140 .reg_name = mm ## block ## id ## _ ## reg_name
141
142 #define ipp_regs(id)\
143 [id] = {\
144 IPP_DCE100_REG_LIST_DCE_BASE(id)\
145 }
146
147 static const struct dce_ipp_registers ipp_regs[] = {
148 ipp_regs(0),
149 ipp_regs(1),
150 ipp_regs(2),
151 ipp_regs(3),
152 ipp_regs(4),
153 ipp_regs(5)
154 };
155
156 static const struct dce_ipp_shift ipp_shift = {
157 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
158 };
159
160 static const struct dce_ipp_mask ipp_mask = {
161 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
162 };
163
164 #define transform_regs(id)\
165 [id] = {\
166 XFM_COMMON_REG_LIST_DCE100(id)\
167 }
168
169 static const struct dce_transform_registers xfm_regs[] = {
170 transform_regs(0),
171 transform_regs(1),
172 transform_regs(2),
173 transform_regs(3),
174 transform_regs(4),
175 transform_regs(5)
176 };
177
178 static const struct dce_transform_shift xfm_shift = {
179 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
180 };
181
182 static const struct dce_transform_mask xfm_mask = {
183 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
184 };
185
186 #define aux_regs(id)\
187 [id] = {\
188 AUX_REG_LIST(id)\
189 }
190
191 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
192 aux_regs(0),
193 aux_regs(1),
194 aux_regs(2),
195 aux_regs(3),
196 aux_regs(4),
197 aux_regs(5)
198 };
199
200 #define hpd_regs(id)\
201 [id] = {\
202 HPD_REG_LIST(id)\
203 }
204
205 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
206 hpd_regs(0),
207 hpd_regs(1),
208 hpd_regs(2),
209 hpd_regs(3),
210 hpd_regs(4),
211 hpd_regs(5)
212 };
213
214 #define link_regs(id)\
215 [id] = {\
216 LE_DCE100_REG_LIST(id)\
217 }
218
219 static const struct dce110_link_enc_registers link_enc_regs[] = {
220 link_regs(0),
221 link_regs(1),
222 link_regs(2),
223 link_regs(3),
224 link_regs(4),
225 link_regs(5),
226 link_regs(6),
227 };
228
229 #define stream_enc_regs(id)\
230 [id] = {\
231 SE_COMMON_REG_LIST_DCE_BASE(id),\
232 .AFMT_CNTL = 0,\
233 }
234
235 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
236 stream_enc_regs(0),
237 stream_enc_regs(1),
238 stream_enc_regs(2),
239 stream_enc_regs(3),
240 stream_enc_regs(4),
241 stream_enc_regs(5),
242 stream_enc_regs(6)
243 };
244
245 static const struct dce_stream_encoder_shift se_shift = {
246 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
247 };
248
249 static const struct dce_stream_encoder_mask se_mask = {
250 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
251 };
252
253 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
254 { DCE_PANEL_CNTL_REG_LIST() }
255 };
256
257 static const struct dce_panel_cntl_shift panel_cntl_shift = {
258 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
259 };
260
261 static const struct dce_panel_cntl_mask panel_cntl_mask = {
262 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
263 };
264
265 #define opp_regs(id)\
266 [id] = {\
267 OPP_DCE_100_REG_LIST(id),\
268 }
269
270 static const struct dce_opp_registers opp_regs[] = {
271 opp_regs(0),
272 opp_regs(1),
273 opp_regs(2),
274 opp_regs(3),
275 opp_regs(4),
276 opp_regs(5)
277 };
278
279 static const struct dce_opp_shift opp_shift = {
280 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
281 };
282
283 static const struct dce_opp_mask opp_mask = {
284 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
285 };
286 #define aux_engine_regs(id)\
287 [id] = {\
288 AUX_COMMON_REG_LIST(id), \
289 .AUX_RESET_MASK = 0 \
290 }
291
292 static const struct dce110_aux_registers aux_engine_regs[] = {
293 aux_engine_regs(0),
294 aux_engine_regs(1),
295 aux_engine_regs(2),
296 aux_engine_regs(3),
297 aux_engine_regs(4),
298 aux_engine_regs(5)
299 };
300
301 #define audio_regs(id)\
302 [id] = {\
303 AUD_COMMON_REG_LIST(id)\
304 }
305
306 static const struct dce_audio_registers audio_regs[] = {
307 audio_regs(0),
308 audio_regs(1),
309 audio_regs(2),
310 audio_regs(3),
311 audio_regs(4),
312 audio_regs(5),
313 audio_regs(6),
314 };
315
316 static const struct dce_audio_shift audio_shift = {
317 AUD_COMMON_MASK_SH_LIST(__SHIFT)
318 };
319
320 static const struct dce_audio_mask audio_mask = {
321 AUD_COMMON_MASK_SH_LIST(_MASK)
322 };
323
324 #define clk_src_regs(id)\
325 [id] = {\
326 CS_COMMON_REG_LIST_DCE_100_110(id),\
327 }
328
329 static const struct dce110_clk_src_regs clk_src_regs[] = {
330 clk_src_regs(0),
331 clk_src_regs(1),
332 clk_src_regs(2)
333 };
334
335 static const struct dce110_clk_src_shift cs_shift = {
336 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
337 };
338
339 static const struct dce110_clk_src_mask cs_mask = {
340 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
341 };
342
343 static const struct dce_dmcu_registers dmcu_regs = {
344 DMCU_DCE110_COMMON_REG_LIST()
345 };
346
347 static const struct dce_dmcu_shift dmcu_shift = {
348 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
349 };
350
351 static const struct dce_dmcu_mask dmcu_mask = {
352 DMCU_MASK_SH_LIST_DCE110(_MASK)
353 };
354
355 static const struct dce_abm_registers abm_regs = {
356 ABM_DCE110_COMMON_REG_LIST()
357 };
358
359 static const struct dce_abm_shift abm_shift = {
360 ABM_MASK_SH_LIST_DCE110(__SHIFT)
361 };
362
363 static const struct dce_abm_mask abm_mask = {
364 ABM_MASK_SH_LIST_DCE110(_MASK)
365 };
366
367 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
368
369 static const struct bios_registers bios_regs = {
370 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
371 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
372 };
373
374 static const struct resource_caps res_cap = {
375 .num_timing_generator = 6,
376 .num_audio = 6,
377 .num_stream_encoder = 6,
378 .num_pll = 3,
379 .num_ddc = 6,
380 };
381
382 static const struct dc_plane_cap plane_cap = {
383 .type = DC_PLANE_TYPE_DCE_RGB,
384
385 .pixel_format_support = {
386 .argb8888 = true,
387 .nv12 = false,
388 .fp16 = false
389 },
390
391 .max_upscale_factor = {
392 .argb8888 = 16000,
393 .nv12 = 1,
394 .fp16 = 1
395 },
396
397 .max_downscale_factor = {
398 .argb8888 = 250,
399 .nv12 = 1,
400 .fp16 = 1
401 }
402 };
403
404 #define CTX ctx
405 #define REG(reg) mm ## reg
406
407 #ifndef mmCC_DC_HDMI_STRAPS
408 #define mmCC_DC_HDMI_STRAPS 0x1918
409 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
410 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
411 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
412 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
413 #endif
414
415 static int map_transmitter_id_to_phy_instance(
416 enum transmitter transmitter)
417 {
418 switch (transmitter) {
419 case TRANSMITTER_UNIPHY_A:
420 return 0;
421 case TRANSMITTER_UNIPHY_B:
422 return 1;
423 case TRANSMITTER_UNIPHY_C:
424 return 2;
425 case TRANSMITTER_UNIPHY_D:
426 return 3;
427 case TRANSMITTER_UNIPHY_E:
428 return 4;
429 case TRANSMITTER_UNIPHY_F:
430 return 5;
431 case TRANSMITTER_UNIPHY_G:
432 return 6;
433 default:
434 ASSERT(0);
435 return 0;
436 }
437 }
438
439 static void read_dce_straps(
440 struct dc_context *ctx,
441 struct resource_straps *straps)
442 {
443 REG_GET_2(CC_DC_HDMI_STRAPS,
444 HDMI_DISABLE, &straps->hdmi_disable,
445 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
446
447 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
448 }
449
450 static struct audio *create_audio(
451 struct dc_context *ctx, unsigned int inst)
452 {
453 return dce_audio_create(ctx, inst,
454 &audio_regs[inst], &audio_shift, &audio_mask);
455 }
456
457 static struct timing_generator *dce100_timing_generator_create(
458 struct dc_context *ctx,
459 uint32_t instance,
460 const struct dce110_timing_generator_offsets *offsets)
461 {
462 struct dce110_timing_generator *tg110 =
463 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
464
465 if (!tg110)
466 return NULL;
467
468 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
469 return &tg110->base;
470 }
471
472 static struct stream_encoder *dce100_stream_encoder_create(
473 enum engine_id eng_id,
474 struct dc_context *ctx)
475 {
476 struct dce110_stream_encoder *enc110 =
477 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
478
479 if (!enc110)
480 return NULL;
481
482 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
483 &stream_enc_regs[eng_id], &se_shift, &se_mask);
484 return &enc110->base;
485 }
486
487 #define SRII(reg_name, block, id)\
488 .reg_name[id] = mm ## block ## id ## _ ## reg_name
489
490 static const struct dce_hwseq_registers hwseq_reg = {
491 HWSEQ_DCE10_REG_LIST()
492 };
493
494 static const struct dce_hwseq_shift hwseq_shift = {
495 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
496 };
497
498 static const struct dce_hwseq_mask hwseq_mask = {
499 HWSEQ_DCE10_MASK_SH_LIST(_MASK)
500 };
501
502 static struct dce_hwseq *dce100_hwseq_create(
503 struct dc_context *ctx)
504 {
505 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
506
507 if (hws) {
508 hws->ctx = ctx;
509 hws->regs = &hwseq_reg;
510 hws->shifts = &hwseq_shift;
511 hws->masks = &hwseq_mask;
512 }
513 return hws;
514 }
515
516 static const struct resource_create_funcs res_create_funcs = {
517 .read_dce_straps = read_dce_straps,
518 .create_audio = create_audio,
519 .create_stream_encoder = dce100_stream_encoder_create,
520 .create_hwseq = dce100_hwseq_create,
521 };
522
523 #define mi_inst_regs(id) { \
524 MI_DCE8_REG_LIST(id), \
525 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
526 }
527 static const struct dce_mem_input_registers mi_regs[] = {
528 mi_inst_regs(0),
529 mi_inst_regs(1),
530 mi_inst_regs(2),
531 mi_inst_regs(3),
532 mi_inst_regs(4),
533 mi_inst_regs(5),
534 };
535
536 static const struct dce_mem_input_shift mi_shifts = {
537 MI_DCE8_MASK_SH_LIST(__SHIFT),
538 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
539 };
540
541 static const struct dce_mem_input_mask mi_masks = {
542 MI_DCE8_MASK_SH_LIST(_MASK),
543 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
544 };
545
546 static const struct dce110_aux_registers_shift aux_shift = {
547 DCE10_AUX_MASK_SH_LIST(__SHIFT)
548 };
549
550 static const struct dce110_aux_registers_mask aux_mask = {
551 DCE10_AUX_MASK_SH_LIST(_MASK)
552 };
553
554 static struct mem_input *dce100_mem_input_create(
555 struct dc_context *ctx,
556 uint32_t inst)
557 {
558 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
559 GFP_KERNEL);
560
561 if (!dce_mi) {
562 BREAK_TO_DEBUGGER();
563 return NULL;
564 }
565
566 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
567 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
568 return &dce_mi->base;
569 }
570
571 static void dce100_transform_destroy(struct transform **xfm)
572 {
573 kfree(TO_DCE_TRANSFORM(*xfm));
574 *xfm = NULL;
575 }
576
577 static struct transform *dce100_transform_create(
578 struct dc_context *ctx,
579 uint32_t inst)
580 {
581 struct dce_transform *transform =
582 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
583
584 if (!transform)
585 return NULL;
586
587 dce_transform_construct(transform, ctx, inst,
588 &xfm_regs[inst], &xfm_shift, &xfm_mask);
589 return &transform->base;
590 }
591
592 static struct input_pixel_processor *dce100_ipp_create(
593 struct dc_context *ctx, uint32_t inst)
594 {
595 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
596
597 if (!ipp) {
598 BREAK_TO_DEBUGGER();
599 return NULL;
600 }
601
602 dce_ipp_construct(ipp, ctx, inst,
603 &ipp_regs[inst], &ipp_shift, &ipp_mask);
604 return &ipp->base;
605 }
606
607 static const struct encoder_feature_support link_enc_feature = {
608 .max_hdmi_deep_color = COLOR_DEPTH_121212,
609 .max_hdmi_pixel_clock = 300000,
610 .flags.bits.IS_HBR2_CAPABLE = true,
611 .flags.bits.IS_TPS3_CAPABLE = true
612 };
613
614 struct link_encoder *dce100_link_encoder_create(
615 const struct encoder_init_data *enc_init_data)
616 {
617 struct dce110_link_encoder *enc110 =
618 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
619 int link_regs_id;
620
621 if (!enc110)
622 return NULL;
623
624 link_regs_id =
625 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
626
627 dce110_link_encoder_construct(enc110,
628 enc_init_data,
629 &link_enc_feature,
630 &link_enc_regs[link_regs_id],
631 &link_enc_aux_regs[enc_init_data->channel - 1],
632 &link_enc_hpd_regs[enc_init_data->hpd_source]);
633 return &enc110->base;
634 }
635
636 static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_data *init_data)
637 {
638 struct dce_panel_cntl *panel_cntl =
639 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
640
641 if (!panel_cntl)
642 return NULL;
643
644 dce_panel_cntl_construct(panel_cntl,
645 init_data,
646 &panel_cntl_regs[init_data->inst],
647 &panel_cntl_shift,
648 &panel_cntl_mask);
649
650 return &panel_cntl->base;
651 }
652
653 struct output_pixel_processor *dce100_opp_create(
654 struct dc_context *ctx,
655 uint32_t inst)
656 {
657 struct dce110_opp *opp =
658 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
659
660 if (!opp)
661 return NULL;
662
663 dce110_opp_construct(opp,
664 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
665 return &opp->base;
666 }
667
668 struct dce_aux *dce100_aux_engine_create(
669 struct dc_context *ctx,
670 uint32_t inst)
671 {
672 struct aux_engine_dce110 *aux_engine =
673 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
674
675 if (!aux_engine)
676 return NULL;
677
678 dce110_aux_engine_construct(aux_engine, ctx, inst,
679 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
680 &aux_engine_regs[inst],
681 &aux_mask,
682 &aux_shift,
683 ctx->dc->caps.extended_aux_timeout_support);
684
685 return &aux_engine->base;
686 }
687 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
688
689 static const struct dce_i2c_registers i2c_hw_regs[] = {
690 i2c_inst_regs(1),
691 i2c_inst_regs(2),
692 i2c_inst_regs(3),
693 i2c_inst_regs(4),
694 i2c_inst_regs(5),
695 i2c_inst_regs(6),
696 };
697
698 static const struct dce_i2c_shift i2c_shifts = {
699 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
700 };
701
702 static const struct dce_i2c_mask i2c_masks = {
703 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
704 };
705
706 struct dce_i2c_hw *dce100_i2c_hw_create(
707 struct dc_context *ctx,
708 uint32_t inst)
709 {
710 struct dce_i2c_hw *dce_i2c_hw =
711 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
712
713 if (!dce_i2c_hw)
714 return NULL;
715
716 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
717 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
718
719 return dce_i2c_hw;
720 }
721 struct clock_source *dce100_clock_source_create(
722 struct dc_context *ctx,
723 struct dc_bios *bios,
724 enum clock_source_id id,
725 const struct dce110_clk_src_regs *regs,
726 bool dp_clk_src)
727 {
728 struct dce110_clk_src *clk_src =
729 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
730
731 if (!clk_src)
732 return NULL;
733
734 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
735 regs, &cs_shift, &cs_mask)) {
736 clk_src->base.dp_clk_src = dp_clk_src;
737 return &clk_src->base;
738 }
739
740 kfree(clk_src);
741 BREAK_TO_DEBUGGER();
742 return NULL;
743 }
744
745 void dce100_clock_source_destroy(struct clock_source **clk_src)
746 {
747 kfree(TO_DCE110_CLK_SRC(*clk_src));
748 *clk_src = NULL;
749 }
750
751 static void dce100_resource_destruct(struct dce110_resource_pool *pool)
752 {
753 unsigned int i;
754
755 for (i = 0; i < pool->base.pipe_count; i++) {
756 if (pool->base.opps[i] != NULL)
757 dce110_opp_destroy(&pool->base.opps[i]);
758
759 if (pool->base.transforms[i] != NULL)
760 dce100_transform_destroy(&pool->base.transforms[i]);
761
762 if (pool->base.ipps[i] != NULL)
763 dce_ipp_destroy(&pool->base.ipps[i]);
764
765 if (pool->base.mis[i] != NULL) {
766 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
767 pool->base.mis[i] = NULL;
768 }
769
770 if (pool->base.timing_generators[i] != NULL) {
771 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
772 pool->base.timing_generators[i] = NULL;
773 }
774 }
775
776 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
777 if (pool->base.engines[i] != NULL)
778 dce110_engine_destroy(&pool->base.engines[i]);
779 if (pool->base.hw_i2cs[i] != NULL) {
780 kfree(pool->base.hw_i2cs[i]);
781 pool->base.hw_i2cs[i] = NULL;
782 }
783 if (pool->base.sw_i2cs[i] != NULL) {
784 kfree(pool->base.sw_i2cs[i]);
785 pool->base.sw_i2cs[i] = NULL;
786 }
787 }
788
789 for (i = 0; i < pool->base.stream_enc_count; i++) {
790 if (pool->base.stream_enc[i] != NULL)
791 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
792 }
793
794 for (i = 0; i < pool->base.clk_src_count; i++) {
795 if (pool->base.clock_sources[i] != NULL)
796 dce100_clock_source_destroy(&pool->base.clock_sources[i]);
797 }
798
799 if (pool->base.dp_clock_source != NULL)
800 dce100_clock_source_destroy(&pool->base.dp_clock_source);
801
802 for (i = 0; i < pool->base.audio_count; i++) {
803 if (pool->base.audios[i] != NULL)
804 dce_aud_destroy(&pool->base.audios[i]);
805 }
806
807 if (pool->base.abm != NULL)
808 dce_abm_destroy(&pool->base.abm);
809
810 if (pool->base.dmcu != NULL)
811 dce_dmcu_destroy(&pool->base.dmcu);
812
813 if (pool->base.irqs != NULL)
814 dal_irq_service_destroy(&pool->base.irqs);
815 }
816
817 static enum dc_status build_mapped_resource(
818 const struct dc *dc,
819 struct dc_state *context,
820 struct dc_stream_state *stream)
821 {
822 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
823
824 if (!pipe_ctx)
825 return DC_ERROR_UNEXPECTED;
826
827 dce110_resource_build_pipe_hw_param(pipe_ctx);
828
829 resource_build_info_frame(pipe_ctx);
830
831 return DC_OK;
832 }
833
834 bool dce100_validate_bandwidth(
835 struct dc *dc,
836 struct dc_state *context,
837 bool fast_validate)
838 {
839 int i;
840 bool at_least_one_pipe = false;
841
842 for (i = 0; i < dc->res_pool->pipe_count; i++) {
843 if (context->res_ctx.pipe_ctx[i].stream)
844 at_least_one_pipe = true;
845 }
846
847 if (at_least_one_pipe) {
848 /* TODO implement when needed but for now hardcode max value*/
849 context->bw_ctx.bw.dce.dispclk_khz = 681000;
850 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
851 } else {
852 context->bw_ctx.bw.dce.dispclk_khz = 0;
853 context->bw_ctx.bw.dce.yclk_khz = 0;
854 }
855
856 return true;
857 }
858
859 static bool dce100_validate_surface_sets(
860 struct dc_state *context)
861 {
862 int i;
863
864 for (i = 0; i < context->stream_count; i++) {
865 if (context->stream_status[i].plane_count == 0)
866 continue;
867
868 if (context->stream_status[i].plane_count > 1)
869 return false;
870
871 if (context->stream_status[i].plane_states[0]->format
872 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
873 return false;
874 }
875
876 return true;
877 }
878
879 enum dc_status dce100_validate_global(
880 struct dc *dc,
881 struct dc_state *context)
882 {
883 if (!dce100_validate_surface_sets(context))
884 return DC_FAIL_SURFACE_VALIDATE;
885
886 return DC_OK;
887 }
888
889 enum dc_status dce100_add_stream_to_ctx(
890 struct dc *dc,
891 struct dc_state *new_ctx,
892 struct dc_stream_state *dc_stream)
893 {
894 enum dc_status result = DC_ERROR_UNEXPECTED;
895
896 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
897
898 if (result == DC_OK)
899 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
900
901 if (result == DC_OK)
902 result = build_mapped_resource(dc, new_ctx, dc_stream);
903
904 return result;
905 }
906
907 static void dce100_destroy_resource_pool(struct resource_pool **pool)
908 {
909 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
910
911 dce100_resource_destruct(dce110_pool);
912 kfree(dce110_pool);
913 *pool = NULL;
914 }
915
916 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
917 {
918
919 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
920 return DC_OK;
921
922 return DC_FAIL_SURFACE_VALIDATE;
923 }
924
925 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
926 struct resource_context *res_ctx,
927 const struct resource_pool *pool,
928 struct dc_stream_state *stream)
929 {
930 int i;
931 int j = -1;
932 struct dc_link *link = stream->link;
933
934 for (i = 0; i < pool->stream_enc_count; i++) {
935 if (!res_ctx->is_stream_enc_acquired[i] &&
936 pool->stream_enc[i]) {
937 /* Store first available for MST second display
938 * in daisy chain use case
939 */
940 j = i;
941 if (pool->stream_enc[i]->id ==
942 link->link_enc->preferred_engine)
943 return pool->stream_enc[i];
944 }
945 }
946
947 /*
948 * below can happen in cases when stream encoder is acquired:
949 * 1) for second MST display in chain, so preferred engine already
950 * acquired;
951 * 2) for another link, which preferred engine already acquired by any
952 * MST configuration.
953 *
954 * If signal is of DP type and preferred engine not found, return last available
955 *
956 * TODO - This is just a patch up and a generic solution is
957 * required for non DP connectors.
958 */
959
960 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
961 return pool->stream_enc[j];
962
963 return NULL;
964 }
965
966 static const struct resource_funcs dce100_res_pool_funcs = {
967 .destroy = dce100_destroy_resource_pool,
968 .link_enc_create = dce100_link_encoder_create,
969 .panel_cntl_create = dce100_panel_cntl_create,
970 .validate_bandwidth = dce100_validate_bandwidth,
971 .validate_plane = dce100_validate_plane,
972 .add_stream_to_ctx = dce100_add_stream_to_ctx,
973 .validate_global = dce100_validate_global,
974 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
975 };
976
977 static bool dce100_resource_construct(
978 uint8_t num_virtual_links,
979 struct dc *dc,
980 struct dce110_resource_pool *pool)
981 {
982 unsigned int i;
983 struct dc_context *ctx = dc->ctx;
984 struct dc_bios *bp;
985
986 ctx->dc_bios->regs = &bios_regs;
987
988 pool->base.res_cap = &res_cap;
989 pool->base.funcs = &dce100_res_pool_funcs;
990 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
991
992 bp = ctx->dc_bios;
993
994 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
995 pool->base.dp_clock_source =
996 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
997
998 pool->base.clock_sources[0] =
999 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1000 pool->base.clock_sources[1] =
1001 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1002 pool->base.clock_sources[2] =
1003 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1004 pool->base.clk_src_count = 3;
1005
1006 } else {
1007 pool->base.dp_clock_source =
1008 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1009
1010 pool->base.clock_sources[0] =
1011 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1012 pool->base.clock_sources[1] =
1013 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1014 pool->base.clk_src_count = 2;
1015 }
1016
1017 if (pool->base.dp_clock_source == NULL) {
1018 dm_error("DC: failed to create dp clock source!\n");
1019 BREAK_TO_DEBUGGER();
1020 goto res_create_fail;
1021 }
1022
1023 for (i = 0; i < pool->base.clk_src_count; i++) {
1024 if (pool->base.clock_sources[i] == NULL) {
1025 dm_error("DC: failed to create clock sources!\n");
1026 BREAK_TO_DEBUGGER();
1027 goto res_create_fail;
1028 }
1029 }
1030
1031 pool->base.dmcu = dce_dmcu_create(ctx,
1032 &dmcu_regs,
1033 &dmcu_shift,
1034 &dmcu_mask);
1035 if (pool->base.dmcu == NULL) {
1036 dm_error("DC: failed to create dmcu!\n");
1037 BREAK_TO_DEBUGGER();
1038 goto res_create_fail;
1039 }
1040
1041 pool->base.abm = dce_abm_create(ctx,
1042 &abm_regs,
1043 &abm_shift,
1044 &abm_mask);
1045 if (pool->base.abm == NULL) {
1046 dm_error("DC: failed to create abm!\n");
1047 BREAK_TO_DEBUGGER();
1048 goto res_create_fail;
1049 }
1050
1051 {
1052 struct irq_service_init_data init_data;
1053 init_data.ctx = dc->ctx;
1054 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1055 if (!pool->base.irqs)
1056 goto res_create_fail;
1057 }
1058
1059 /*************************************************
1060 * Resource + asic cap harcoding *
1061 *************************************************/
1062 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1063 pool->base.pipe_count = res_cap.num_timing_generator;
1064 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1065 dc->caps.max_downscale_ratio = 200;
1066 dc->caps.i2c_speed_in_khz = 40;
1067 dc->caps.i2c_speed_in_khz = 40;
1068 dc->caps.max_cursor_size = 128;
1069 dc->caps.min_horizontal_blanking_period = 80;
1070 dc->caps.dual_link_dvi = true;
1071 dc->caps.disable_dp_clk_share = true;
1072 dc->caps.extended_aux_timeout_support = false;
1073
1074 for (i = 0; i < pool->base.pipe_count; i++) {
1075 pool->base.timing_generators[i] =
1076 dce100_timing_generator_create(
1077 ctx,
1078 i,
1079 &dce100_tg_offsets[i]);
1080 if (pool->base.timing_generators[i] == NULL) {
1081 BREAK_TO_DEBUGGER();
1082 dm_error("DC: failed to create tg!\n");
1083 goto res_create_fail;
1084 }
1085
1086 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
1087 if (pool->base.mis[i] == NULL) {
1088 BREAK_TO_DEBUGGER();
1089 dm_error(
1090 "DC: failed to create memory input!\n");
1091 goto res_create_fail;
1092 }
1093
1094 pool->base.ipps[i] = dce100_ipp_create(ctx, i);
1095 if (pool->base.ipps[i] == NULL) {
1096 BREAK_TO_DEBUGGER();
1097 dm_error(
1098 "DC: failed to create input pixel processor!\n");
1099 goto res_create_fail;
1100 }
1101
1102 pool->base.transforms[i] = dce100_transform_create(ctx, i);
1103 if (pool->base.transforms[i] == NULL) {
1104 BREAK_TO_DEBUGGER();
1105 dm_error(
1106 "DC: failed to create transform!\n");
1107 goto res_create_fail;
1108 }
1109
1110 pool->base.opps[i] = dce100_opp_create(ctx, i);
1111 if (pool->base.opps[i] == NULL) {
1112 BREAK_TO_DEBUGGER();
1113 dm_error(
1114 "DC: failed to create output pixel processor!\n");
1115 goto res_create_fail;
1116 }
1117 }
1118
1119 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1120 pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
1121 if (pool->base.engines[i] == NULL) {
1122 BREAK_TO_DEBUGGER();
1123 dm_error(
1124 "DC:failed to create aux engine!!\n");
1125 goto res_create_fail;
1126 }
1127 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);
1128 if (pool->base.hw_i2cs[i] == NULL) {
1129 BREAK_TO_DEBUGGER();
1130 dm_error(
1131 "DC:failed to create i2c engine!!\n");
1132 goto res_create_fail;
1133 }
1134 pool->base.sw_i2cs[i] = NULL;
1135 }
1136
1137 dc->caps.max_planes = pool->base.pipe_count;
1138
1139 for (i = 0; i < dc->caps.max_planes; ++i)
1140 dc->caps.planes[i] = plane_cap;
1141
1142 if (!resource_construct(num_virtual_links, dc, &pool->base,
1143 &res_create_funcs))
1144 goto res_create_fail;
1145
1146 /* Create hardware sequencer */
1147 dce100_hw_sequencer_construct(dc);
1148 return true;
1149
1150 res_create_fail:
1151 dce100_resource_destruct(pool);
1152
1153 return false;
1154 }
1155
1156 struct resource_pool *dce100_create_resource_pool(
1157 uint8_t num_virtual_links,
1158 struct dc *dc)
1159 {
1160 struct dce110_resource_pool *pool =
1161 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1162
1163 if (!pool)
1164 return NULL;
1165
1166 if (dce100_resource_construct(num_virtual_links, dc, pool))
1167 return &pool->base;
1168
1169 kfree(pool);
1170 BREAK_TO_DEBUGGER();
1171 return NULL;
1172 }
1173
Linux with added FPC-III support