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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
blob4c230f1de9a30e7daf1c1c828036213aa4cdb7c8
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/delay.h>
27
28 #include "dm_services.h"
29 #include "dc.h"
30 #include "dc_bios_types.h"
31 #include "core_types.h"
32 #include "core_status.h"
33 #include "resource.h"
34 #include "dm_helpers.h"
35 #include "dce110_hw_sequencer.h"
36 #include "dce110_timing_generator.h"
37 #include "dce/dce_hwseq.h"
38 #include "gpio_service_interface.h"
39
40 #include "dce110_compressor.h"
41
42 #include "bios/bios_parser_helper.h"
43 #include "timing_generator.h"
44 #include "mem_input.h"
45 #include "opp.h"
46 #include "ipp.h"
47 #include "transform.h"
48 #include "stream_encoder.h"
49 #include "link_encoder.h"
50 #include "link_hwss.h"
51 #include "clock_source.h"
52 #include "clk_mgr.h"
53 #include "abm.h"
54 #include "audio.h"
55 #include "reg_helper.h"
56 #include "panel_cntl.h"
57
58 /* include DCE11 register header files */
59 #include "dce/dce_11_0_d.h"
60 #include "dce/dce_11_0_sh_mask.h"
61 #include "custom_float.h"
62
63 #include "atomfirmware.h"
64
65 #define GAMMA_HW_POINTS_NUM 256
66
67 /*
68 * All values are in milliseconds;
69 * For eDP, after power-up/power/down,
70 * 300/500 msec max. delay from LCDVCC to black video generation
71 */
72 #define PANEL_POWER_UP_TIMEOUT 300
73 #define PANEL_POWER_DOWN_TIMEOUT 500
74 #define HPD_CHECK_INTERVAL 10
75 #define OLED_POST_T7_DELAY 100
76 #define OLED_PRE_T11_DELAY 150
77
78 #define CTX \
79 hws->ctx
80
81 #define DC_LOGGER_INIT()
82
83 #define REG(reg)\
84 hws->regs->reg
85
86 #undef FN
87 #define FN(reg_name, field_name) \
88 hws->shifts->field_name, hws->masks->field_name
89
90 struct dce110_hw_seq_reg_offsets {
91 uint32_t crtc;
92 };
93
94 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
95 {
96 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
97 },
98 {
99 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
100 },
101 {
102 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
103 },
104 {
105 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
106 }
107 };
108
109 #define HW_REG_BLND(reg, id)\
110 (reg + reg_offsets[id].blnd)
111
112 #define HW_REG_CRTC(reg, id)\
113 (reg + reg_offsets[id].crtc)
114
115 #define MAX_WATERMARK 0xFFFF
116 #define SAFE_NBP_MARK 0x7FFF
117
118 /*******************************************************************************
119 * Private definitions
120 ******************************************************************************/
121 /***************************PIPE_CONTROL***********************************/
122 static void dce110_init_pte(struct dc_context *ctx)
123 {
124 uint32_t addr;
125 uint32_t value = 0;
126 uint32_t chunk_int = 0;
127 uint32_t chunk_mul = 0;
128
129 addr = mmUNP_DVMM_PTE_CONTROL;
130 value = dm_read_reg(ctx, addr);
131
132 set_reg_field_value(
133 value,
134 0,
135 DVMM_PTE_CONTROL,
136 DVMM_USE_SINGLE_PTE);
137
138 set_reg_field_value(
139 value,
140 1,
141 DVMM_PTE_CONTROL,
142 DVMM_PTE_BUFFER_MODE0);
143
144 set_reg_field_value(
145 value,
146 1,
147 DVMM_PTE_CONTROL,
148 DVMM_PTE_BUFFER_MODE1);
149
150 dm_write_reg(ctx, addr, value);
151
152 addr = mmDVMM_PTE_REQ;
153 value = dm_read_reg(ctx, addr);
154
155 chunk_int = get_reg_field_value(
156 value,
157 DVMM_PTE_REQ,
158 HFLIP_PTEREQ_PER_CHUNK_INT);
159
160 chunk_mul = get_reg_field_value(
161 value,
162 DVMM_PTE_REQ,
163 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
164
165 if (chunk_int != 0x4 || chunk_mul != 0x4) {
166
167 set_reg_field_value(
168 value,
169 255,
170 DVMM_PTE_REQ,
171 MAX_PTEREQ_TO_ISSUE);
172
173 set_reg_field_value(
174 value,
175 4,
176 DVMM_PTE_REQ,
177 HFLIP_PTEREQ_PER_CHUNK_INT);
178
179 set_reg_field_value(
180 value,
181 4,
182 DVMM_PTE_REQ,
183 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
184
185 dm_write_reg(ctx, addr, value);
186 }
187 }
188 /**************************************************************************/
189
190 static void enable_display_pipe_clock_gating(
191 struct dc_context *ctx,
192 bool clock_gating)
193 {
194 /*TODO*/
195 }
196
197 static bool dce110_enable_display_power_gating(
198 struct dc *dc,
199 uint8_t controller_id,
200 struct dc_bios *dcb,
201 enum pipe_gating_control power_gating)
202 {
203 enum bp_result bp_result = BP_RESULT_OK;
204 enum bp_pipe_control_action cntl;
205 struct dc_context *ctx = dc->ctx;
206 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
207
208 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
209 return true;
210
211 if (power_gating == PIPE_GATING_CONTROL_INIT)
212 cntl = ASIC_PIPE_INIT;
213 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
214 cntl = ASIC_PIPE_ENABLE;
215 else
216 cntl = ASIC_PIPE_DISABLE;
217
218 if (controller_id == underlay_idx)
219 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
220
221 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
222
223 bp_result = dcb->funcs->enable_disp_power_gating(
224 dcb, controller_id + 1, cntl);
225
226 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
227 * by default when command table is called
228 *
229 * Bios parser accepts controller_id = 6 as indicative of
230 * underlay pipe in dce110. But we do not support more
231 * than 3.
232 */
233 if (controller_id < CONTROLLER_ID_MAX - 1)
234 dm_write_reg(ctx,
235 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
236 0);
237 }
238
239 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
240 dce110_init_pte(ctx);
241
242 if (bp_result == BP_RESULT_OK)
243 return true;
244 else
245 return false;
246 }
247
248 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
249 const struct dc_plane_state *plane_state)
250 {
251 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
252
253 switch (plane_state->format) {
254 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
255 prescale_params->scale = 0x2082;
256 break;
257 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
258 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
259 prescale_params->scale = 0x2020;
260 break;
261 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
262 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
263 prescale_params->scale = 0x2008;
264 break;
265 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
266 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
267 prescale_params->scale = 0x2000;
268 break;
269 default:
270 ASSERT(false);
271 break;
272 }
273 }
274
275 static bool
276 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
277 const struct dc_plane_state *plane_state)
278 {
279 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
280 const struct dc_transfer_func *tf = NULL;
281 struct ipp_prescale_params prescale_params = { 0 };
282 bool result = true;
283
284 if (ipp == NULL)
285 return false;
286
287 if (plane_state->in_transfer_func)
288 tf = plane_state->in_transfer_func;
289
290 build_prescale_params(&prescale_params, plane_state);
291 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
292
293 if (plane_state->gamma_correction &&
294 !plane_state->gamma_correction->is_identity &&
295 dce_use_lut(plane_state->format))
296 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
297
298 if (tf == NULL) {
299 /* Default case if no input transfer function specified */
300 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
301 } else if (tf->type == TF_TYPE_PREDEFINED) {
302 switch (tf->tf) {
303 case TRANSFER_FUNCTION_SRGB:
304 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
305 break;
306 case TRANSFER_FUNCTION_BT709:
307 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
308 break;
309 case TRANSFER_FUNCTION_LINEAR:
310 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
311 break;
312 case TRANSFER_FUNCTION_PQ:
313 default:
314 result = false;
315 break;
316 }
317 } else if (tf->type == TF_TYPE_BYPASS) {
318 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
319 } else {
320 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
321 result = false;
322 }
323
324 return result;
325 }
326
327 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
328 struct curve_points *arr_points,
329 uint32_t hw_points_num)
330 {
331 struct custom_float_format fmt;
332
333 struct pwl_result_data *rgb = rgb_resulted;
334
335 uint32_t i = 0;
336
337 fmt.exponenta_bits = 6;
338 fmt.mantissa_bits = 12;
339 fmt.sign = true;
340
341 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
342 &arr_points[0].custom_float_x)) {
343 BREAK_TO_DEBUGGER();
344 return false;
345 }
346
347 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
348 &arr_points[0].custom_float_offset)) {
349 BREAK_TO_DEBUGGER();
350 return false;
351 }
352
353 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
354 &arr_points[0].custom_float_slope)) {
355 BREAK_TO_DEBUGGER();
356 return false;
357 }
358
359 fmt.mantissa_bits = 10;
360 fmt.sign = false;
361
362 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
363 &arr_points[1].custom_float_x)) {
364 BREAK_TO_DEBUGGER();
365 return false;
366 }
367
368 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
369 &arr_points[1].custom_float_y)) {
370 BREAK_TO_DEBUGGER();
371 return false;
372 }
373
374 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
375 &arr_points[1].custom_float_slope)) {
376 BREAK_TO_DEBUGGER();
377 return false;
378 }
379
380 fmt.mantissa_bits = 12;
381 fmt.sign = true;
382
383 while (i != hw_points_num) {
384 if (!convert_to_custom_float_format(rgb->red, &fmt,
385 &rgb->red_reg)) {
386 BREAK_TO_DEBUGGER();
387 return false;
388 }
389
390 if (!convert_to_custom_float_format(rgb->green, &fmt,
391 &rgb->green_reg)) {
392 BREAK_TO_DEBUGGER();
393 return false;
394 }
395
396 if (!convert_to_custom_float_format(rgb->blue, &fmt,
397 &rgb->blue_reg)) {
398 BREAK_TO_DEBUGGER();
399 return false;
400 }
401
402 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
403 &rgb->delta_red_reg)) {
404 BREAK_TO_DEBUGGER();
405 return false;
406 }
407
408 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
409 &rgb->delta_green_reg)) {
410 BREAK_TO_DEBUGGER();
411 return false;
412 }
413
414 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
415 &rgb->delta_blue_reg)) {
416 BREAK_TO_DEBUGGER();
417 return false;
418 }
419
420 ++rgb;
421 ++i;
422 }
423
424 return true;
425 }
426
427 #define MAX_LOW_POINT 25
428 #define NUMBER_REGIONS 16
429 #define NUMBER_SW_SEGMENTS 16
430
431 static bool
432 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
433 struct pwl_params *regamma_params)
434 {
435 struct curve_points *arr_points;
436 struct pwl_result_data *rgb_resulted;
437 struct pwl_result_data *rgb;
438 struct pwl_result_data *rgb_plus_1;
439 struct fixed31_32 y_r;
440 struct fixed31_32 y_g;
441 struct fixed31_32 y_b;
442 struct fixed31_32 y1_min;
443 struct fixed31_32 y3_max;
444
445 int32_t region_start, region_end;
446 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
447
448 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
449 return false;
450
451 arr_points = regamma_params->arr_points;
452 rgb_resulted = regamma_params->rgb_resulted;
453 hw_points = 0;
454
455 memset(regamma_params, 0, sizeof(struct pwl_params));
456
457 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
458 /* 16 segments
459 * segments are from 2^-11 to 2^5
460 */
461 region_start = -11;
462 region_end = region_start + NUMBER_REGIONS;
463
464 for (i = 0; i < NUMBER_REGIONS; i++)
465 seg_distr[i] = 4;
466
467 } else {
468 /* 10 segments
469 * segment is from 2^-10 to 2^1
470 * We include an extra segment for range [2^0, 2^1). This is to
471 * ensure that colors with normalized values of 1 don't miss the
472 * LUT.
473 */
474 region_start = -10;
475 region_end = 1;
476
477 seg_distr[0] = 4;
478 seg_distr[1] = 4;
479 seg_distr[2] = 4;
480 seg_distr[3] = 4;
481 seg_distr[4] = 4;
482 seg_distr[5] = 4;
483 seg_distr[6] = 4;
484 seg_distr[7] = 4;
485 seg_distr[8] = 4;
486 seg_distr[9] = 4;
487 seg_distr[10] = 0;
488 seg_distr[11] = -1;
489 seg_distr[12] = -1;
490 seg_distr[13] = -1;
491 seg_distr[14] = -1;
492 seg_distr[15] = -1;
493 }
494
495 for (k = 0; k < 16; k++) {
496 if (seg_distr[k] != -1)
497 hw_points += (1 << seg_distr[k]);
498 }
499
500 j = 0;
501 for (k = 0; k < (region_end - region_start); k++) {
502 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
503 start_index = (region_start + k + MAX_LOW_POINT) *
504 NUMBER_SW_SEGMENTS;
505 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
506 i += increment) {
507 if (j == hw_points - 1)
508 break;
509 rgb_resulted[j].red = output_tf->tf_pts.red[i];
510 rgb_resulted[j].green = output_tf->tf_pts.green[i];
511 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
512 j++;
513 }
514 }
515
516 /* last point */
517 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
518 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
519 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
520 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
521
522 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
523 dc_fixpt_from_int(region_start));
524 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
525 dc_fixpt_from_int(region_end));
526
527 y_r = rgb_resulted[0].red;
528 y_g = rgb_resulted[0].green;
529 y_b = rgb_resulted[0].blue;
530
531 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
532
533 arr_points[0].y = y1_min;
534 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
535 arr_points[0].x);
536
537 y_r = rgb_resulted[hw_points - 1].red;
538 y_g = rgb_resulted[hw_points - 1].green;
539 y_b = rgb_resulted[hw_points - 1].blue;
540
541 /* see comment above, m_arrPoints[1].y should be the Y value for the
542 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
543 */
544 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
545
546 arr_points[1].y = y3_max;
547
548 arr_points[1].slope = dc_fixpt_zero;
549
550 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
551 /* for PQ, we want to have a straight line from last HW X point,
552 * and the slope to be such that we hit 1.0 at 10000 nits.
553 */
554 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
555
556 arr_points[1].slope = dc_fixpt_div(
557 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
558 dc_fixpt_sub(end_value, arr_points[1].x));
559 }
560
561 regamma_params->hw_points_num = hw_points;
562
563 k = 0;
564 for (i = 1; i < 16; i++) {
565 if (seg_distr[k] != -1) {
566 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
567 regamma_params->arr_curve_points[i].offset =
568 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
569 }
570 k++;
571 }
572
573 if (seg_distr[k] != -1)
574 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
575
576 rgb = rgb_resulted;
577 rgb_plus_1 = rgb_resulted + 1;
578
579 i = 1;
580
581 while (i != hw_points + 1) {
582 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
583 rgb_plus_1->red = rgb->red;
584 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
585 rgb_plus_1->green = rgb->green;
586 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
587 rgb_plus_1->blue = rgb->blue;
588
589 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
590 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
591 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
592
593 ++rgb_plus_1;
594 ++rgb;
595 ++i;
596 }
597
598 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
599
600 return true;
601 }
602
603 static bool
604 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
605 const struct dc_stream_state *stream)
606 {
607 struct transform *xfm = pipe_ctx->plane_res.xfm;
608
609 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
610 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
611
612 if (stream->out_transfer_func &&
613 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
614 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
615 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
616 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
617 &xfm->regamma_params)) {
618 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
619 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
620 } else {
621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
622 }
623
624 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
625
626 return true;
627 }
628
629 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
630 {
631 bool is_hdmi_tmds;
632 bool is_dp;
633
634 ASSERT(pipe_ctx->stream);
635
636 if (pipe_ctx->stream_res.stream_enc == NULL)
637 return; /* this is not root pipe */
638
639 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
640 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
641
642 if (!is_hdmi_tmds && !is_dp)
643 return;
644
645 if (is_hdmi_tmds)
646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
647 pipe_ctx->stream_res.stream_enc,
648 &pipe_ctx->stream_res.encoder_info_frame);
649 else
650 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
651 pipe_ctx->stream_res.stream_enc,
652 &pipe_ctx->stream_res.encoder_info_frame);
653 }
654
655 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
656 {
657 enum dc_lane_count lane_count =
658 pipe_ctx->stream->link->cur_link_settings.lane_count;
659 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
660 struct dc_link *link = pipe_ctx->stream->link;
661 const struct dc *dc = link->dc;
662
663 uint32_t active_total_with_borders;
664 uint32_t early_control = 0;
665 struct timing_generator *tg = pipe_ctx->stream_res.tg;
666
667 /* For MST, there are multiply stream go to only one link.
668 * connect DIG back_end to front_end while enable_stream and
669 * disconnect them during disable_stream
670 * BY this, it is logic clean to separate stream and link */
671 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
672 pipe_ctx->stream_res.stream_enc->id, true);
673
674 dc->hwss.update_info_frame(pipe_ctx);
675
676 /* enable early control to avoid corruption on DP monitor*/
677 active_total_with_borders =
678 timing->h_addressable
679 + timing->h_border_left
680 + timing->h_border_right;
681
682 if (lane_count != 0)
683 early_control = active_total_with_borders % lane_count;
684
685 if (early_control == 0)
686 early_control = lane_count;
687
688 tg->funcs->set_early_control(tg, early_control);
689
690 /* enable audio only within mode set */
691 if (pipe_ctx->stream_res.audio != NULL) {
692 if (dc_is_dp_signal(pipe_ctx->stream->signal))
693 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
694 }
695
696
697
698
699 }
700
701 static enum bp_result link_transmitter_control(
702 struct dc_bios *bios,
703 struct bp_transmitter_control *cntl)
704 {
705 enum bp_result result;
706
707 result = bios->funcs->transmitter_control(bios, cntl);
708
709 return result;
710 }
711
712 /*
713 * @brief
714 * eDP only.
715 */
716 void dce110_edp_wait_for_hpd_ready(
717 struct dc_link *link,
718 bool power_up)
719 {
720 struct dc_context *ctx = link->ctx;
721 struct graphics_object_id connector = link->link_enc->connector;
722 struct gpio *hpd;
723 struct dc_sink *sink = link->local_sink;
724 bool edp_hpd_high = false;
725 uint32_t time_elapsed = 0;
726 uint32_t timeout = power_up ?
727 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
728
729 if (dal_graphics_object_id_get_connector_id(connector)
730 != CONNECTOR_ID_EDP) {
731 BREAK_TO_DEBUGGER();
732 return;
733 }
734
735 if (!power_up)
736 /*
737 * From KV, we will not HPD low after turning off VCC -
738 * instead, we will check the SW timer in power_up().
739 */
740 return;
741
742 /*
743 * When we power on/off the eDP panel,
744 * we need to wait until SENSE bit is high/low.
745 */
746
747 /* obtain HPD */
748 /* TODO what to do with this? */
749 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
750
751 if (!hpd) {
752 BREAK_TO_DEBUGGER();
753 return;
754 }
755
756 if (sink != NULL) {
757 if (sink->edid_caps.panel_patch.extra_t3_ms > 0) {
758 int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms;
759
760 msleep(extra_t3_in_ms);
761 }
762 }
763
764 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
765
766 /* wait until timeout or panel detected */
767
768 do {
769 uint32_t detected = 0;
770
771 dal_gpio_get_value(hpd, &detected);
772
773 if (!(detected ^ power_up)) {
774 edp_hpd_high = true;
775 break;
776 }
777
778 msleep(HPD_CHECK_INTERVAL);
779
780 time_elapsed += HPD_CHECK_INTERVAL;
781 } while (time_elapsed < timeout);
782
783 dal_gpio_close(hpd);
784
785 dal_gpio_destroy_irq(&hpd);
786
787 if (false == edp_hpd_high) {
788 DC_LOG_ERROR(
789 "%s: wait timed out!\n", __func__);
790 }
791 }
792
793 void dce110_edp_power_control(
794 struct dc_link *link,
795 bool power_up)
796 {
797 struct dc_context *ctx = link->ctx;
798 struct bp_transmitter_control cntl = { 0 };
799 enum bp_result bp_result;
800
801
802 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
803 != CONNECTOR_ID_EDP) {
804 BREAK_TO_DEBUGGER();
805 return;
806 }
807
808 if (!link->panel_cntl)
809 return;
810
811 if (power_up !=
812 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
813
814 unsigned long long current_ts = dm_get_timestamp(ctx);
815 unsigned long long time_since_edp_poweroff_ms =
816 div64_u64(dm_get_elapse_time_in_ns(
817 ctx,
818 current_ts,
819 link->link_trace.time_stamp.edp_poweroff), 1000000);
820 unsigned long long time_since_edp_poweron_ms =
821 div64_u64(dm_get_elapse_time_in_ns(
822 ctx,
823 current_ts,
824 link->link_trace.time_stamp.edp_poweron), 1000000);
825 DC_LOG_HW_RESUME_S3(
826 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
827 __func__,
828 power_up,
829 current_ts,
830 link->link_trace.time_stamp.edp_poweroff,
831 link->link_trace.time_stamp.edp_poweron,
832 time_since_edp_poweroff_ms,
833 time_since_edp_poweron_ms);
834
835 /* Send VBIOS command to prompt eDP panel power */
836 if (power_up) {
837 /* edp requires a min of 500ms from LCDVDD off to on */
838 unsigned long long remaining_min_edp_poweroff_time_ms = 500;
839
840 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
841 if (link->local_sink != NULL)
842 remaining_min_edp_poweroff_time_ms +=
843 link->local_sink->edid_caps.panel_patch.extra_t12_ms;
844
845 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
846 if (link->link_trace.time_stamp.edp_poweroff != 0) {
847 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
848 remaining_min_edp_poweroff_time_ms =
849 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
850 else
851 remaining_min_edp_poweroff_time_ms = 0;
852 }
853
854 if (remaining_min_edp_poweroff_time_ms) {
855 DC_LOG_HW_RESUME_S3(
856 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
857 __func__, remaining_min_edp_poweroff_time_ms);
858 msleep(remaining_min_edp_poweroff_time_ms);
859 DC_LOG_HW_RESUME_S3(
860 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
861 __func__, remaining_min_edp_poweroff_time_ms);
862 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
863 __func__, remaining_min_edp_poweroff_time_ms);
864 } else {
865 DC_LOG_HW_RESUME_S3(
866 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
867 __func__, remaining_min_edp_poweroff_time_ms);
868 }
869 }
870
871 DC_LOG_HW_RESUME_S3(
872 "%s: BEGIN: Panel Power action: %s\n",
873 __func__, (power_up ? "On":"Off"));
874
875 cntl.action = power_up ?
876 TRANSMITTER_CONTROL_POWER_ON :
877 TRANSMITTER_CONTROL_POWER_OFF;
878 cntl.transmitter = link->link_enc->transmitter;
879 cntl.connector_obj_id = link->link_enc->connector;
880 cntl.coherent = false;
881 cntl.lanes_number = LANE_COUNT_FOUR;
882 cntl.hpd_sel = link->link_enc->hpd_source;
883
884 if (ctx->dc->ctx->dmub_srv &&
885 ctx->dc->debug.dmub_command_table) {
886 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
887 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
888 LVTMA_CONTROL_POWER_ON);
889 else
890 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
891 LVTMA_CONTROL_POWER_OFF);
892 }
893
894 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
895
896 DC_LOG_HW_RESUME_S3(
897 "%s: END: Panel Power action: %s bp_result=%u\n",
898 __func__, (power_up ? "On":"Off"),
899 bp_result);
900
901 if (!power_up)
902 /*save driver power off time stamp*/
903 link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
904 else
905 link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
906
907 DC_LOG_HW_RESUME_S3(
908 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
909 __func__,
910 link->link_trace.time_stamp.edp_poweroff,
911 link->link_trace.time_stamp.edp_poweron);
912
913 if (bp_result != BP_RESULT_OK)
914 DC_LOG_ERROR(
915 "%s: Panel Power bp_result: %d\n",
916 __func__, bp_result);
917 } else {
918 DC_LOG_HW_RESUME_S3(
919 "%s: Skipping Panel Power action: %s\n",
920 __func__, (power_up ? "On":"Off"));
921 }
922 }
923
924 /*todo: cloned in stream enc, fix*/
925 /*
926 * @brief
927 * eDP only. Control the backlight of the eDP panel
928 */
929 void dce110_edp_backlight_control(
930 struct dc_link *link,
931 bool enable)
932 {
933 struct dc_context *ctx = link->ctx;
934 struct bp_transmitter_control cntl = { 0 };
935
936 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
937 != CONNECTOR_ID_EDP) {
938 BREAK_TO_DEBUGGER();
939 return;
940 }
941
942 if (link->panel_cntl) {
943 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
944
945 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
946 DC_LOG_HW_RESUME_S3(
947 "%s: panel already powered up/off. Do nothing.\n",
948 __func__);
949 return;
950 }
951 }
952
953 /* Send VBIOS command to control eDP panel backlight */
954
955 DC_LOG_HW_RESUME_S3(
956 "%s: backlight action: %s\n",
957 __func__, (enable ? "On":"Off"));
958
959 cntl.action = enable ?
960 TRANSMITTER_CONTROL_BACKLIGHT_ON :
961 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
962
963 /*cntl.engine_id = ctx->engine;*/
964 cntl.transmitter = link->link_enc->transmitter;
965 cntl.connector_obj_id = link->link_enc->connector;
966 /*todo: unhardcode*/
967 cntl.lanes_number = LANE_COUNT_FOUR;
968 cntl.hpd_sel = link->link_enc->hpd_source;
969 cntl.signal = SIGNAL_TYPE_EDP;
970
971 /* For eDP, the following delays might need to be considered
972 * after link training completed:
973 * idle period - min. accounts for required BS-Idle pattern,
974 * max. allows for source frame synchronization);
975 * 50 msec max. delay from valid video data from source
976 * to video on dislpay or backlight enable.
977 *
978 * Disable the delay for now.
979 * Enable it in the future if necessary.
980 */
981 /* dc_service_sleep_in_milliseconds(50); */
982 /*edp 1.2*/
983 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
984 edp_receiver_ready_T7(link);
985
986 if (ctx->dc->ctx->dmub_srv &&
987 ctx->dc->debug.dmub_command_table) {
988 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
989 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
990 LVTMA_CONTROL_LCD_BLON);
991 else
992 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
993 LVTMA_CONTROL_LCD_BLOFF);
994 }
995
996 link_transmitter_control(ctx->dc_bios, &cntl);
997
998 if (enable && link->dpcd_sink_ext_caps.bits.oled)
999 msleep(OLED_POST_T7_DELAY);
1000
1001 if (link->dpcd_sink_ext_caps.bits.oled ||
1002 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1003 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1004 dc_link_backlight_enable_aux(link, enable);
1005
1006 /*edp 1.2*/
1007 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
1008 edp_add_delay_for_T9(link);
1009
1010 if (!enable && link->dpcd_sink_ext_caps.bits.oled)
1011 msleep(OLED_PRE_T11_DELAY);
1012 }
1013
1014 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1015 {
1016 /* notify audio driver for audio modes of monitor */
1017 struct dc *dc;
1018 struct clk_mgr *clk_mgr;
1019 unsigned int i, num_audio = 1;
1020
1021 if (!pipe_ctx->stream)
1022 return;
1023
1024 dc = pipe_ctx->stream->ctx->dc;
1025 clk_mgr = dc->clk_mgr;
1026
1027 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1028 return;
1029
1030 if (pipe_ctx->stream_res.audio) {
1031 for (i = 0; i < MAX_PIPES; i++) {
1032 /*current_state not updated yet*/
1033 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1034 num_audio++;
1035 }
1036
1037 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1038
1039 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1040 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1041 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1042 /* un-mute audio */
1043 /* TODO: audio should be per stream rather than per link */
1044 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1045 pipe_ctx->stream_res.stream_enc, false);
1046 if (pipe_ctx->stream_res.audio)
1047 pipe_ctx->stream_res.audio->enabled = true;
1048 }
1049 }
1050
1051 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1052 {
1053 struct dc *dc;
1054 struct clk_mgr *clk_mgr;
1055
1056 if (!pipe_ctx || !pipe_ctx->stream)
1057 return;
1058
1059 dc = pipe_ctx->stream->ctx->dc;
1060 clk_mgr = dc->clk_mgr;
1061
1062 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1063 return;
1064
1065 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1066 pipe_ctx->stream_res.stream_enc, true);
1067 if (pipe_ctx->stream_res.audio) {
1068 pipe_ctx->stream_res.audio->enabled = false;
1069
1070 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1071 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1072 pipe_ctx->stream_res.stream_enc);
1073 else
1074 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1075 pipe_ctx->stream_res.stream_enc);
1076
1077 if (clk_mgr->funcs->enable_pme_wa)
1078 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1079 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1080
1081 /* TODO: notify audio driver for if audio modes list changed
1082 * add audio mode list change flag */
1083 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1084 * stream->stream_engine_id);
1085 */
1086 }
1087 }
1088
1089 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1090 {
1091 struct dc_stream_state *stream = pipe_ctx->stream;
1092 struct dc_link *link = stream->link;
1093 struct dc *dc = pipe_ctx->stream->ctx->dc;
1094
1095 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1096 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1097 pipe_ctx->stream_res.stream_enc);
1098 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1099 pipe_ctx->stream_res.stream_enc);
1100 }
1101
1102 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1103 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1104 pipe_ctx->stream_res.stream_enc);
1105
1106 dc->hwss.disable_audio_stream(pipe_ctx);
1107
1108 link->link_enc->funcs->connect_dig_be_to_fe(
1109 link->link_enc,
1110 pipe_ctx->stream_res.stream_enc->id,
1111 false);
1112
1113 }
1114
1115 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1116 struct dc_link_settings *link_settings)
1117 {
1118 struct encoder_unblank_param params = { { 0 } };
1119 struct dc_stream_state *stream = pipe_ctx->stream;
1120 struct dc_link *link = stream->link;
1121 struct dce_hwseq *hws = link->dc->hwseq;
1122
1123 /* only 3 items below are used by unblank */
1124 params.timing = pipe_ctx->stream->timing;
1125 params.link_settings.link_rate = link_settings->link_rate;
1126
1127 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1128 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1129
1130 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1131 hws->funcs.edp_backlight_control(link, true);
1132 }
1133 }
1134
1135 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1136 {
1137 struct dc_stream_state *stream = pipe_ctx->stream;
1138 struct dc_link *link = stream->link;
1139 struct dce_hwseq *hws = link->dc->hwseq;
1140
1141 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1142 hws->funcs.edp_backlight_control(link, false);
1143 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1144 }
1145
1146 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1147 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1148
1149 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1150 /*
1151 * After output is idle pattern some sinks need time to recognize the stream
1152 * has changed or they enter protection state and hang.
1153 */
1154 msleep(60);
1155 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
1156 edp_receiver_ready_T9(link);
1157 }
1158
1159 }
1160
1161
1162 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1163 {
1164 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1165 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1166 }
1167
1168 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1169 {
1170 switch (crtc_id) {
1171 case CONTROLLER_ID_D0:
1172 return DTO_SOURCE_ID0;
1173 case CONTROLLER_ID_D1:
1174 return DTO_SOURCE_ID1;
1175 case CONTROLLER_ID_D2:
1176 return DTO_SOURCE_ID2;
1177 case CONTROLLER_ID_D3:
1178 return DTO_SOURCE_ID3;
1179 case CONTROLLER_ID_D4:
1180 return DTO_SOURCE_ID4;
1181 case CONTROLLER_ID_D5:
1182 return DTO_SOURCE_ID5;
1183 default:
1184 return DTO_SOURCE_UNKNOWN;
1185 }
1186 }
1187
1188 static void build_audio_output(
1189 struct dc_state *state,
1190 const struct pipe_ctx *pipe_ctx,
1191 struct audio_output *audio_output)
1192 {
1193 const struct dc_stream_state *stream = pipe_ctx->stream;
1194 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1195
1196 audio_output->signal = pipe_ctx->stream->signal;
1197
1198 /* audio_crtc_info */
1199
1200 audio_output->crtc_info.h_total =
1201 stream->timing.h_total;
1202
1203 /*
1204 * Audio packets are sent during actual CRTC blank physical signal, we
1205 * need to specify actual active signal portion
1206 */
1207 audio_output->crtc_info.h_active =
1208 stream->timing.h_addressable
1209 + stream->timing.h_border_left
1210 + stream->timing.h_border_right;
1211
1212 audio_output->crtc_info.v_active =
1213 stream->timing.v_addressable
1214 + stream->timing.v_border_top
1215 + stream->timing.v_border_bottom;
1216
1217 audio_output->crtc_info.pixel_repetition = 1;
1218
1219 audio_output->crtc_info.interlaced =
1220 stream->timing.flags.INTERLACE;
1221
1222 audio_output->crtc_info.refresh_rate =
1223 (stream->timing.pix_clk_100hz*100)/
1224 (stream->timing.h_total*stream->timing.v_total);
1225
1226 audio_output->crtc_info.color_depth =
1227 stream->timing.display_color_depth;
1228
1229 audio_output->crtc_info.requested_pixel_clock_100Hz =
1230 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1231
1232 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1233 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1234
1235 /*for HDMI, audio ACR is with deep color ratio factor*/
1236 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1237 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1238 (stream->timing.pix_clk_100hz)) {
1239 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1240 audio_output->crtc_info.requested_pixel_clock_100Hz =
1241 audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1242 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1243 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1244
1245 }
1246 }
1247
1248 if (state->clk_mgr &&
1249 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1250 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1251 audio_output->pll_info.dp_dto_source_clock_in_khz =
1252 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1253 state->clk_mgr);
1254 }
1255
1256 audio_output->pll_info.feed_back_divider =
1257 pipe_ctx->pll_settings.feedback_divider;
1258
1259 audio_output->pll_info.dto_source =
1260 translate_to_dto_source(
1261 pipe_ctx->stream_res.tg->inst + 1);
1262
1263 /* TODO hard code to enable for now. Need get from stream */
1264 audio_output->pll_info.ss_enabled = true;
1265
1266 audio_output->pll_info.ss_percentage =
1267 pipe_ctx->pll_settings.ss_percentage;
1268 }
1269
1270 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1271 struct tg_color *color)
1272 {
1273 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1274
1275 switch (pipe_ctx->plane_res.scl_data.format) {
1276 case PIXEL_FORMAT_ARGB8888:
1277 /* set boarder color to red */
1278 color->color_r_cr = color_value;
1279 break;
1280
1281 case PIXEL_FORMAT_ARGB2101010:
1282 /* set boarder color to blue */
1283 color->color_b_cb = color_value;
1284 break;
1285 case PIXEL_FORMAT_420BPP8:
1286 /* set boarder color to green */
1287 color->color_g_y = color_value;
1288 break;
1289 case PIXEL_FORMAT_420BPP10:
1290 /* set boarder color to yellow */
1291 color->color_g_y = color_value;
1292 color->color_r_cr = color_value;
1293 break;
1294 case PIXEL_FORMAT_FP16:
1295 /* set boarder color to white */
1296 color->color_r_cr = color_value;
1297 color->color_b_cb = color_value;
1298 color->color_g_y = color_value;
1299 break;
1300 default:
1301 break;
1302 }
1303 }
1304
1305 static void program_scaler(const struct dc *dc,
1306 const struct pipe_ctx *pipe_ctx)
1307 {
1308 struct tg_color color = {0};
1309
1310 #if defined(CONFIG_DRM_AMD_DC_DCN)
1311 /* TOFPGA */
1312 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1313 return;
1314 #endif
1315
1316 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1317 get_surface_visual_confirm_color(pipe_ctx, &color);
1318 else
1319 color_space_to_black_color(dc,
1320 pipe_ctx->stream->output_color_space,
1321 &color);
1322
1323 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1324 pipe_ctx->plane_res.xfm,
1325 pipe_ctx->plane_res.scl_data.lb_params.depth,
1326 &pipe_ctx->stream->bit_depth_params);
1327
1328 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1329 /*
1330 * The way 420 is packed, 2 channels carry Y component, 1 channel
1331 * alternate between Cb and Cr, so both channels need the pixel
1332 * value for Y
1333 */
1334 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1335 color.color_r_cr = color.color_g_y;
1336
1337 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1338 pipe_ctx->stream_res.tg,
1339 &color);
1340 }
1341
1342 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1343 &pipe_ctx->plane_res.scl_data);
1344 }
1345
1346 static enum dc_status dce110_enable_stream_timing(
1347 struct pipe_ctx *pipe_ctx,
1348 struct dc_state *context,
1349 struct dc *dc)
1350 {
1351 struct dc_stream_state *stream = pipe_ctx->stream;
1352 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1353 pipe_ctx[pipe_ctx->pipe_idx];
1354 struct tg_color black_color = {0};
1355
1356 if (!pipe_ctx_old->stream) {
1357
1358 /* program blank color */
1359 color_space_to_black_color(dc,
1360 stream->output_color_space, &black_color);
1361 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1362 pipe_ctx->stream_res.tg,
1363 &black_color);
1364
1365 /*
1366 * Must blank CRTC after disabling power gating and before any
1367 * programming, otherwise CRTC will be hung in bad state
1368 */
1369 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1370
1371 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1372 pipe_ctx->clock_source,
1373 &pipe_ctx->stream_res.pix_clk_params,
1374 &pipe_ctx->pll_settings)) {
1375 BREAK_TO_DEBUGGER();
1376 return DC_ERROR_UNEXPECTED;
1377 }
1378
1379 pipe_ctx->stream_res.tg->funcs->program_timing(
1380 pipe_ctx->stream_res.tg,
1381 &stream->timing,
1382 0,
1383 0,
1384 0,
1385 0,
1386 pipe_ctx->stream->signal,
1387 true);
1388 }
1389
1390 if (!pipe_ctx_old->stream) {
1391 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1392 pipe_ctx->stream_res.tg)) {
1393 BREAK_TO_DEBUGGER();
1394 return DC_ERROR_UNEXPECTED;
1395 }
1396 }
1397
1398 return DC_OK;
1399 }
1400
1401 static enum dc_status apply_single_controller_ctx_to_hw(
1402 struct pipe_ctx *pipe_ctx,
1403 struct dc_state *context,
1404 struct dc *dc)
1405 {
1406 struct dc_stream_state *stream = pipe_ctx->stream;
1407 struct drr_params params = {0};
1408 unsigned int event_triggers = 0;
1409 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1410 struct dce_hwseq *hws = dc->hwseq;
1411
1412 if (hws->funcs.disable_stream_gating) {
1413 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1414 }
1415
1416 if (pipe_ctx->stream_res.audio != NULL) {
1417 struct audio_output audio_output;
1418
1419 build_audio_output(context, pipe_ctx, &audio_output);
1420
1421 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1422 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1423 pipe_ctx->stream_res.stream_enc,
1424 pipe_ctx->stream_res.audio->inst,
1425 &pipe_ctx->stream->audio_info);
1426 else
1427 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1428 pipe_ctx->stream_res.stream_enc,
1429 pipe_ctx->stream_res.audio->inst,
1430 &pipe_ctx->stream->audio_info,
1431 &audio_output.crtc_info);
1432
1433 pipe_ctx->stream_res.audio->funcs->az_configure(
1434 pipe_ctx->stream_res.audio,
1435 pipe_ctx->stream->signal,
1436 &audio_output.crtc_info,
1437 &pipe_ctx->stream->audio_info);
1438 }
1439
1440 /* */
1441 /* Do not touch stream timing on seamless boot optimization. */
1442 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1443 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1444
1445 if (hws->funcs.setup_vupdate_interrupt)
1446 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1447
1448 params.vertical_total_min = stream->adjust.v_total_min;
1449 params.vertical_total_max = stream->adjust.v_total_max;
1450 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1451 pipe_ctx->stream_res.tg->funcs->set_drr(
1452 pipe_ctx->stream_res.tg, &params);
1453
1454 // DRR should set trigger event to monitor surface update event
1455 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1456 event_triggers = 0x80;
1457 /* Event triggers and num frames initialized for DRR, but can be
1458 * later updated for PSR use. Note DRR trigger events are generated
1459 * regardless of whether num frames met.
1460 */
1461 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1462 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1463 pipe_ctx->stream_res.tg, event_triggers, 2);
1464
1465 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1466 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1467 pipe_ctx->stream_res.stream_enc,
1468 pipe_ctx->stream_res.tg->inst);
1469
1470 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1471 pipe_ctx->stream_res.opp,
1472 COLOR_SPACE_YCBCR601,
1473 stream->timing.display_color_depth,
1474 stream->signal);
1475
1476 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1477 pipe_ctx->stream_res.opp,
1478 &stream->bit_depth_params,
1479 &stream->clamping);
1480 while (odm_pipe) {
1481 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1482 odm_pipe->stream_res.opp,
1483 COLOR_SPACE_YCBCR601,
1484 stream->timing.display_color_depth,
1485 stream->signal);
1486
1487 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1488 odm_pipe->stream_res.opp,
1489 &stream->bit_depth_params,
1490 &stream->clamping);
1491 odm_pipe = odm_pipe->next_odm_pipe;
1492 }
1493
1494 if (!stream->dpms_off)
1495 core_link_enable_stream(context, pipe_ctx);
1496
1497 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1498
1499 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1500
1501 return DC_OK;
1502 }
1503
1504 /******************************************************************************/
1505
1506 static void power_down_encoders(struct dc *dc)
1507 {
1508 int i;
1509
1510 /* do not know BIOS back-front mapping, simply blank all. It will not
1511 * hurt for non-DP
1512 */
1513 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1514 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1515 dc->res_pool->stream_enc[i]);
1516 }
1517
1518 for (i = 0; i < dc->link_count; i++) {
1519 enum signal_type signal = dc->links[i]->connector_signal;
1520
1521 if ((signal == SIGNAL_TYPE_EDP) ||
1522 (signal == SIGNAL_TYPE_DISPLAY_PORT))
1523 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1524 dp_receiver_power_ctrl(dc->links[i], false);
1525
1526 if (signal != SIGNAL_TYPE_EDP)
1527 signal = SIGNAL_TYPE_NONE;
1528
1529 dc->links[i]->link_enc->funcs->disable_output(
1530 dc->links[i]->link_enc, signal);
1531
1532 dc->links[i]->link_status.link_active = false;
1533 memset(&dc->links[i]->cur_link_settings, 0,
1534 sizeof(dc->links[i]->cur_link_settings));
1535 }
1536 }
1537
1538 static void power_down_controllers(struct dc *dc)
1539 {
1540 int i;
1541
1542 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1543 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1544 dc->res_pool->timing_generators[i]);
1545 }
1546 }
1547
1548 static void power_down_clock_sources(struct dc *dc)
1549 {
1550 int i;
1551
1552 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1553 dc->res_pool->dp_clock_source) == false)
1554 dm_error("Failed to power down pll! (dp clk src)\n");
1555
1556 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1557 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1558 dc->res_pool->clock_sources[i]) == false)
1559 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1560 }
1561 }
1562
1563 static void power_down_all_hw_blocks(struct dc *dc)
1564 {
1565 power_down_encoders(dc);
1566
1567 power_down_controllers(dc);
1568
1569 power_down_clock_sources(dc);
1570
1571 if (dc->fbc_compressor)
1572 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1573 }
1574
1575 static void disable_vga_and_power_gate_all_controllers(
1576 struct dc *dc)
1577 {
1578 int i;
1579 struct timing_generator *tg;
1580 struct dc_context *ctx = dc->ctx;
1581
1582 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1583 tg = dc->res_pool->timing_generators[i];
1584
1585 if (tg->funcs->disable_vga)
1586 tg->funcs->disable_vga(tg);
1587 }
1588 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1589 /* Enable CLOCK gating for each pipe BEFORE controller
1590 * powergating. */
1591 enable_display_pipe_clock_gating(ctx,
1592 true);
1593
1594 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1595 dc->hwss.disable_plane(dc,
1596 &dc->current_state->res_ctx.pipe_ctx[i]);
1597 }
1598 }
1599
1600
1601 static struct dc_stream_state *get_edp_stream(struct dc_state *context)
1602 {
1603 int i;
1604
1605 for (i = 0; i < context->stream_count; i++) {
1606 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1607 return context->streams[i];
1608 }
1609 return NULL;
1610 }
1611
1612 static struct dc_link *get_edp_link_with_sink(
1613 struct dc *dc,
1614 struct dc_state *context)
1615 {
1616 int i;
1617 struct dc_link *link = NULL;
1618
1619 /* check if there is an eDP panel not in use */
1620 for (i = 0; i < dc->link_count; i++) {
1621 if (dc->links[i]->local_sink &&
1622 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1623 link = dc->links[i];
1624 break;
1625 }
1626 }
1627
1628 return link;
1629 }
1630
1631 /**
1632 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1633 * 1. Power down all DC HW blocks
1634 * 2. Disable VGA engine on all controllers
1635 * 3. Enable power gating for controller
1636 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1637 */
1638 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1639 {
1640 int i;
1641 struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context);
1642 struct dc_link *edp_link = get_edp_link(dc);
1643 struct dc_stream_state *edp_stream = NULL;
1644 bool can_apply_edp_fast_boot = false;
1645 bool can_apply_seamless_boot = false;
1646 bool keep_edp_vdd_on = false;
1647 struct dce_hwseq *hws = dc->hwseq;
1648
1649 if (hws->funcs.init_pipes)
1650 hws->funcs.init_pipes(dc, context);
1651
1652 edp_stream = get_edp_stream(context);
1653
1654 // Check fastboot support, disable on DCE8 because of blank screens
1655 if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1656 dc->ctx->dce_version != DCE_VERSION_8_1 &&
1657 dc->ctx->dce_version != DCE_VERSION_8_3) {
1658
1659 // enable fastboot if backend is enabled on eDP
1660 if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
1661 /* Set optimization flag on eDP stream*/
1662 if (edp_stream && edp_link->link_status.link_active) {
1663 edp_stream->apply_edp_fast_boot_optimization = true;
1664 can_apply_edp_fast_boot = true;
1665 }
1666 }
1667
1668 // We are trying to enable eDP, don't power down VDD
1669 if (edp_stream)
1670 keep_edp_vdd_on = true;
1671 }
1672
1673 // Check seamless boot support
1674 for (i = 0; i < context->stream_count; i++) {
1675 if (context->streams[i]->apply_seamless_boot_optimization) {
1676 can_apply_seamless_boot = true;
1677 break;
1678 }
1679 }
1680
1681 /* eDP should not have stream in resume from S4 and so even with VBios post
1682 * it should get turned off
1683 */
1684 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1685 if (edp_link_with_sink && !keep_edp_vdd_on) {
1686 /*turn off backlight before DP_blank and encoder powered down*/
1687 hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1688 }
1689 /*resume from S3, no vbios posting, no need to power down again*/
1690 power_down_all_hw_blocks(dc);
1691 disable_vga_and_power_gate_all_controllers(dc);
1692 if (edp_link_with_sink && !keep_edp_vdd_on)
1693 dc->hwss.edp_power_control(edp_link_with_sink, false);
1694 }
1695 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1696 }
1697
1698 static uint32_t compute_pstate_blackout_duration(
1699 struct bw_fixed blackout_duration,
1700 const struct dc_stream_state *stream)
1701 {
1702 uint32_t total_dest_line_time_ns;
1703 uint32_t pstate_blackout_duration_ns;
1704
1705 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1706
1707 total_dest_line_time_ns = 1000000UL *
1708 (stream->timing.h_total * 10) /
1709 stream->timing.pix_clk_100hz +
1710 pstate_blackout_duration_ns;
1711
1712 return total_dest_line_time_ns;
1713 }
1714
1715 static void dce110_set_displaymarks(
1716 const struct dc *dc,
1717 struct dc_state *context)
1718 {
1719 uint8_t i, num_pipes;
1720 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1721
1722 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1723 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1724 uint32_t total_dest_line_time_ns;
1725
1726 if (pipe_ctx->stream == NULL)
1727 continue;
1728
1729 total_dest_line_time_ns = compute_pstate_blackout_duration(
1730 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1731 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1732 pipe_ctx->plane_res.mi,
1733 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1734 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1735 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1736 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1737 total_dest_line_time_ns);
1738 if (i == underlay_idx) {
1739 num_pipes++;
1740 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1741 pipe_ctx->plane_res.mi,
1742 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1743 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1744 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1745 total_dest_line_time_ns);
1746 }
1747 num_pipes++;
1748 }
1749 }
1750
1751 void dce110_set_safe_displaymarks(
1752 struct resource_context *res_ctx,
1753 const struct resource_pool *pool)
1754 {
1755 int i;
1756 int underlay_idx = pool->underlay_pipe_index;
1757 struct dce_watermarks max_marks = {
1758 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1759 struct dce_watermarks nbp_marks = {
1760 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1761 struct dce_watermarks min_marks = { 0, 0, 0, 0};
1762
1763 for (i = 0; i < MAX_PIPES; i++) {
1764 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1765 continue;
1766
1767 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1768 res_ctx->pipe_ctx[i].plane_res.mi,
1769 nbp_marks,
1770 max_marks,
1771 min_marks,
1772 max_marks,
1773 MAX_WATERMARK);
1774
1775 if (i == underlay_idx)
1776 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1777 res_ctx->pipe_ctx[i].plane_res.mi,
1778 nbp_marks,
1779 max_marks,
1780 max_marks,
1781 MAX_WATERMARK);
1782
1783 }
1784 }
1785
1786 /*******************************************************************************
1787 * Public functions
1788 ******************************************************************************/
1789
1790 static void set_drr(struct pipe_ctx **pipe_ctx,
1791 int num_pipes, unsigned int vmin, unsigned int vmax,
1792 unsigned int vmid, unsigned int vmid_frame_number)
1793 {
1794 int i = 0;
1795 struct drr_params params = {0};
1796 // DRR should set trigger event to monitor surface update event
1797 unsigned int event_triggers = 0x80;
1798 // Note DRR trigger events are generated regardless of whether num frames met.
1799 unsigned int num_frames = 2;
1800
1801 params.vertical_total_max = vmax;
1802 params.vertical_total_min = vmin;
1803
1804 /* TODO: If multiple pipes are to be supported, you need
1805 * some GSL stuff. Static screen triggers may be programmed differently
1806 * as well.
1807 */
1808 for (i = 0; i < num_pipes; i++) {
1809 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1810 pipe_ctx[i]->stream_res.tg, &params);
1811
1812 if (vmax != 0 && vmin != 0)
1813 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1814 pipe_ctx[i]->stream_res.tg,
1815 event_triggers, num_frames);
1816 }
1817 }
1818
1819 static void get_position(struct pipe_ctx **pipe_ctx,
1820 int num_pipes,
1821 struct crtc_position *position)
1822 {
1823 int i = 0;
1824
1825 /* TODO: handle pipes > 1
1826 */
1827 for (i = 0; i < num_pipes; i++)
1828 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1829 }
1830
1831 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1832 int num_pipes, const struct dc_static_screen_params *params)
1833 {
1834 unsigned int i;
1835 unsigned int triggers = 0;
1836
1837 if (params->triggers.overlay_update)
1838 triggers |= 0x100;
1839 if (params->triggers.surface_update)
1840 triggers |= 0x80;
1841 if (params->triggers.cursor_update)
1842 triggers |= 0x2;
1843 if (params->triggers.force_trigger)
1844 triggers |= 0x1;
1845
1846 if (num_pipes) {
1847 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1848
1849 if (dc->fbc_compressor)
1850 triggers |= 0x84;
1851 }
1852
1853 for (i = 0; i < num_pipes; i++)
1854 pipe_ctx[i]->stream_res.tg->funcs->
1855 set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1856 triggers, params->num_frames);
1857 }
1858
1859 /*
1860 * Check if FBC can be enabled
1861 */
1862 static bool should_enable_fbc(struct dc *dc,
1863 struct dc_state *context,
1864 uint32_t *pipe_idx)
1865 {
1866 uint32_t i;
1867 struct pipe_ctx *pipe_ctx = NULL;
1868 struct resource_context *res_ctx = &context->res_ctx;
1869 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1870
1871
1872 ASSERT(dc->fbc_compressor);
1873
1874 /* FBC memory should be allocated */
1875 if (!dc->ctx->fbc_gpu_addr)
1876 return false;
1877
1878 /* Only supports single display */
1879 if (context->stream_count != 1)
1880 return false;
1881
1882 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1883 if (res_ctx->pipe_ctx[i].stream) {
1884
1885 pipe_ctx = &res_ctx->pipe_ctx[i];
1886
1887 if (!pipe_ctx)
1888 continue;
1889
1890 /* fbc not applicable on underlay pipe */
1891 if (pipe_ctx->pipe_idx != underlay_idx) {
1892 *pipe_idx = i;
1893 break;
1894 }
1895 }
1896 }
1897
1898 if (i == dc->res_pool->pipe_count)
1899 return false;
1900
1901 if (!pipe_ctx->stream->link)
1902 return false;
1903
1904 /* Only supports eDP */
1905 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
1906 return false;
1907
1908 /* PSR should not be enabled */
1909 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
1910 return false;
1911
1912 /* Nothing to compress */
1913 if (!pipe_ctx->plane_state)
1914 return false;
1915
1916 /* Only for non-linear tiling */
1917 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1918 return false;
1919
1920 return true;
1921 }
1922
1923 /*
1924 * Enable FBC
1925 */
1926 static void enable_fbc(
1927 struct dc *dc,
1928 struct dc_state *context)
1929 {
1930 uint32_t pipe_idx = 0;
1931
1932 if (should_enable_fbc(dc, context, &pipe_idx)) {
1933 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1934 struct compr_addr_and_pitch_params params = {0, 0, 0};
1935 struct compressor *compr = dc->fbc_compressor;
1936 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1937
1938 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1939 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1940 params.inst = pipe_ctx->stream_res.tg->inst;
1941 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1942
1943 compr->funcs->surface_address_and_pitch(compr, &params);
1944 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1945
1946 compr->funcs->enable_fbc(compr, &params);
1947 }
1948 }
1949
1950 static void dce110_reset_hw_ctx_wrap(
1951 struct dc *dc,
1952 struct dc_state *context)
1953 {
1954 int i;
1955
1956 /* Reset old context */
1957 /* look up the targets that have been removed since last commit */
1958 for (i = 0; i < MAX_PIPES; i++) {
1959 struct pipe_ctx *pipe_ctx_old =
1960 &dc->current_state->res_ctx.pipe_ctx[i];
1961 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1962
1963 /* Note: We need to disable output if clock sources change,
1964 * since bios does optimization and doesn't apply if changing
1965 * PHY when not already disabled.
1966 */
1967
1968 /* Skip underlay pipe since it will be handled in commit surface*/
1969 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1970 continue;
1971
1972 if (!pipe_ctx->stream ||
1973 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1974 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1975
1976 /* Disable if new stream is null. O/w, if stream is
1977 * disabled already, no need to disable again.
1978 */
1979 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
1980 core_link_disable_stream(pipe_ctx_old);
1981
1982 /* free acquired resources*/
1983 if (pipe_ctx_old->stream_res.audio) {
1984 /*disable az_endpoint*/
1985 pipe_ctx_old->stream_res.audio->funcs->
1986 az_disable(pipe_ctx_old->stream_res.audio);
1987
1988 /*free audio*/
1989 if (dc->caps.dynamic_audio == true) {
1990 /*we have to dynamic arbitrate the audio endpoints*/
1991 /*we free the resource, need reset is_audio_acquired*/
1992 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
1993 pipe_ctx_old->stream_res.audio, false);
1994 pipe_ctx_old->stream_res.audio = NULL;
1995 }
1996 }
1997 }
1998
1999 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2000 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2001 dm_error("DC: failed to blank crtc!\n");
2002 BREAK_TO_DEBUGGER();
2003 }
2004 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2005 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2006 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2007
2008 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2009 dc->res_pool,
2010 old_clk))
2011 old_clk->funcs->cs_power_down(old_clk);
2012
2013 dc->hwss.disable_plane(dc, pipe_ctx_old);
2014
2015 pipe_ctx_old->stream = NULL;
2016 }
2017 }
2018 }
2019
2020 static void dce110_setup_audio_dto(
2021 struct dc *dc,
2022 struct dc_state *context)
2023 {
2024 int i;
2025
2026 /* program audio wall clock. use HDMI as clock source if HDMI
2027 * audio active. Otherwise, use DP as clock source
2028 * first, loop to find any HDMI audio, if not, loop find DP audio
2029 */
2030 /* Setup audio rate clock source */
2031 /* Issue:
2032 * Audio lag happened on DP monitor when unplug a HDMI monitor
2033 *
2034 * Cause:
2035 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2036 * is set to either dto0 or dto1, audio should work fine.
2037 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2038 * set to dto0 will cause audio lag.
2039 *
2040 * Solution:
2041 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2042 * find first available pipe with audio, setup audio wall DTO per topology
2043 * instead of per pipe.
2044 */
2045 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2046 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2047
2048 if (pipe_ctx->stream == NULL)
2049 continue;
2050
2051 if (pipe_ctx->top_pipe)
2052 continue;
2053 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2054 continue;
2055 if (pipe_ctx->stream_res.audio != NULL) {
2056 struct audio_output audio_output;
2057
2058 build_audio_output(context, pipe_ctx, &audio_output);
2059
2060 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2061 pipe_ctx->stream_res.audio,
2062 pipe_ctx->stream->signal,
2063 &audio_output.crtc_info,
2064 &audio_output.pll_info);
2065 break;
2066 }
2067 }
2068
2069 /* no HDMI audio is found, try DP audio */
2070 if (i == dc->res_pool->pipe_count) {
2071 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2072 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2073
2074 if (pipe_ctx->stream == NULL)
2075 continue;
2076
2077 if (pipe_ctx->top_pipe)
2078 continue;
2079
2080 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2081 continue;
2082
2083 if (pipe_ctx->stream_res.audio != NULL) {
2084 struct audio_output audio_output;
2085
2086 build_audio_output(context, pipe_ctx, &audio_output);
2087
2088 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2089 pipe_ctx->stream_res.audio,
2090 pipe_ctx->stream->signal,
2091 &audio_output.crtc_info,
2092 &audio_output.pll_info);
2093 break;
2094 }
2095 }
2096 }
2097 }
2098
2099 enum dc_status dce110_apply_ctx_to_hw(
2100 struct dc *dc,
2101 struct dc_state *context)
2102 {
2103 struct dce_hwseq *hws = dc->hwseq;
2104 struct dc_bios *dcb = dc->ctx->dc_bios;
2105 enum dc_status status;
2106 int i;
2107
2108 /* Reset old context */
2109 /* look up the targets that have been removed since last commit */
2110 hws->funcs.reset_hw_ctx_wrap(dc, context);
2111
2112 /* Skip applying if no targets */
2113 if (context->stream_count <= 0)
2114 return DC_OK;
2115
2116 /* Apply new context */
2117 dcb->funcs->set_scratch_critical_state(dcb, true);
2118
2119 /* below is for real asic only */
2120 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2121 struct pipe_ctx *pipe_ctx_old =
2122 &dc->current_state->res_ctx.pipe_ctx[i];
2123 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2124
2125 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2126 continue;
2127
2128 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2129 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2130 dce_crtc_switch_to_clk_src(dc->hwseq,
2131 pipe_ctx->clock_source, i);
2132 continue;
2133 }
2134
2135 hws->funcs.enable_display_power_gating(
2136 dc, i, dc->ctx->dc_bios,
2137 PIPE_GATING_CONTROL_DISABLE);
2138 }
2139
2140 if (dc->fbc_compressor)
2141 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2142
2143 dce110_setup_audio_dto(dc, context);
2144
2145 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2146 struct pipe_ctx *pipe_ctx_old =
2147 &dc->current_state->res_ctx.pipe_ctx[i];
2148 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2149
2150 if (pipe_ctx->stream == NULL)
2151 continue;
2152
2153 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2154 pipe_ctx->stream->link->link_state_valid) {
2155 continue;
2156 }
2157
2158 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2159 continue;
2160
2161 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2162 continue;
2163
2164 status = apply_single_controller_ctx_to_hw(
2165 pipe_ctx,
2166 context,
2167 dc);
2168
2169 if (DC_OK != status)
2170 return status;
2171 }
2172
2173 if (dc->fbc_compressor)
2174 enable_fbc(dc, dc->current_state);
2175
2176 dcb->funcs->set_scratch_critical_state(dcb, false);
2177
2178 return DC_OK;
2179 }
2180
2181 /*******************************************************************************
2182 * Front End programming
2183 ******************************************************************************/
2184 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2185 {
2186 struct default_adjustment default_adjust = { 0 };
2187
2188 default_adjust.force_hw_default = false;
2189 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2190 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2191 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2192 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2193
2194 /* display color depth */
2195 default_adjust.color_depth =
2196 pipe_ctx->stream->timing.display_color_depth;
2197
2198 /* Lb color depth */
2199 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2200
2201 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2202 pipe_ctx->plane_res.xfm, &default_adjust);
2203 }
2204
2205
2206 /*******************************************************************************
2207 * In order to turn on/off specific surface we will program
2208 * Blender + CRTC
2209 *
2210 * In case that we have two surfaces and they have a different visibility
2211 * we can't turn off the CRTC since it will turn off the entire display
2212 *
2213 * |----------------------------------------------- |
2214 * |bottom pipe|curr pipe | | |
2215 * |Surface |Surface | Blender | CRCT |
2216 * |visibility |visibility | Configuration| |
2217 * |------------------------------------------------|
2218 * | off | off | CURRENT_PIPE | blank |
2219 * | off | on | CURRENT_PIPE | unblank |
2220 * | on | off | OTHER_PIPE | unblank |
2221 * | on | on | BLENDING | unblank |
2222 * -------------------------------------------------|
2223 *
2224 ******************************************************************************/
2225 static void program_surface_visibility(const struct dc *dc,
2226 struct pipe_ctx *pipe_ctx)
2227 {
2228 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2229 bool blank_target = false;
2230
2231 if (pipe_ctx->bottom_pipe) {
2232
2233 /* For now we are supporting only two pipes */
2234 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2235
2236 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2237 if (pipe_ctx->plane_state->visible)
2238 blender_mode = BLND_MODE_BLENDING;
2239 else
2240 blender_mode = BLND_MODE_OTHER_PIPE;
2241
2242 } else if (!pipe_ctx->plane_state->visible)
2243 blank_target = true;
2244
2245 } else if (!pipe_ctx->plane_state->visible)
2246 blank_target = true;
2247
2248 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2249 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2250
2251 }
2252
2253 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2254 {
2255 int i = 0;
2256 struct xfm_grph_csc_adjustment adjust;
2257 memset(&adjust, 0, sizeof(adjust));
2258 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2259
2260
2261 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2262 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2263
2264 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2265 adjust.temperature_matrix[i] =
2266 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2267 }
2268
2269 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2270 }
2271 static void update_plane_addr(const struct dc *dc,
2272 struct pipe_ctx *pipe_ctx)
2273 {
2274 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2275
2276 if (plane_state == NULL)
2277 return;
2278
2279 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2280 pipe_ctx->plane_res.mi,
2281 &plane_state->address,
2282 plane_state->flip_immediate);
2283
2284 plane_state->status.requested_address = plane_state->address;
2285 }
2286
2287 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2288 {
2289 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2290
2291 if (plane_state == NULL)
2292 return;
2293
2294 plane_state->status.is_flip_pending =
2295 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2296 pipe_ctx->plane_res.mi);
2297
2298 if (plane_state->status.is_flip_pending && !plane_state->visible)
2299 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2300
2301 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2302 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2303 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2304 plane_state->status.is_right_eye =\
2305 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2306 }
2307 }
2308
2309 void dce110_power_down(struct dc *dc)
2310 {
2311 power_down_all_hw_blocks(dc);
2312 disable_vga_and_power_gate_all_controllers(dc);
2313 }
2314
2315 static bool wait_for_reset_trigger_to_occur(
2316 struct dc_context *dc_ctx,
2317 struct timing_generator *tg)
2318 {
2319 bool rc = false;
2320
2321 /* To avoid endless loop we wait at most
2322 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2323 const uint32_t frames_to_wait_on_triggered_reset = 10;
2324 uint32_t i;
2325
2326 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2327
2328 if (!tg->funcs->is_counter_moving(tg)) {
2329 DC_ERROR("TG counter is not moving!\n");
2330 break;
2331 }
2332
2333 if (tg->funcs->did_triggered_reset_occur(tg)) {
2334 rc = true;
2335 /* usually occurs at i=1 */
2336 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2337 i);
2338 break;
2339 }
2340
2341 /* Wait for one frame. */
2342 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2343 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2344 }
2345
2346 if (false == rc)
2347 DC_ERROR("GSL: Timeout on reset trigger!\n");
2348
2349 return rc;
2350 }
2351
2352 /* Enable timing synchronization for a group of Timing Generators. */
2353 static void dce110_enable_timing_synchronization(
2354 struct dc *dc,
2355 int group_index,
2356 int group_size,
2357 struct pipe_ctx *grouped_pipes[])
2358 {
2359 struct dc_context *dc_ctx = dc->ctx;
2360 struct dcp_gsl_params gsl_params = { 0 };
2361 int i;
2362
2363 DC_SYNC_INFO("GSL: Setting-up...\n");
2364
2365 /* Designate a single TG in the group as a master.
2366 * Since HW doesn't care which one, we always assign
2367 * the 1st one in the group. */
2368 gsl_params.gsl_group = 0;
2369 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2370
2371 for (i = 0; i < group_size; i++)
2372 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2373 grouped_pipes[i]->stream_res.tg, &gsl_params);
2374
2375 /* Reset slave controllers on master VSync */
2376 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2377
2378 for (i = 1 /* skip the master */; i < group_size; i++)
2379 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2380 grouped_pipes[i]->stream_res.tg,
2381 gsl_params.gsl_group);
2382
2383 for (i = 1 /* skip the master */; i < group_size; i++) {
2384 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2385 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2386 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2387 grouped_pipes[i]->stream_res.tg);
2388 }
2389
2390 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2391 * is that the sync'ed displays will not drift out of sync over time*/
2392 DC_SYNC_INFO("GSL: Restoring register states.\n");
2393 for (i = 0; i < group_size; i++)
2394 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2395
2396 DC_SYNC_INFO("GSL: Set-up complete.\n");
2397 }
2398
2399 static void dce110_enable_per_frame_crtc_position_reset(
2400 struct dc *dc,
2401 int group_size,
2402 struct pipe_ctx *grouped_pipes[])
2403 {
2404 struct dc_context *dc_ctx = dc->ctx;
2405 struct dcp_gsl_params gsl_params = { 0 };
2406 int i;
2407
2408 gsl_params.gsl_group = 0;
2409 gsl_params.gsl_master = 0;
2410
2411 for (i = 0; i < group_size; i++)
2412 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2413 grouped_pipes[i]->stream_res.tg, &gsl_params);
2414
2415 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2416
2417 for (i = 1; i < group_size; i++)
2418 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2419 grouped_pipes[i]->stream_res.tg,
2420 gsl_params.gsl_master,
2421 &grouped_pipes[i]->stream->triggered_crtc_reset);
2422
2423 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2424 for (i = 1; i < group_size; i++)
2425 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2426
2427 for (i = 0; i < group_size; i++)
2428 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2429
2430 }
2431
2432 static void init_pipes(struct dc *dc, struct dc_state *context)
2433 {
2434 // Do nothing
2435 }
2436
2437 static void init_hw(struct dc *dc)
2438 {
2439 int i;
2440 struct dc_bios *bp;
2441 struct transform *xfm;
2442 struct abm *abm;
2443 struct dmcu *dmcu;
2444 struct dce_hwseq *hws = dc->hwseq;
2445 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2446
2447 bp = dc->ctx->dc_bios;
2448 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2449 xfm = dc->res_pool->transforms[i];
2450 xfm->funcs->transform_reset(xfm);
2451
2452 hws->funcs.enable_display_power_gating(
2453 dc, i, bp,
2454 PIPE_GATING_CONTROL_INIT);
2455 hws->funcs.enable_display_power_gating(
2456 dc, i, bp,
2457 PIPE_GATING_CONTROL_DISABLE);
2458 hws->funcs.enable_display_pipe_clock_gating(
2459 dc->ctx,
2460 true);
2461 }
2462
2463 dce_clock_gating_power_up(dc->hwseq, false);
2464 /***************************************/
2465
2466 for (i = 0; i < dc->link_count; i++) {
2467 /****************************************/
2468 /* Power up AND update implementation according to the
2469 * required signal (which may be different from the
2470 * default signal on connector). */
2471 struct dc_link *link = dc->links[i];
2472
2473 link->link_enc->funcs->hw_init(link->link_enc);
2474 }
2475
2476 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2477 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2478
2479 tg->funcs->disable_vga(tg);
2480
2481 /* Blank controller using driver code instead of
2482 * command table. */
2483 tg->funcs->set_blank(tg, true);
2484 hwss_wait_for_blank_complete(tg);
2485 }
2486
2487 for (i = 0; i < dc->res_pool->audio_count; i++) {
2488 struct audio *audio = dc->res_pool->audios[i];
2489 audio->funcs->hw_init(audio);
2490 }
2491
2492 for (i = 0; i < dc->link_count; i++) {
2493 struct dc_link *link = dc->links[i];
2494
2495 if (link->panel_cntl)
2496 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2497 }
2498
2499 abm = dc->res_pool->abm;
2500 if (abm != NULL)
2501 abm->funcs->abm_init(abm, backlight);
2502
2503 dmcu = dc->res_pool->dmcu;
2504 if (dmcu != NULL && abm != NULL)
2505 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2506
2507 if (dc->fbc_compressor)
2508 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2509
2510 }
2511
2512
2513 void dce110_prepare_bandwidth(
2514 struct dc *dc,
2515 struct dc_state *context)
2516 {
2517 struct clk_mgr *dccg = dc->clk_mgr;
2518
2519 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2520
2521 dccg->funcs->update_clocks(
2522 dccg,
2523 context,
2524 false);
2525 }
2526
2527 void dce110_optimize_bandwidth(
2528 struct dc *dc,
2529 struct dc_state *context)
2530 {
2531 struct clk_mgr *dccg = dc->clk_mgr;
2532
2533 dce110_set_displaymarks(dc, context);
2534
2535 dccg->funcs->update_clocks(
2536 dccg,
2537 context,
2538 true);
2539 }
2540
2541 static void dce110_program_front_end_for_pipe(
2542 struct dc *dc, struct pipe_ctx *pipe_ctx)
2543 {
2544 struct mem_input *mi = pipe_ctx->plane_res.mi;
2545 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2546 struct xfm_grph_csc_adjustment adjust;
2547 struct out_csc_color_matrix tbl_entry;
2548 unsigned int i;
2549 struct dce_hwseq *hws = dc->hwseq;
2550
2551 DC_LOGGER_INIT();
2552 memset(&tbl_entry, 0, sizeof(tbl_entry));
2553
2554 memset(&adjust, 0, sizeof(adjust));
2555 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2556
2557 dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2558
2559 set_default_colors(pipe_ctx);
2560 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2561 == true) {
2562 tbl_entry.color_space =
2563 pipe_ctx->stream->output_color_space;
2564
2565 for (i = 0; i < 12; i++)
2566 tbl_entry.regval[i] =
2567 pipe_ctx->stream->csc_color_matrix.matrix[i];
2568
2569 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2570 (pipe_ctx->plane_res.xfm, &tbl_entry);
2571 }
2572
2573 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2574 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2575
2576 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2577 adjust.temperature_matrix[i] =
2578 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2579 }
2580
2581 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2582
2583 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2584
2585 program_scaler(dc, pipe_ctx);
2586
2587 mi->funcs->mem_input_program_surface_config(
2588 mi,
2589 plane_state->format,
2590 &plane_state->tiling_info,
2591 &plane_state->plane_size,
2592 plane_state->rotation,
2593 NULL,
2594 false);
2595 if (mi->funcs->set_blank)
2596 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2597
2598 if (dc->config.gpu_vm_support)
2599 mi->funcs->mem_input_program_pte_vm(
2600 pipe_ctx->plane_res.mi,
2601 plane_state->format,
2602 &plane_state->tiling_info,
2603 plane_state->rotation);
2604
2605 /* Moved programming gamma from dc to hwss */
2606 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2607 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2608 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2609 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2610
2611 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2612 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2613
2614 DC_LOG_SURFACE(
2615 "Pipe:%d %p: addr hi:0x%x, "
2616 "addr low:0x%x, "
2617 "src: %d, %d, %d,"
2618 " %d; dst: %d, %d, %d, %d;"
2619 "clip: %d, %d, %d, %d\n",
2620 pipe_ctx->pipe_idx,
2621 (void *) pipe_ctx->plane_state,
2622 pipe_ctx->plane_state->address.grph.addr.high_part,
2623 pipe_ctx->plane_state->address.grph.addr.low_part,
2624 pipe_ctx->plane_state->src_rect.x,
2625 pipe_ctx->plane_state->src_rect.y,
2626 pipe_ctx->plane_state->src_rect.width,
2627 pipe_ctx->plane_state->src_rect.height,
2628 pipe_ctx->plane_state->dst_rect.x,
2629 pipe_ctx->plane_state->dst_rect.y,
2630 pipe_ctx->plane_state->dst_rect.width,
2631 pipe_ctx->plane_state->dst_rect.height,
2632 pipe_ctx->plane_state->clip_rect.x,
2633 pipe_ctx->plane_state->clip_rect.y,
2634 pipe_ctx->plane_state->clip_rect.width,
2635 pipe_ctx->plane_state->clip_rect.height);
2636
2637 DC_LOG_SURFACE(
2638 "Pipe %d: width, height, x, y\n"
2639 "viewport:%d, %d, %d, %d\n"
2640 "recout: %d, %d, %d, %d\n",
2641 pipe_ctx->pipe_idx,
2642 pipe_ctx->plane_res.scl_data.viewport.width,
2643 pipe_ctx->plane_res.scl_data.viewport.height,
2644 pipe_ctx->plane_res.scl_data.viewport.x,
2645 pipe_ctx->plane_res.scl_data.viewport.y,
2646 pipe_ctx->plane_res.scl_data.recout.width,
2647 pipe_ctx->plane_res.scl_data.recout.height,
2648 pipe_ctx->plane_res.scl_data.recout.x,
2649 pipe_ctx->plane_res.scl_data.recout.y);
2650 }
2651
2652 static void dce110_apply_ctx_for_surface(
2653 struct dc *dc,
2654 const struct dc_stream_state *stream,
2655 int num_planes,
2656 struct dc_state *context)
2657 {
2658 int i;
2659
2660 if (num_planes == 0)
2661 return;
2662
2663 if (dc->fbc_compressor)
2664 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2665
2666 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2667 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2668
2669 if (pipe_ctx->stream != stream)
2670 continue;
2671
2672 /* Need to allocate mem before program front end for Fiji */
2673 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2674 pipe_ctx->plane_res.mi,
2675 pipe_ctx->stream->timing.h_total,
2676 pipe_ctx->stream->timing.v_total,
2677 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2678 context->stream_count);
2679
2680 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2681
2682 dc->hwss.update_plane_addr(dc, pipe_ctx);
2683
2684 program_surface_visibility(dc, pipe_ctx);
2685
2686 }
2687
2688 if (dc->fbc_compressor)
2689 enable_fbc(dc, context);
2690 }
2691
2692 static void dce110_post_unlock_program_front_end(
2693 struct dc *dc,
2694 struct dc_state *context)
2695 {
2696 }
2697
2698 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2699 {
2700 struct dce_hwseq *hws = dc->hwseq;
2701 int fe_idx = pipe_ctx->plane_res.mi ?
2702 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2703
2704 /* Do not power down fe when stream is active on dce*/
2705 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2706 return;
2707
2708 hws->funcs.enable_display_power_gating(
2709 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2710
2711 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2712 dc->res_pool->transforms[fe_idx]);
2713 }
2714
2715 static void dce110_wait_for_mpcc_disconnect(
2716 struct dc *dc,
2717 struct resource_pool *res_pool,
2718 struct pipe_ctx *pipe_ctx)
2719 {
2720 /* do nothing*/
2721 }
2722
2723 static void program_output_csc(struct dc *dc,
2724 struct pipe_ctx *pipe_ctx,
2725 enum dc_color_space colorspace,
2726 uint16_t *matrix,
2727 int opp_id)
2728 {
2729 int i;
2730 struct out_csc_color_matrix tbl_entry;
2731
2732 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2733 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2734
2735 for (i = 0; i < 12; i++)
2736 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2737
2738 tbl_entry.color_space = color_space;
2739
2740 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2741 pipe_ctx->plane_res.xfm, &tbl_entry);
2742 }
2743 }
2744
2745 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2746 {
2747 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2748 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2749 struct mem_input *mi = pipe_ctx->plane_res.mi;
2750 struct dc_cursor_mi_param param = {
2751 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2752 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2753 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2754 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2755 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2756 .rotation = pipe_ctx->plane_state->rotation,
2757 .mirror = pipe_ctx->plane_state->horizontal_mirror
2758 };
2759
2760 /**
2761 * If the cursor's source viewport is clipped then we need to
2762 * translate the cursor to appear in the correct position on
2763 * the screen.
2764 *
2765 * This translation isn't affected by scaling so it needs to be
2766 * done *after* we adjust the position for the scale factor.
2767 *
2768 * This is only done by opt-in for now since there are still
2769 * some usecases like tiled display that might enable the
2770 * cursor on both streams while expecting dc to clip it.
2771 */
2772 if (pos_cpy.translate_by_source) {
2773 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2774 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2775 }
2776
2777 if (pipe_ctx->plane_state->address.type
2778 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2779 pos_cpy.enable = false;
2780
2781 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2782 pos_cpy.enable = false;
2783
2784 if (ipp->funcs->ipp_cursor_set_position)
2785 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2786 if (mi->funcs->set_cursor_position)
2787 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2788 }
2789
2790 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2791 {
2792 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2793
2794 if (pipe_ctx->plane_res.ipp &&
2795 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2796 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2797 pipe_ctx->plane_res.ipp, attributes);
2798
2799 if (pipe_ctx->plane_res.mi &&
2800 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2801 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2802 pipe_ctx->plane_res.mi, attributes);
2803
2804 if (pipe_ctx->plane_res.xfm &&
2805 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2806 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2807 pipe_ctx->plane_res.xfm, attributes);
2808 }
2809
2810 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
2811 uint32_t backlight_pwm_u16_16,
2812 uint32_t frame_ramp)
2813 {
2814 struct dc_link *link = pipe_ctx->stream->link;
2815 struct dc *dc = link->ctx->dc;
2816 struct abm *abm = pipe_ctx->stream_res.abm;
2817 struct panel_cntl *panel_cntl = link->panel_cntl;
2818 struct dmcu *dmcu = dc->res_pool->dmcu;
2819 bool fw_set_brightness = true;
2820 /* DMCU -1 for all controller id values,
2821 * therefore +1 here
2822 */
2823 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
2824
2825 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
2826 return false;
2827
2828 if (dmcu)
2829 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2830
2831 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
2832 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
2833 else
2834 abm->funcs->set_backlight_level_pwm(
2835 abm,
2836 backlight_pwm_u16_16,
2837 frame_ramp,
2838 controller_id,
2839 link->panel_cntl->inst);
2840
2841 return true;
2842 }
2843
2844 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
2845 {
2846 struct abm *abm = pipe_ctx->stream_res.abm;
2847 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2848
2849 if (abm)
2850 abm->funcs->set_abm_immediate_disable(abm,
2851 pipe_ctx->stream->link->panel_cntl->inst);
2852
2853 if (panel_cntl)
2854 panel_cntl->funcs->store_backlight_level(panel_cntl);
2855 }
2856
2857 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
2858 {
2859 struct abm *abm = pipe_ctx->stream_res.abm;
2860 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2861 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
2862
2863 if (abm && panel_cntl)
2864 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
2865 }
2866
2867 static const struct hw_sequencer_funcs dce110_funcs = {
2868 .program_gamut_remap = program_gamut_remap,
2869 .program_output_csc = program_output_csc,
2870 .init_hw = init_hw,
2871 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2872 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2873 .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
2874 .update_plane_addr = update_plane_addr,
2875 .update_pending_status = dce110_update_pending_status,
2876 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2877 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2878 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2879 .update_info_frame = dce110_update_info_frame,
2880 .enable_stream = dce110_enable_stream,
2881 .disable_stream = dce110_disable_stream,
2882 .unblank_stream = dce110_unblank_stream,
2883 .blank_stream = dce110_blank_stream,
2884 .enable_audio_stream = dce110_enable_audio_stream,
2885 .disable_audio_stream = dce110_disable_audio_stream,
2886 .disable_plane = dce110_power_down_fe,
2887 .pipe_control_lock = dce_pipe_control_lock,
2888 .interdependent_update_lock = NULL,
2889 .cursor_lock = dce_pipe_control_lock,
2890 .prepare_bandwidth = dce110_prepare_bandwidth,
2891 .optimize_bandwidth = dce110_optimize_bandwidth,
2892 .set_drr = set_drr,
2893 .get_position = get_position,
2894 .set_static_screen_control = set_static_screen_control,
2895 .setup_stereo = NULL,
2896 .set_avmute = dce110_set_avmute,
2897 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2898 .edp_backlight_control = dce110_edp_backlight_control,
2899 .edp_power_control = dce110_edp_power_control,
2900 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
2901 .set_cursor_position = dce110_set_cursor_position,
2902 .set_cursor_attribute = dce110_set_cursor_attribute,
2903 .set_backlight_level = dce110_set_backlight_level,
2904 .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
2905 .set_pipe = dce110_set_pipe,
2906 };
2907
2908 static const struct hwseq_private_funcs dce110_private_funcs = {
2909 .init_pipes = init_pipes,
2910 .update_plane_addr = update_plane_addr,
2911 .set_input_transfer_func = dce110_set_input_transfer_func,
2912 .set_output_transfer_func = dce110_set_output_transfer_func,
2913 .power_down = dce110_power_down,
2914 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2915 .enable_display_power_gating = dce110_enable_display_power_gating,
2916 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2917 .enable_stream_timing = dce110_enable_stream_timing,
2918 .disable_stream_gating = NULL,
2919 .enable_stream_gating = NULL,
2920 .edp_backlight_control = dce110_edp_backlight_control,
2921 };
2922
2923 void dce110_hw_sequencer_construct(struct dc *dc)
2924 {
2925 dc->hwss = dce110_funcs;
2926 dc->hwseq->funcs = dce110_private_funcs;
2927 }
2928
Linux with added FPC-III support