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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_dpp_dscl.c
blobefa86d5c68470cc6832c9a9360310e129adea27f
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "core_types.h"
29
30 #include "reg_helper.h"
31 #include "dcn10_dpp.h"
32 #include "basics/conversion.h"
33
34
35 #define NUM_PHASES 64
36 #define HORZ_MAX_TAPS 8
37 #define VERT_MAX_TAPS 8
38
39 #define BLACK_OFFSET_RGB_Y 0x0
40 #define BLACK_OFFSET_CBCR 0x8000
41
42 #define REG(reg)\
43 dpp->tf_regs->reg
44
45 #define CTX \
46 dpp->base.ctx
47
48 #undef FN
49 #define FN(reg_name, field_name) \
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51
52 enum dcn10_coef_filter_type_sel {
53 SCL_COEF_LUMA_VERT_FILTER = 0,
54 SCL_COEF_LUMA_HORZ_FILTER = 1,
55 SCL_COEF_CHROMA_VERT_FILTER = 2,
56 SCL_COEF_CHROMA_HORZ_FILTER = 3,
57 SCL_COEF_ALPHA_VERT_FILTER = 4,
58 SCL_COEF_ALPHA_HORZ_FILTER = 5
59 };
60
61 enum dscl_autocal_mode {
62 AUTOCAL_MODE_OFF = 0,
63
64 /* Autocal calculate the scaling ratio and initial phase and the
65 * DSCL_MODE_SEL must be set to 1
66 */
67 AUTOCAL_MODE_AUTOSCALE = 1,
68 /* Autocal perform auto centering without replication and the
69 * DSCL_MODE_SEL must be set to 0
70 */
71 AUTOCAL_MODE_AUTOCENTER = 2,
72 /* Autocal perform auto centering and auto replication and the
73 * DSCL_MODE_SEL must be set to 0
74 */
75 AUTOCAL_MODE_AUTOREPLICATE = 3
76 };
77
78 enum dscl_mode_sel {
79 DSCL_MODE_SCALING_444_BYPASS = 0,
80 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
81 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
82 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
83 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
84 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
85 DSCL_MODE_DSCL_BYPASS = 6
86 };
87
88 static void dpp1_dscl_set_overscan(
89 struct dcn10_dpp *dpp,
90 const struct scaler_data *data)
91 {
92 uint32_t left = data->recout.x;
93 uint32_t top = data->recout.y;
94
95 int right = data->h_active - data->recout.x - data->recout.width;
96 int bottom = data->v_active - data->recout.y - data->recout.height;
97
98 if (right < 0) {
99 BREAK_TO_DEBUGGER();
100 right = 0;
101 }
102 if (bottom < 0) {
103 BREAK_TO_DEBUGGER();
104 bottom = 0;
105 }
106
107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
108 EXT_OVERSCAN_LEFT, left,
109 EXT_OVERSCAN_RIGHT, right);
110
111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
112 EXT_OVERSCAN_BOTTOM, bottom,
113 EXT_OVERSCAN_TOP, top);
114 }
115
116 static void dpp1_dscl_set_otg_blank(
117 struct dcn10_dpp *dpp, const struct scaler_data *data)
118 {
119 uint32_t h_blank_start = data->h_active;
120 uint32_t h_blank_end = 0;
121 uint32_t v_blank_start = data->v_active;
122 uint32_t v_blank_end = 0;
123
124 REG_SET_2(OTG_H_BLANK, 0,
125 OTG_H_BLANK_START, h_blank_start,
126 OTG_H_BLANK_END, h_blank_end);
127
128 REG_SET_2(OTG_V_BLANK, 0,
129 OTG_V_BLANK_START, v_blank_start,
130 OTG_V_BLANK_END, v_blank_end);
131 }
132
133 static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
134 {
135 if (depth == LB_PIXEL_DEPTH_30BPP)
136 return 0; /* 10 bpc */
137 else if (depth == LB_PIXEL_DEPTH_24BPP)
138 return 1; /* 8 bpc */
139 else if (depth == LB_PIXEL_DEPTH_18BPP)
140 return 2; /* 6 bpc */
141 else if (depth == LB_PIXEL_DEPTH_36BPP)
142 return 3; /* 12 bpc */
143 else {
144 ASSERT(0);
145 return -1; /* Unsupported */
146 }
147 }
148
149 static bool dpp1_dscl_is_video_format(enum pixel_format format)
150 {
151 if (format >= PIXEL_FORMAT_VIDEO_BEGIN
152 && format <= PIXEL_FORMAT_VIDEO_END)
153 return true;
154 else
155 return false;
156 }
157
158 static bool dpp1_dscl_is_420_format(enum pixel_format format)
159 {
160 if (format == PIXEL_FORMAT_420BPP8 ||
161 format == PIXEL_FORMAT_420BPP10)
162 return true;
163 else
164 return false;
165 }
166
167 static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
168 struct dpp *dpp_base,
169 const struct scaler_data *data,
170 bool dbg_always_scale)
171 {
172 const long long one = dc_fixpt_one.value;
173
174 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
175 /* DSCL is processing data in fixed format */
176 if (data->format == PIXEL_FORMAT_FP16)
177 return DSCL_MODE_DSCL_BYPASS;
178 }
179
180 if (data->ratios.horz.value == one
181 && data->ratios.vert.value == one
182 && data->ratios.horz_c.value == one
183 && data->ratios.vert_c.value == one
184 && !dbg_always_scale)
185 return DSCL_MODE_SCALING_444_BYPASS;
186
187 if (!dpp1_dscl_is_420_format(data->format)) {
188 if (dpp1_dscl_is_video_format(data->format))
189 return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
190 else
191 return DSCL_MODE_SCALING_444_RGB_ENABLE;
192 }
193 if (data->ratios.horz.value == one && data->ratios.vert.value == one)
194 return DSCL_MODE_SCALING_420_LUMA_BYPASS;
195 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
196 return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
197
198 return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
199 }
200
201 static void dpp1_power_on_dscl(
202 struct dpp *dpp_base,
203 bool power_on)
204 {
205 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
206
207 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {
208 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, power_on ? 0 : 3);
209 if (power_on)
210 REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5);
211 }
212 }
213
214
215 static void dpp1_dscl_set_lb(
216 struct dcn10_dpp *dpp,
217 const struct line_buffer_params *lb_params,
218 enum lb_memory_config mem_size_config)
219 {
220 /* LB */
221 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
222 /* DSCL caps: pixel data processed in fixed format */
223 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);
224 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
225
226 REG_SET_7(LB_DATA_FORMAT, 0,
227 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */
228 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */
229 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */
230 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */
231 DITHER_EN, 0, /* Dithering enable: Disabled */
232 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
233 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
234 }
235 else {
236 /* DSCL caps: pixel data processed in float format */
237 REG_SET_2(LB_DATA_FORMAT, 0,
238 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
239 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
240 }
241
242 REG_SET_2(LB_MEMORY_CTRL, 0,
243 MEMORY_CONFIG, mem_size_config,
244 LB_MAX_PARTITIONS, 63);
245 }
246
247 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
248 {
249 if (taps == 8)
250 return get_filter_8tap_64p(ratio);
251 else if (taps == 7)
252 return get_filter_7tap_64p(ratio);
253 else if (taps == 6)
254 return get_filter_6tap_64p(ratio);
255 else if (taps == 5)
256 return get_filter_5tap_64p(ratio);
257 else if (taps == 4)
258 return get_filter_4tap_64p(ratio);
259 else if (taps == 3)
260 return get_filter_3tap_64p(ratio);
261 else if (taps == 2)
262 return get_filter_2tap_64p();
263 else if (taps == 1)
264 return NULL;
265 else {
266 /* should never happen, bug */
267 BREAK_TO_DEBUGGER();
268 return NULL;
269 }
270 }
271
272 static void dpp1_dscl_set_scaler_filter(
273 struct dcn10_dpp *dpp,
274 uint32_t taps,
275 enum dcn10_coef_filter_type_sel filter_type,
276 const uint16_t *filter)
277 {
278 const int tap_pairs = (taps + 1) / 2;
279 int phase;
280 int pair;
281 uint16_t odd_coef, even_coef;
282
283 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
284 SCL_COEF_RAM_TAP_PAIR_IDX, 0,
285 SCL_COEF_RAM_PHASE, 0,
286 SCL_COEF_RAM_FILTER_TYPE, filter_type);
287
288 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
289 for (pair = 0; pair < tap_pairs; pair++) {
290 even_coef = filter[phase * taps + 2 * pair];
291 if ((pair * 2 + 1) < taps)
292 odd_coef = filter[phase * taps + 2 * pair + 1];
293 else
294 odd_coef = 0;
295
296 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
297 /* Even tap coefficient (bits 1:0 fixed to 0) */
298 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,
299 /* Write/read control for even coefficient */
300 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,
301 /* Odd tap coefficient (bits 1:0 fixed to 0) */
302 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,
303 /* Write/read control for odd coefficient */
304 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1);
305 }
306 }
307
308 }
309
310 static void dpp1_dscl_set_scl_filter(
311 struct dcn10_dpp *dpp,
312 const struct scaler_data *scl_data,
313 bool chroma_coef_mode)
314 {
315 bool h_2tap_hardcode_coef_en = false;
316 bool v_2tap_hardcode_coef_en = false;
317 bool h_2tap_sharp_en = false;
318 bool v_2tap_sharp_en = false;
319 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
320 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
321 bool coef_ram_current;
322 const uint16_t *filter_h = NULL;
323 const uint16_t *filter_v = NULL;
324 const uint16_t *filter_h_c = NULL;
325 const uint16_t *filter_v_c = NULL;
326
327 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
328 && scl_data->taps.h_taps_c < 3
329 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
330 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
331 && scl_data->taps.v_taps_c < 3
332 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
333
334 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
335 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
336
337 REG_UPDATE_6(DSCL_2TAP_CONTROL,
338 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,
339 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,
340 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,
341 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,
342 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,
343 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor);
344
345 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
346 bool filter_updated = false;
347
348 filter_h = dpp1_dscl_get_filter_coeffs_64p(
349 scl_data->taps.h_taps, scl_data->ratios.horz);
350 filter_v = dpp1_dscl_get_filter_coeffs_64p(
351 scl_data->taps.v_taps, scl_data->ratios.vert);
352
353 filter_updated = (filter_h && (filter_h != dpp->filter_h))
354 || (filter_v && (filter_v != dpp->filter_v));
355
356 if (chroma_coef_mode) {
357 filter_h_c = dpp1_dscl_get_filter_coeffs_64p(
358 scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
359 filter_v_c = dpp1_dscl_get_filter_coeffs_64p(
360 scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
361 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
362 || (filter_v_c && (filter_v_c != dpp->filter_v_c));
363 }
364
365 if (filter_updated) {
366 uint32_t scl_mode = REG_READ(SCL_MODE);
367
368 if (!h_2tap_hardcode_coef_en && filter_h) {
369 dpp1_dscl_set_scaler_filter(
370 dpp, scl_data->taps.h_taps,
371 SCL_COEF_LUMA_HORZ_FILTER, filter_h);
372 }
373 dpp->filter_h = filter_h;
374 if (!v_2tap_hardcode_coef_en && filter_v) {
375 dpp1_dscl_set_scaler_filter(
376 dpp, scl_data->taps.v_taps,
377 SCL_COEF_LUMA_VERT_FILTER, filter_v);
378 }
379 dpp->filter_v = filter_v;
380 if (chroma_coef_mode) {
381 if (!h_2tap_hardcode_coef_en && filter_h_c) {
382 dpp1_dscl_set_scaler_filter(
383 dpp, scl_data->taps.h_taps_c,
384 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
385 }
386 if (!v_2tap_hardcode_coef_en && filter_v_c) {
387 dpp1_dscl_set_scaler_filter(
388 dpp, scl_data->taps.v_taps_c,
389 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
390 }
391 }
392 dpp->filter_h_c = filter_h_c;
393 dpp->filter_v_c = filter_v_c;
394
395 coef_ram_current = get_reg_field_value_ex(
396 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
397 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
398
399 /* Swap coefficient RAM and set chroma coefficient mode */
400 REG_SET_2(SCL_MODE, scl_mode,
401 SCL_COEF_RAM_SELECT, !coef_ram_current,
402 SCL_CHROMA_COEF_MODE, chroma_coef_mode);
403 }
404 }
405 }
406
407 static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)
408 {
409 if (depth == LB_PIXEL_DEPTH_30BPP)
410 return 10;
411 else if (depth == LB_PIXEL_DEPTH_24BPP)
412 return 8;
413 else if (depth == LB_PIXEL_DEPTH_18BPP)
414 return 6;
415 else if (depth == LB_PIXEL_DEPTH_36BPP)
416 return 12;
417 else {
418 BREAK_TO_DEBUGGER();
419 return -1; /* Unsupported */
420 }
421 }
422
423 void dpp1_dscl_calc_lb_num_partitions(
424 const struct scaler_data *scl_data,
425 enum lb_memory_config lb_config,
426 int *num_part_y,
427 int *num_part_c)
428 {
429 int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a,
430 lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a;
431
432 int line_size = scl_data->viewport.width < scl_data->recout.width ?
433 scl_data->viewport.width : scl_data->recout.width;
434 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
435 scl_data->viewport_c.width : scl_data->recout.width;
436
437 if (line_size == 0)
438 line_size = 1;
439
440 if (line_size_c == 0)
441 line_size_c = 1;
442
443
444 lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
445 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
446 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
447 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
448
449 if (lb_config == LB_MEMORY_CONFIG_1) {
450 lb_memory_size = 816;
451 lb_memory_size_c = 816;
452 lb_memory_size_a = 984;
453 } else if (lb_config == LB_MEMORY_CONFIG_2) {
454 lb_memory_size = 1088;
455 lb_memory_size_c = 1088;
456 lb_memory_size_a = 1312;
457 } else if (lb_config == LB_MEMORY_CONFIG_3) {
458 /* 420 mode: using 3rd mem from Y, Cr and Cb */
459 lb_memory_size = 816 + 1088 + 848 + 848 + 848;
460 lb_memory_size_c = 816 + 1088;
461 lb_memory_size_a = 984 + 1312 + 456;
462 } else {
463 lb_memory_size = 816 + 1088 + 848;
464 lb_memory_size_c = 816 + 1088 + 848;
465 lb_memory_size_a = 984 + 1312 + 456;
466 }
467 *num_part_y = lb_memory_size / memory_line_size_y;
468 *num_part_c = lb_memory_size_c / memory_line_size_c;
469 num_partitions_a = lb_memory_size_a / memory_line_size_a;
470
471 if (scl_data->lb_params.alpha_en
472 && (num_partitions_a < *num_part_y))
473 *num_part_y = num_partitions_a;
474
475 if (*num_part_y > 64)
476 *num_part_y = 64;
477 if (*num_part_c > 64)
478 *num_part_c = 64;
479
480 }
481
482 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
483 {
484 if (ceil_vratio > 2)
485 return vtaps <= (num_partitions - ceil_vratio + 2);
486 else
487 return vtaps <= num_partitions;
488 }
489
490 /*find first match configuration which meets the min required lb size*/
491 static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
492 const struct scaler_data *scl_data)
493 {
494 int num_part_y, num_part_c;
495 int vtaps = scl_data->taps.v_taps;
496 int vtaps_c = scl_data->taps.v_taps_c;
497 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
498 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
499 enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0;
500
501 if (dpp->base.ctx->dc->debug.use_max_lb)
502 return mem_cfg;
503
504 dpp->base.caps->dscl_calc_lb_num_partitions(
505 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
506
507 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
508 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
509 return LB_MEMORY_CONFIG_1;
510
511 dpp->base.caps->dscl_calc_lb_num_partitions(
512 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
513
514 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
515 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
516 return LB_MEMORY_CONFIG_2;
517
518 if (scl_data->format == PIXEL_FORMAT_420BPP8
519 || scl_data->format == PIXEL_FORMAT_420BPP10) {
520 dpp->base.caps->dscl_calc_lb_num_partitions(
521 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
522
523 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
524 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
525 return LB_MEMORY_CONFIG_3;
526 }
527
528 dpp->base.caps->dscl_calc_lb_num_partitions(
529 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
530
531 /*Ensure we can support the requested number of vtaps*/
532 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
533 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));
534
535 return LB_MEMORY_CONFIG_0;
536 }
537
538 void dpp1_dscl_set_scaler_auto_scale(
539 struct dpp *dpp_base,
540 const struct scaler_data *scl_data)
541 {
542 enum lb_memory_config lb_config;
543 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
544 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
545 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
546 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
547 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
548
549 dpp1_dscl_set_overscan(dpp, scl_data);
550
551 dpp1_dscl_set_otg_blank(dpp, scl_data);
552
553 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
554
555 if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
556 return;
557
558 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
559 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
560
561 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
562 return;
563
564 /* TODO: v_min */
565 REG_SET_3(DSCL_AUTOCAL, 0,
566 AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,
567 AUTOCAL_NUM_PIPE, 0,
568 AUTOCAL_PIPE_ID, 0);
569
570 /* Black offsets */
571 if (ycbcr)
572 REG_SET_2(SCL_BLACK_OFFSET, 0,
573 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
574 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
575 else
576
577 REG_SET_2(SCL_BLACK_OFFSET, 0,
578 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
579 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
580
581 REG_SET_4(SCL_TAP_CONTROL, 0,
582 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
583 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
584 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
585 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
586
587 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
588 }
589
590
591 static void dpp1_dscl_set_manual_ratio_init(
592 struct dcn10_dpp *dpp, const struct scaler_data *data)
593 {
594 uint32_t init_frac = 0;
595 uint32_t init_int = 0;
596
597 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
598 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5);
599
600 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
601 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5);
602
603 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
604 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5);
605
606 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
607 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5);
608
609 /*
610 * 0.24 format for fraction, first five bits zeroed
611 */
612 init_frac = dc_fixpt_u0d19(data->inits.h) << 5;
613 init_int = dc_fixpt_floor(data->inits.h);
614 REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
615 SCL_H_INIT_FRAC, init_frac,
616 SCL_H_INIT_INT, init_int);
617
618 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5;
619 init_int = dc_fixpt_floor(data->inits.h_c);
620 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
621 SCL_H_INIT_FRAC_C, init_frac,
622 SCL_H_INIT_INT_C, init_int);
623
624 init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
625 init_int = dc_fixpt_floor(data->inits.v);
626 REG_SET_2(SCL_VERT_FILTER_INIT, 0,
627 SCL_V_INIT_FRAC, init_frac,
628 SCL_V_INIT_INT, init_int);
629
630 if (REG(SCL_VERT_FILTER_INIT_BOT)) {
631 init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5;
632 init_int = dc_fixpt_floor(data->inits.v_bot);
633 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
634 SCL_V_INIT_FRAC_BOT, init_frac,
635 SCL_V_INIT_INT_BOT, init_int);
636 }
637
638 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
639 init_int = dc_fixpt_floor(data->inits.v_c);
640 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
641 SCL_V_INIT_FRAC_C, init_frac,
642 SCL_V_INIT_INT_C, init_int);
643
644 if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
645 init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5;
646 init_int = dc_fixpt_floor(data->inits.v_c_bot);
647 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
648 SCL_V_INIT_FRAC_BOT_C, init_frac,
649 SCL_V_INIT_INT_BOT_C, init_int);
650 }
651 }
652
653
654
655 static void dpp1_dscl_set_recout(
656 struct dcn10_dpp *dpp, const struct rect *recout)
657 {
658 int visual_confirm_on = 0;
659 if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
660 visual_confirm_on = 1;
661
662 REG_SET_2(RECOUT_START, 0,
663 /* First pixel of RECOUT */
664 RECOUT_START_X, recout->x,
665 /* First line of RECOUT */
666 RECOUT_START_Y, recout->y);
667
668 REG_SET_2(RECOUT_SIZE, 0,
669 /* Number of RECOUT horizontal pixels */
670 RECOUT_WIDTH, recout->width,
671 /* Number of RECOUT vertical lines */
672 RECOUT_HEIGHT, recout->height
673 - visual_confirm_on * 2 * (dpp->base.inst + 1));
674 }
675
676 /* Main function to program scaler and line buffer in manual scaling mode */
677 void dpp1_dscl_set_scaler_manual_scale(
678 struct dpp *dpp_base,
679 const struct scaler_data *scl_data)
680 {
681 enum lb_memory_config lb_config;
682 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
683 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
684 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
685 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
686 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
687
688 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
689 return;
690
691 PERF_TRACE();
692
693 dpp->scl_data = *scl_data;
694
695 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {
696 if (dscl_mode != DSCL_MODE_DSCL_BYPASS)
697 dpp1_power_on_dscl(dpp_base, true);
698 }
699
700 /* Autocal off */
701 REG_SET_3(DSCL_AUTOCAL, 0,
702 AUTOCAL_MODE, AUTOCAL_MODE_OFF,
703 AUTOCAL_NUM_PIPE, 0,
704 AUTOCAL_PIPE_ID, 0);
705
706 /* Recout */
707 dpp1_dscl_set_recout(dpp, &scl_data->recout);
708
709 /* MPC Size */
710 REG_SET_2(MPC_SIZE, 0,
711 /* Number of horizontal pixels of MPC */
712 MPC_WIDTH, scl_data->h_active,
713 /* Number of vertical lines of MPC */
714 MPC_HEIGHT, scl_data->v_active);
715
716 /* SCL mode */
717 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
718
719 if (dscl_mode == DSCL_MODE_DSCL_BYPASS) {
720 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)
721 dpp1_power_on_dscl(dpp_base, false);
722 return;
723 }
724
725 /* LB */
726 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
727 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
728
729 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
730 return;
731
732 /* Black offsets */
733 if (REG(SCL_BLACK_OFFSET)) {
734 if (ycbcr)
735 REG_SET_2(SCL_BLACK_OFFSET, 0,
736 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
737 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
738 else
739
740 REG_SET_2(SCL_BLACK_OFFSET, 0,
741 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
742 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
743 }
744
745 /* Manually calculate scale ratio and init values */
746 dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
747
748 /* HTaps/VTaps */
749 REG_SET_4(SCL_TAP_CONTROL, 0,
750 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
751 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
752 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
753 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
754
755 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
756 PERF_TRACE();
757 }
Linux with added FPC-III support