drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_HWSS_DCN10_H__
  27 #define __DC_HWSS_DCN10_H__
  28
  29 #include "core_types.h"
  30 #include "hw_sequencer_private.h"
  31
  32 struct dc;
  33
  34 void dcn10_hw_sequencer_construct(struct dc *dc);
  35
  36 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
  37 void dcn10_calc_vupdate_position(
  38                 struct dc *dc,
  39                 struct pipe_ctx *pipe_ctx,
  40                 uint32_t *start_line,
  41                 uint32_t *end_line);
  42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
  43 enum dc_status dcn10_enable_stream_timing(
  44                 struct pipe_ctx *pipe_ctx,
  45                 struct dc_state *context,
  46                 struct dc *dc);
  47 void dcn10_optimize_bandwidth(
  48                 struct dc *dc,
  49                 struct dc_state *context);
  50 void dcn10_prepare_bandwidth(
  51                 struct dc *dc,
  52                 struct dc_state *context);
  53 void dcn10_pipe_control_lock(
  54         struct dc *dc,
  55         struct pipe_ctx *pipe,
  56         bool lock);
  57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
  58 void dcn10_blank_pixel_data(
  59                 struct dc *dc,
  60                 struct pipe_ctx *pipe_ctx,
  61                 bool blank);
  62 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
  63                 struct dc_link_settings *link_settings);
  64 void dcn10_program_output_csc(struct dc *dc,
  65                 struct pipe_ctx *pipe_ctx,
  66                 enum dc_color_space colorspace,
  67                 uint16_t *matrix,
  68                 int opp_id);
  69 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  70                                 const struct dc_stream_state *stream);
  71 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  72                         const struct dc_plane_state *plane_state);
  73 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
  74 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
  75 void dcn10_reset_hw_ctx_wrap(
  76                 struct dc *dc,
  77                 struct dc_state *context);
  78 void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
  79 void dcn10_lock_all_pipes(
  80                 struct dc *dc,
  81                 struct dc_state *context,
  82                 bool lock);
  83 void dcn10_apply_ctx_for_surface(
  84                 struct dc *dc,
  85                 const struct dc_stream_state *stream,
  86                 int num_planes,
  87                 struct dc_state *context);
  88 void dcn10_post_unlock_program_front_end(
  89                 struct dc *dc,
  90                 struct dc_state *context);
  91 void dcn10_hubp_pg_control(
  92                 struct dce_hwseq *hws,
  93                 unsigned int hubp_inst,
  94                 bool power_on);
  95 void dcn10_dpp_pg_control(
  96                 struct dce_hwseq *hws,
  97                 unsigned int dpp_inst,
  98                 bool power_on);
  99 void dcn10_enable_power_gating_plane(
 100         struct dce_hwseq *hws,
 101         bool enable);
 102 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
 103 void dcn10_disable_vga(
 104         struct dce_hwseq *hws);
 105 void dcn10_program_pipe(
 106                 struct dc *dc,
 107                 struct pipe_ctx *pipe_ctx,
 108                 struct dc_state *context);
 109 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
 110 void dcn10_init_hw(struct dc *dc);
 111 void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
 112 void dcn10_power_down_on_boot(struct dc *dc);
 113 enum dc_status dce110_apply_ctx_to_hw(
 114                 struct dc *dc,
 115                 struct dc_state *context);
 116 void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
 117 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
 118 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);
 119 void dce110_power_down(struct dc *dc);
 120 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
 121 void dcn10_enable_timing_synchronization(
 122                 struct dc *dc,
 123                 int group_index,
 124                 int group_size,
 125                 struct pipe_ctx *grouped_pipes[]);
 126 void dcn10_enable_per_frame_crtc_position_reset(
 127                 struct dc *dc,
 128                 int group_size,
 129                 struct pipe_ctx *grouped_pipes[]);
 130 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
 131 void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
 132                 const uint8_t *custom_sdp_message,
 133                 unsigned int sdp_message_size);
 134 void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
 135 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
 136 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
 137 bool dcn10_dummy_display_power_gating(
 138                 struct dc *dc,
 139                 uint8_t controller_id,
 140                 struct dc_bios *dcb,
 141                 enum pipe_gating_control power_gating);
 142 void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
 143                 int num_pipes, unsigned int vmin, unsigned int vmax,
 144                 unsigned int vmid, unsigned int vmid_frame_number);
 145 void dcn10_get_position(struct pipe_ctx **pipe_ctx,
 146                 int num_pipes,
 147                 struct crtc_position *position);
 148 void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
 149                 int num_pipes, const struct dc_static_screen_params *params);
 150 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);
 151 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
 152 void dcn10_log_hw_state(struct dc *dc,
 153                 struct dc_log_buffer_ctx *log_ctx);
 154 void dcn10_get_hw_state(struct dc *dc,
 155                 char *pBuf,
 156                 unsigned int bufSize,
 157                 unsigned int mask);
 158 void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
 159 void dcn10_wait_for_mpcc_disconnect(
 160                 struct dc *dc,
 161                 struct resource_pool *res_pool,
 162                 struct pipe_ctx *pipe_ctx);
 163 void dce110_edp_backlight_control(
 164                 struct dc_link *link,
 165                 bool enable);
 166 void dce110_edp_power_control(
 167                 struct dc_link *link,
 168                 bool power_up);
 169 void dce110_edp_wait_for_hpd_ready(
 170                 struct dc_link *link,
 171                 bool power_up);
 172 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);
 173 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
 174 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
 175 void dcn10_setup_periodic_interrupt(
 176                 struct dc *dc,
 177                 struct pipe_ctx *pipe_ctx,
 178                 enum vline_select vline);
 179 enum dc_status dcn10_set_clock(struct dc *dc,
 180                 enum dc_clock_type clock_type,
 181                 uint32_t clk_khz,
 182                 uint32_t stepping);
 183 void dcn10_get_clock(struct dc *dc,
 184                 enum dc_clock_type clock_type,
 185                 struct dc_clock_config *clock_cfg);
 186 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
 187 void dcn10_bios_golden_init(struct dc *dc);
 188 void dcn10_plane_atomic_power_down(struct dc *dc,
 189                 struct dpp *dpp,
 190                 struct hubp *hubp);
 191 void dcn10_get_surface_visual_confirm_color(
 192                 const struct pipe_ctx *pipe_ctx,
 193                 struct tg_color *color);
 194 void dcn10_get_hdr_visual_confirm_color(
 195                 struct pipe_ctx *pipe_ctx,
 196                 struct tg_color *color);
 197 bool dcn10_disconnect_pipes(
 198                 struct dc *dc,
 199                 struct dc_state *context);
 200
 201 void dcn10_wait_for_pending_cleared(struct dc *dc,
 202                 struct dc_state *context);
 203 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
 204 void dcn10_verify_allow_pstate_change_high(struct dc *dc);
 205
 206 #endif /* __DC_HWSS_DCN10_H__ */