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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_link_encoder.c
blob81db0179f7ea8ac381b976c0ccbd28cbc36baa43
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28
29 #include "reg_helper.h"
30
31 #include "core_types.h"
32 #include "link_encoder.h"
33 #include "dcn10_link_encoder.h"
34 #include "stream_encoder.h"
35 #include "i2caux_interface.h"
36 #include "dc_bios_types.h"
37
38 #include "gpio_service_interface.h"
39
40 #define CTX \
41 enc10->base.ctx
42 #define DC_LOGGER \
43 enc10->base.ctx->logger
44
45 #define REG(reg)\
46 (enc10->link_regs->reg)
47
48 #undef FN
49 #define FN(reg_name, field_name) \
50 enc10->link_shift->field_name, enc10->link_mask->field_name
51
52
53 /*
54 * @brief
55 * Trigger Source Select
56 * ASIC-dependent, actual values for register programming
57 */
58 #define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
59 #define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
60 #define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
61 #define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
62 #define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
63 #define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
64 #define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
65 #define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
66
67 enum {
68 DP_MST_UPDATE_MAX_RETRY = 50
69 };
70
71 static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
72 .validate_output_with_stream =
73 dcn10_link_encoder_validate_output_with_stream,
74 .hw_init = dcn10_link_encoder_hw_init,
75 .setup = dcn10_link_encoder_setup,
76 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
77 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
78 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
79 .disable_output = dcn10_link_encoder_disable_output,
80 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
81 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
82 .update_mst_stream_allocation_table =
83 dcn10_link_encoder_update_mst_stream_allocation_table,
84 .psr_program_dp_dphy_fast_training =
85 dcn10_psr_program_dp_dphy_fast_training,
86 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
87 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
88 .enable_hpd = dcn10_link_encoder_enable_hpd,
89 .disable_hpd = dcn10_link_encoder_disable_hpd,
90 .is_dig_enabled = dcn10_is_dig_enabled,
91 .get_dig_frontend = dcn10_get_dig_frontend,
92 .get_dig_mode = dcn10_get_dig_mode,
93 .destroy = dcn10_link_encoder_destroy,
94 .get_max_link_cap = dcn10_link_encoder_get_max_link_cap,
95 };
96
97 static enum bp_result link_transmitter_control(
98 struct dcn10_link_encoder *enc10,
99 struct bp_transmitter_control *cntl)
100 {
101 enum bp_result result;
102 struct dc_bios *bp = enc10->base.ctx->dc_bios;
103
104 result = bp->funcs->transmitter_control(bp, cntl);
105
106 return result;
107 }
108
109 static void enable_phy_bypass_mode(
110 struct dcn10_link_encoder *enc10,
111 bool enable)
112 {
113 /* This register resides in DP back end block;
114 * transmitter is used for the offset
115 */
116 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
117
118 }
119
120 static void disable_prbs_symbols(
121 struct dcn10_link_encoder *enc10,
122 bool disable)
123 {
124 /* This register resides in DP back end block;
125 * transmitter is used for the offset
126 */
127 REG_UPDATE_4(DP_DPHY_CNTL,
128 DPHY_ATEST_SEL_LANE0, disable,
129 DPHY_ATEST_SEL_LANE1, disable,
130 DPHY_ATEST_SEL_LANE2, disable,
131 DPHY_ATEST_SEL_LANE3, disable);
132 }
133
134 static void disable_prbs_mode(
135 struct dcn10_link_encoder *enc10)
136 {
137 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
138 }
139
140 static void program_pattern_symbols(
141 struct dcn10_link_encoder *enc10,
142 uint16_t pattern_symbols[8])
143 {
144 /* This register resides in DP back end block;
145 * transmitter is used for the offset
146 */
147 REG_SET_3(DP_DPHY_SYM0, 0,
148 DPHY_SYM1, pattern_symbols[0],
149 DPHY_SYM2, pattern_symbols[1],
150 DPHY_SYM3, pattern_symbols[2]);
151
152 /* This register resides in DP back end block;
153 * transmitter is used for the offset
154 */
155 REG_SET_3(DP_DPHY_SYM1, 0,
156 DPHY_SYM4, pattern_symbols[3],
157 DPHY_SYM5, pattern_symbols[4],
158 DPHY_SYM6, pattern_symbols[5]);
159
160 /* This register resides in DP back end block;
161 * transmitter is used for the offset
162 */
163 REG_SET_2(DP_DPHY_SYM2, 0,
164 DPHY_SYM7, pattern_symbols[6],
165 DPHY_SYM8, pattern_symbols[7]);
166 }
167
168 static void set_dp_phy_pattern_d102(
169 struct dcn10_link_encoder *enc10)
170 {
171 /* Disable PHY Bypass mode to setup the test pattern */
172 enable_phy_bypass_mode(enc10, false);
173
174 /* For 10-bit PRBS or debug symbols
175 * please use the following sequence:
176 *
177 * Enable debug symbols on the lanes
178 */
179 disable_prbs_symbols(enc10, true);
180
181 /* Disable PRBS mode */
182 disable_prbs_mode(enc10);
183
184 /* Program debug symbols to be output */
185 {
186 uint16_t pattern_symbols[8] = {
187 0x2AA, 0x2AA, 0x2AA, 0x2AA,
188 0x2AA, 0x2AA, 0x2AA, 0x2AA
189 };
190
191 program_pattern_symbols(enc10, pattern_symbols);
192 }
193
194 /* Enable phy bypass mode to enable the test pattern */
195
196 enable_phy_bypass_mode(enc10, true);
197 }
198
199 static void set_link_training_complete(
200 struct dcn10_link_encoder *enc10,
201 bool complete)
202 {
203 /* This register resides in DP back end block;
204 * transmitter is used for the offset
205 */
206 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
207
208 }
209
210 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
211 struct link_encoder *enc,
212 uint32_t index)
213 {
214 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
215 /* Write Training Pattern */
216
217 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
218
219 /* Set HW Register Training Complete to false */
220
221 set_link_training_complete(enc10, false);
222
223 /* Disable PHY Bypass mode to output Training Pattern */
224
225 enable_phy_bypass_mode(enc10, false);
226
227 /* Disable PRBS mode */
228 disable_prbs_mode(enc10);
229 }
230
231 static void setup_panel_mode(
232 struct dcn10_link_encoder *enc10,
233 enum dp_panel_mode panel_mode)
234 {
235 uint32_t value;
236
237 if (!REG(DP_DPHY_INTERNAL_CTRL))
238 return;
239
240 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
241
242 switch (panel_mode) {
243 case DP_PANEL_MODE_EDP:
244 value = 0x1;
245 break;
246 case DP_PANEL_MODE_SPECIAL:
247 value = 0x11;
248 break;
249 default:
250 value = 0x0;
251 break;
252 }
253
254 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
255 }
256
257 static void set_dp_phy_pattern_symbol_error(
258 struct dcn10_link_encoder *enc10)
259 {
260 /* Disable PHY Bypass mode to setup the test pattern */
261 enable_phy_bypass_mode(enc10, false);
262
263 /* program correct panel mode*/
264 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
265
266 /* A PRBS23 pattern is used for most DP electrical measurements. */
267
268 /* Enable PRBS symbols on the lanes */
269 disable_prbs_symbols(enc10, false);
270
271 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
272 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
273 DPHY_PRBS_SEL, 1,
274 DPHY_PRBS_EN, 1);
275
276 /* Enable phy bypass mode to enable the test pattern */
277 enable_phy_bypass_mode(enc10, true);
278 }
279
280 static void set_dp_phy_pattern_prbs7(
281 struct dcn10_link_encoder *enc10)
282 {
283 /* Disable PHY Bypass mode to setup the test pattern */
284 enable_phy_bypass_mode(enc10, false);
285
286 /* A PRBS7 pattern is used for most DP electrical measurements. */
287
288 /* Enable PRBS symbols on the lanes */
289 disable_prbs_symbols(enc10, false);
290
291 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
292 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
293 DPHY_PRBS_SEL, 0,
294 DPHY_PRBS_EN, 1);
295
296 /* Enable phy bypass mode to enable the test pattern */
297 enable_phy_bypass_mode(enc10, true);
298 }
299
300 static void set_dp_phy_pattern_80bit_custom(
301 struct dcn10_link_encoder *enc10,
302 const uint8_t *pattern)
303 {
304 /* Disable PHY Bypass mode to setup the test pattern */
305 enable_phy_bypass_mode(enc10, false);
306
307 /* Enable debug symbols on the lanes */
308
309 disable_prbs_symbols(enc10, true);
310
311 /* Enable PHY bypass mode to enable the test pattern */
312 /* TODO is it really needed ? */
313
314 enable_phy_bypass_mode(enc10, true);
315
316 /* Program 80 bit custom pattern */
317 {
318 uint16_t pattern_symbols[8];
319
320 pattern_symbols[0] =
321 ((pattern[1] & 0x03) << 8) | pattern[0];
322 pattern_symbols[1] =
323 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
324 pattern_symbols[2] =
325 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
326 pattern_symbols[3] =
327 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
328 pattern_symbols[4] =
329 ((pattern[6] & 0x03) << 8) | pattern[5];
330 pattern_symbols[5] =
331 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
332 pattern_symbols[6] =
333 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
334 pattern_symbols[7] =
335 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
336
337 program_pattern_symbols(enc10, pattern_symbols);
338 }
339
340 /* Enable phy bypass mode to enable the test pattern */
341
342 enable_phy_bypass_mode(enc10, true);
343 }
344
345 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
346 struct dcn10_link_encoder *enc10,
347 unsigned int cp2520_pattern)
348 {
349
350 /* previously there is a register DP_HBR2_EYE_PATTERN
351 * that is enabled to get the pattern.
352 * But it does not work with the latest spec change,
353 * so we are programming the following registers manually.
354 *
355 * The following settings have been confirmed
356 * by Nick Chorney and Sandra Liu
357 */
358
359 /* Disable PHY Bypass mode to setup the test pattern */
360
361 enable_phy_bypass_mode(enc10, false);
362
363 /* Setup DIG encoder in DP SST mode */
364 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
365
366 /* ensure normal panel mode. */
367 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
368
369 /* no vbid after BS (SR)
370 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
371 * 11000260 / 11000104 / 110000FC
372 */
373 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
374 DP_IDLE_BS_INTERVAL, 0xFC,
375 DP_VBID_DISABLE, 1,
376 DP_VID_ENHANCED_FRAME_MODE, 1);
377
378 /* swap every BS with SR */
379 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
380
381 /* select cp2520 patterns */
382 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
383 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
384 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
385 else
386 /* pre-DCE11 can only generate CP2520 pattern 2 */
387 ASSERT(cp2520_pattern == 2);
388
389 /* set link training complete */
390 set_link_training_complete(enc10, true);
391
392 /* disable video stream */
393 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
394
395 /* Disable PHY Bypass mode to setup the test pattern */
396 enable_phy_bypass_mode(enc10, false);
397 }
398
399 static void set_dp_phy_pattern_passthrough_mode(
400 struct dcn10_link_encoder *enc10,
401 enum dp_panel_mode panel_mode)
402 {
403 /* program correct panel mode */
404 setup_panel_mode(enc10, panel_mode);
405
406 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
407 * in case we were doing HBR2 compliance pattern before
408 */
409 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
410 DP_IDLE_BS_INTERVAL, 0x2000,
411 DP_VBID_DISABLE, 0,
412 DP_VID_ENHANCED_FRAME_MODE, 1);
413
414 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
415
416 /* set link training complete */
417 set_link_training_complete(enc10, true);
418
419 /* Disable PHY Bypass mode to setup the test pattern */
420 enable_phy_bypass_mode(enc10, false);
421
422 /* Disable PRBS mode */
423 disable_prbs_mode(enc10);
424 }
425
426 /* return value is bit-vector */
427 static uint8_t get_frontend_source(
428 enum engine_id engine)
429 {
430 switch (engine) {
431 case ENGINE_ID_DIGA:
432 return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
433 case ENGINE_ID_DIGB:
434 return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
435 case ENGINE_ID_DIGC:
436 return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
437 case ENGINE_ID_DIGD:
438 return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
439 case ENGINE_ID_DIGE:
440 return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
441 case ENGINE_ID_DIGF:
442 return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
443 case ENGINE_ID_DIGG:
444 return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
445 default:
446 ASSERT_CRITICAL(false);
447 return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
448 }
449 }
450
451 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
452 {
453 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
454 int32_t value;
455 enum engine_id result;
456
457 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
458
459 switch (value) {
460 case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
461 result = ENGINE_ID_DIGA;
462 break;
463 case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
464 result = ENGINE_ID_DIGB;
465 break;
466 case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
467 result = ENGINE_ID_DIGC;
468 break;
469 case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
470 result = ENGINE_ID_DIGD;
471 break;
472 case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
473 result = ENGINE_ID_DIGE;
474 break;
475 case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
476 result = ENGINE_ID_DIGF;
477 break;
478 case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
479 result = ENGINE_ID_DIGG;
480 break;
481 default:
482 // invalid source select DIG
483 ASSERT(false);
484 result = ENGINE_ID_UNKNOWN;
485 }
486
487 return result;
488
489 }
490
491 void enc1_configure_encoder(
492 struct dcn10_link_encoder *enc10,
493 const struct dc_link_settings *link_settings)
494 {
495 /* set number of lanes */
496 REG_SET(DP_CONFIG, 0,
497 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
498
499 /* setup scrambler */
500 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
501 }
502
503 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
504 bool exit_link_training_required)
505 {
506 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
507
508 if (exit_link_training_required)
509 REG_UPDATE(DP_DPHY_FAST_TRAINING,
510 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
511 else {
512 REG_UPDATE(DP_DPHY_FAST_TRAINING,
513 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
514 /*In DCE 11, we are able to pre-program a Force SR register
515 * to be able to trigger SR symbol after 5 idle patterns
516 * transmitted. Upon PSR Exit, DMCU can trigger
517 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
518 * DPHY_LOAD_BS_COUNT_START and the internal counter
519 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
520 * replaced by SR symbol once.
521 */
522
523 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
524 }
525 }
526
527 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
528 unsigned int sdp_transmit_line_num_deadline)
529 {
530 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
531
532 REG_UPDATE_2(DP_SEC_CNTL1,
533 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
534 DP_SEC_GSP0_PRIORITY, 1);
535 }
536
537 bool dcn10_is_dig_enabled(struct link_encoder *enc)
538 {
539 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
540 uint32_t value;
541
542 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
543 return value;
544 }
545
546 static void link_encoder_disable(struct dcn10_link_encoder *enc10)
547 {
548 /* reset training pattern */
549 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
550 DPHY_TRAINING_PATTERN_SEL, 0);
551
552 /* reset training complete */
553 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
554
555 /* reset panel mode */
556 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
557 }
558
559 static void hpd_initialize(
560 struct dcn10_link_encoder *enc10)
561 {
562 /* Associate HPD with DIG_BE */
563 enum hpd_source_id hpd_source = enc10->base.hpd_source;
564
565 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
566 }
567
568 bool dcn10_link_encoder_validate_dvi_output(
569 const struct dcn10_link_encoder *enc10,
570 enum signal_type connector_signal,
571 enum signal_type signal,
572 const struct dc_crtc_timing *crtc_timing)
573 {
574 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
575
576 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
577 max_pixel_clock *= 2;
578
579 /* This handles the case of HDMI downgrade to DVI we don't want to
580 * we don't want to cap the pixel clock if the DDI is not DVI.
581 */
582 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
583 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
584 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
585
586 /* DVI only support RGB pixel encoding */
587 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
588 return false;
589
590 /*connect DVI via adpater's HDMI connector*/
591 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
592 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
593 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
594 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
595 return false;
596 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
597 return false;
598
599 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
600 return false;
601
602 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
603 switch (crtc_timing->display_color_depth) {
604 case COLOR_DEPTH_666:
605 case COLOR_DEPTH_888:
606 break;
607 case COLOR_DEPTH_101010:
608 case COLOR_DEPTH_161616:
609 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
610 return false;
611 break;
612 default:
613 return false;
614 }
615
616 return true;
617 }
618
619 static bool dcn10_link_encoder_validate_hdmi_output(
620 const struct dcn10_link_encoder *enc10,
621 const struct dc_crtc_timing *crtc_timing,
622 const struct dc_edid_caps *edid_caps,
623 int adjusted_pix_clk_100hz)
624 {
625 enum dc_color_depth max_deep_color =
626 enc10->base.features.max_hdmi_deep_color;
627
628 // check pixel clock against edid specified max TMDS clk
629 if (edid_caps->max_tmds_clk_mhz != 0 &&
630 adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
631 return false;
632
633 if (max_deep_color < crtc_timing->display_color_depth)
634 return false;
635
636 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
637 return false;
638 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
639 return false;
640
641 if ((adjusted_pix_clk_100hz == 0) ||
642 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
643 return false;
644
645 /* DCE11 HW does not support 420 */
646 if (!enc10->base.features.hdmi_ycbcr420_supported &&
647 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
648 return false;
649
650 if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
651 adjusted_pix_clk_100hz >= 3000000)
652 return false;
653 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
654 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
655 return false;
656 return true;
657 }
658
659 bool dcn10_link_encoder_validate_dp_output(
660 const struct dcn10_link_encoder *enc10,
661 const struct dc_crtc_timing *crtc_timing)
662 {
663 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
664 if (!enc10->base.features.dp_ycbcr420_supported)
665 return false;
666 }
667
668 return true;
669 }
670
671 void dcn10_link_encoder_construct(
672 struct dcn10_link_encoder *enc10,
673 const struct encoder_init_data *init_data,
674 const struct encoder_feature_support *enc_features,
675 const struct dcn10_link_enc_registers *link_regs,
676 const struct dcn10_link_enc_aux_registers *aux_regs,
677 const struct dcn10_link_enc_hpd_registers *hpd_regs,
678 const struct dcn10_link_enc_shift *link_shift,
679 const struct dcn10_link_enc_mask *link_mask)
680 {
681 struct bp_encoder_cap_info bp_cap_info = {0};
682 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
683 enum bp_result result = BP_RESULT_OK;
684
685 enc10->base.funcs = &dcn10_lnk_enc_funcs;
686 enc10->base.ctx = init_data->ctx;
687 enc10->base.id = init_data->encoder;
688
689 enc10->base.hpd_source = init_data->hpd_source;
690 enc10->base.connector = init_data->connector;
691
692 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
693
694 enc10->base.features = *enc_features;
695
696 enc10->base.transmitter = init_data->transmitter;
697
698 /* set the flag to indicate whether driver poll the I2C data pin
699 * while doing the DP sink detect
700 */
701
702 /* if (dal_adapter_service_is_feature_supported(as,
703 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
704 enc10->base.features.flags.bits.
705 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
706
707 enc10->base.output_signals =
708 SIGNAL_TYPE_DVI_SINGLE_LINK |
709 SIGNAL_TYPE_DVI_DUAL_LINK |
710 SIGNAL_TYPE_LVDS |
711 SIGNAL_TYPE_DISPLAY_PORT |
712 SIGNAL_TYPE_DISPLAY_PORT_MST |
713 SIGNAL_TYPE_EDP |
714 SIGNAL_TYPE_HDMI_TYPE_A;
715
716 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
717 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
718 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
719 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
720 * Prefer DIG assignment is decided by board design.
721 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
722 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
723 * By this, adding DIGG should not hurt DCE 8.0.
724 * This will let DCE 8.1 share DCE 8.0 as much as possible
725 */
726
727 enc10->link_regs = link_regs;
728 enc10->aux_regs = aux_regs;
729 enc10->hpd_regs = hpd_regs;
730 enc10->link_shift = link_shift;
731 enc10->link_mask = link_mask;
732
733 switch (enc10->base.transmitter) {
734 case TRANSMITTER_UNIPHY_A:
735 enc10->base.preferred_engine = ENGINE_ID_DIGA;
736 break;
737 case TRANSMITTER_UNIPHY_B:
738 enc10->base.preferred_engine = ENGINE_ID_DIGB;
739 break;
740 case TRANSMITTER_UNIPHY_C:
741 enc10->base.preferred_engine = ENGINE_ID_DIGC;
742 break;
743 case TRANSMITTER_UNIPHY_D:
744 enc10->base.preferred_engine = ENGINE_ID_DIGD;
745 break;
746 case TRANSMITTER_UNIPHY_E:
747 enc10->base.preferred_engine = ENGINE_ID_DIGE;
748 break;
749 case TRANSMITTER_UNIPHY_F:
750 enc10->base.preferred_engine = ENGINE_ID_DIGF;
751 break;
752 case TRANSMITTER_UNIPHY_G:
753 enc10->base.preferred_engine = ENGINE_ID_DIGG;
754 break;
755 default:
756 ASSERT_CRITICAL(false);
757 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
758 }
759
760 /* default to one to mirror Windows behavior */
761 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
762
763 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
764 enc10->base.id, &bp_cap_info);
765
766 /* Override features with DCE-specific values */
767 if (result == BP_RESULT_OK) {
768 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
769 bp_cap_info.DP_HBR2_EN;
770 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
771 bp_cap_info.DP_HBR3_EN;
772 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
773 enc10->base.features.flags.bits.DP_IS_USB_C =
774 bp_cap_info.DP_IS_USB_C;
775 } else {
776 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
777 __func__,
778 result);
779 }
780 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
781 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
782 }
783 }
784
785 bool dcn10_link_encoder_validate_output_with_stream(
786 struct link_encoder *enc,
787 const struct dc_stream_state *stream)
788 {
789 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
790 bool is_valid;
791
792 //if SCDC (340-600MHz) is disabled, set to HDMI 1.4 timing limit
793 if (stream->sink->edid_caps.panel_patch.skip_scdc_overwrite &&
794 enc10->base.features.max_hdmi_pixel_clock > 300000)
795 enc10->base.features.max_hdmi_pixel_clock = 300000;
796
797 switch (stream->signal) {
798 case SIGNAL_TYPE_DVI_SINGLE_LINK:
799 case SIGNAL_TYPE_DVI_DUAL_LINK:
800 is_valid = dcn10_link_encoder_validate_dvi_output(
801 enc10,
802 stream->link->connector_signal,
803 stream->signal,
804 &stream->timing);
805 break;
806 case SIGNAL_TYPE_HDMI_TYPE_A:
807 is_valid = dcn10_link_encoder_validate_hdmi_output(
808 enc10,
809 &stream->timing,
810 &stream->sink->edid_caps,
811 stream->phy_pix_clk * 10);
812 break;
813 case SIGNAL_TYPE_DISPLAY_PORT:
814 case SIGNAL_TYPE_DISPLAY_PORT_MST:
815 is_valid = dcn10_link_encoder_validate_dp_output(
816 enc10, &stream->timing);
817 break;
818 case SIGNAL_TYPE_EDP:
819 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
820 break;
821 case SIGNAL_TYPE_VIRTUAL:
822 is_valid = true;
823 break;
824 default:
825 is_valid = false;
826 break;
827 }
828
829 return is_valid;
830 }
831
832 void dcn10_link_encoder_hw_init(
833 struct link_encoder *enc)
834 {
835 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
836 struct bp_transmitter_control cntl = { 0 };
837 enum bp_result result;
838
839 cntl.action = TRANSMITTER_CONTROL_INIT;
840 cntl.engine_id = ENGINE_ID_UNKNOWN;
841 cntl.transmitter = enc10->base.transmitter;
842 cntl.connector_obj_id = enc10->base.connector;
843 cntl.lanes_number = LANE_COUNT_FOUR;
844 cntl.coherent = false;
845 cntl.hpd_sel = enc10->base.hpd_source;
846
847 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
848 cntl.signal = SIGNAL_TYPE_EDP;
849
850 result = link_transmitter_control(enc10, &cntl);
851
852 if (result != BP_RESULT_OK) {
853 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
854 __func__);
855 BREAK_TO_DEBUGGER();
856 return;
857 }
858
859 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
860 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
861
862 result = link_transmitter_control(enc10, &cntl);
863
864 ASSERT(result == BP_RESULT_OK);
865
866 }
867 dcn10_aux_initialize(enc10);
868
869 /* reinitialize HPD.
870 * hpd_initialize() will pass DIG_FE id to HW context.
871 * All other routine within HW context will use fe_engine_offset
872 * as DIG_FE id even caller pass DIG_FE id.
873 * So this routine must be called first.
874 */
875 hpd_initialize(enc10);
876 }
877
878 void dcn10_link_encoder_destroy(struct link_encoder **enc)
879 {
880 kfree(TO_DCN10_LINK_ENC(*enc));
881 *enc = NULL;
882 }
883
884 void dcn10_link_encoder_setup(
885 struct link_encoder *enc,
886 enum signal_type signal)
887 {
888 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
889
890 switch (signal) {
891 case SIGNAL_TYPE_EDP:
892 case SIGNAL_TYPE_DISPLAY_PORT:
893 /* DP SST */
894 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
895 break;
896 case SIGNAL_TYPE_LVDS:
897 /* LVDS */
898 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
899 break;
900 case SIGNAL_TYPE_DVI_SINGLE_LINK:
901 case SIGNAL_TYPE_DVI_DUAL_LINK:
902 /* TMDS-DVI */
903 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
904 break;
905 case SIGNAL_TYPE_HDMI_TYPE_A:
906 /* TMDS-HDMI */
907 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
908 break;
909 case SIGNAL_TYPE_DISPLAY_PORT_MST:
910 /* DP MST */
911 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
912 break;
913 default:
914 ASSERT_CRITICAL(false);
915 /* invalid mode ! */
916 break;
917 }
918
919 }
920
921 /* TODO: still need depth or just pass in adjusted pixel clock? */
922 void dcn10_link_encoder_enable_tmds_output(
923 struct link_encoder *enc,
924 enum clock_source_id clock_source,
925 enum dc_color_depth color_depth,
926 enum signal_type signal,
927 uint32_t pixel_clock)
928 {
929 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
930 struct bp_transmitter_control cntl = { 0 };
931 enum bp_result result;
932
933 /* Enable the PHY */
934
935 cntl.action = TRANSMITTER_CONTROL_ENABLE;
936 cntl.engine_id = enc->preferred_engine;
937 cntl.transmitter = enc10->base.transmitter;
938 cntl.pll_id = clock_source;
939 cntl.signal = signal;
940 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
941 cntl.lanes_number = 8;
942 else
943 cntl.lanes_number = 4;
944
945 cntl.hpd_sel = enc10->base.hpd_source;
946
947 cntl.pixel_clock = pixel_clock;
948 cntl.color_depth = color_depth;
949
950 result = link_transmitter_control(enc10, &cntl);
951
952 if (result != BP_RESULT_OK) {
953 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
954 __func__);
955 BREAK_TO_DEBUGGER();
956 }
957 }
958
959 /* enables DP PHY output */
960 void dcn10_link_encoder_enable_dp_output(
961 struct link_encoder *enc,
962 const struct dc_link_settings *link_settings,
963 enum clock_source_id clock_source)
964 {
965 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
966 struct bp_transmitter_control cntl = { 0 };
967 enum bp_result result;
968
969 /* Enable the PHY */
970
971 /* number_of_lanes is used for pixel clock adjust,
972 * but it's not passed to asic_control.
973 * We need to set number of lanes manually.
974 */
975 enc1_configure_encoder(enc10, link_settings);
976
977 cntl.action = TRANSMITTER_CONTROL_ENABLE;
978 cntl.engine_id = enc->preferred_engine;
979 cntl.transmitter = enc10->base.transmitter;
980 cntl.pll_id = clock_source;
981 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
982 cntl.lanes_number = link_settings->lane_count;
983 cntl.hpd_sel = enc10->base.hpd_source;
984 cntl.pixel_clock = link_settings->link_rate
985 * LINK_RATE_REF_FREQ_IN_KHZ;
986 /* TODO: check if undefined works */
987 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
988
989 result = link_transmitter_control(enc10, &cntl);
990
991 if (result != BP_RESULT_OK) {
992 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
993 __func__);
994 BREAK_TO_DEBUGGER();
995 }
996 }
997
998 /* enables DP PHY output in MST mode */
999 void dcn10_link_encoder_enable_dp_mst_output(
1000 struct link_encoder *enc,
1001 const struct dc_link_settings *link_settings,
1002 enum clock_source_id clock_source)
1003 {
1004 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1005 struct bp_transmitter_control cntl = { 0 };
1006 enum bp_result result;
1007
1008 /* Enable the PHY */
1009
1010 /* number_of_lanes is used for pixel clock adjust,
1011 * but it's not passed to asic_control.
1012 * We need to set number of lanes manually.
1013 */
1014 enc1_configure_encoder(enc10, link_settings);
1015
1016 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1017 cntl.engine_id = ENGINE_ID_UNKNOWN;
1018 cntl.transmitter = enc10->base.transmitter;
1019 cntl.pll_id = clock_source;
1020 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1021 cntl.lanes_number = link_settings->lane_count;
1022 cntl.hpd_sel = enc10->base.hpd_source;
1023 cntl.pixel_clock = link_settings->link_rate
1024 * LINK_RATE_REF_FREQ_IN_KHZ;
1025 /* TODO: check if undefined works */
1026 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1027
1028 result = link_transmitter_control(enc10, &cntl);
1029
1030 if (result != BP_RESULT_OK) {
1031 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1032 __func__);
1033 BREAK_TO_DEBUGGER();
1034 }
1035 }
1036 /*
1037 * @brief
1038 * Disable transmitter and its encoder
1039 */
1040 void dcn10_link_encoder_disable_output(
1041 struct link_encoder *enc,
1042 enum signal_type signal)
1043 {
1044 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1045 struct bp_transmitter_control cntl = { 0 };
1046 enum bp_result result;
1047
1048 if (!dcn10_is_dig_enabled(enc)) {
1049 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1050 /*in DP_Alt_No_Connect case, we turn off the dig already,
1051 after excuation the PHY w/a sequence, not allow touch PHY any more*/
1052 return;
1053 }
1054 /* Power-down RX and disable GPU PHY should be paired.
1055 * Disabling PHY without powering down RX may cause
1056 * symbol lock loss, on which we will get DP Sink interrupt.
1057 */
1058
1059 /* There is a case for the DP active dongles
1060 * where we want to disable the PHY but keep RX powered,
1061 * for those we need to ignore DP Sink interrupt
1062 * by checking lane count that has been set
1063 * on the last do_enable_output().
1064 */
1065
1066 /* disable transmitter */
1067 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1068 cntl.transmitter = enc10->base.transmitter;
1069 cntl.hpd_sel = enc10->base.hpd_source;
1070 cntl.signal = signal;
1071 cntl.connector_obj_id = enc10->base.connector;
1072
1073 result = link_transmitter_control(enc10, &cntl);
1074
1075 if (result != BP_RESULT_OK) {
1076 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1077 __func__);
1078 BREAK_TO_DEBUGGER();
1079 return;
1080 }
1081
1082 /* disable encoder */
1083 if (dc_is_dp_signal(signal))
1084 link_encoder_disable(enc10);
1085 }
1086
1087 void dcn10_link_encoder_dp_set_lane_settings(
1088 struct link_encoder *enc,
1089 const struct link_training_settings *link_settings)
1090 {
1091 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1092 union dpcd_training_lane_set training_lane_set = { { 0 } };
1093 int32_t lane = 0;
1094 struct bp_transmitter_control cntl = { 0 };
1095
1096 if (!link_settings) {
1097 BREAK_TO_DEBUGGER();
1098 return;
1099 }
1100
1101 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1102 cntl.transmitter = enc10->base.transmitter;
1103 cntl.connector_obj_id = enc10->base.connector;
1104 cntl.lanes_number = link_settings->link_settings.lane_count;
1105 cntl.hpd_sel = enc10->base.hpd_source;
1106 cntl.pixel_clock = link_settings->link_settings.link_rate *
1107 LINK_RATE_REF_FREQ_IN_KHZ;
1108
1109 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1110 /* translate lane settings */
1111
1112 training_lane_set.bits.VOLTAGE_SWING_SET =
1113 link_settings->lane_settings[lane].VOLTAGE_SWING;
1114 training_lane_set.bits.PRE_EMPHASIS_SET =
1115 link_settings->lane_settings[lane].PRE_EMPHASIS;
1116
1117 /* post cursor 2 setting only applies to HBR2 link rate */
1118 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1119 /* this is passed to VBIOS
1120 * to program post cursor 2 level
1121 */
1122 training_lane_set.bits.POST_CURSOR2_SET =
1123 link_settings->lane_settings[lane].POST_CURSOR2;
1124 }
1125
1126 cntl.lane_select = lane;
1127 cntl.lane_settings = training_lane_set.raw;
1128
1129 /* call VBIOS table to set voltage swing and pre-emphasis */
1130 link_transmitter_control(enc10, &cntl);
1131 }
1132 }
1133
1134 /* set DP PHY test and training patterns */
1135 void dcn10_link_encoder_dp_set_phy_pattern(
1136 struct link_encoder *enc,
1137 const struct encoder_set_dp_phy_pattern_param *param)
1138 {
1139 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1140
1141 switch (param->dp_phy_pattern) {
1142 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1143 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1144 break;
1145 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1146 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1147 break;
1148 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1149 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1150 break;
1151 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1152 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1153 break;
1154 case DP_TEST_PATTERN_D102:
1155 set_dp_phy_pattern_d102(enc10);
1156 break;
1157 case DP_TEST_PATTERN_SYMBOL_ERROR:
1158 set_dp_phy_pattern_symbol_error(enc10);
1159 break;
1160 case DP_TEST_PATTERN_PRBS7:
1161 set_dp_phy_pattern_prbs7(enc10);
1162 break;
1163 case DP_TEST_PATTERN_80BIT_CUSTOM:
1164 set_dp_phy_pattern_80bit_custom(
1165 enc10, param->custom_pattern);
1166 break;
1167 case DP_TEST_PATTERN_CP2520_1:
1168 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
1169 break;
1170 case DP_TEST_PATTERN_CP2520_2:
1171 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
1172 break;
1173 case DP_TEST_PATTERN_CP2520_3:
1174 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
1175 break;
1176 case DP_TEST_PATTERN_VIDEO_MODE: {
1177 set_dp_phy_pattern_passthrough_mode(
1178 enc10, param->dp_panel_mode);
1179 break;
1180 }
1181
1182 default:
1183 /* invalid phy pattern */
1184 ASSERT_CRITICAL(false);
1185 break;
1186 }
1187 }
1188
1189 static void fill_stream_allocation_row_info(
1190 const struct link_mst_stream_allocation *stream_allocation,
1191 uint32_t *src,
1192 uint32_t *slots)
1193 {
1194 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1195
1196 if (stream_enc) {
1197 *src = stream_enc->id;
1198 *slots = stream_allocation->slot_count;
1199 } else {
1200 *src = 0;
1201 *slots = 0;
1202 }
1203 }
1204
1205 /* programs DP MST VC payload allocation */
1206 void dcn10_link_encoder_update_mst_stream_allocation_table(
1207 struct link_encoder *enc,
1208 const struct link_mst_stream_allocation_table *table)
1209 {
1210 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1211 uint32_t value0 = 0;
1212 uint32_t value1 = 0;
1213 uint32_t value2 = 0;
1214 uint32_t slots = 0;
1215 uint32_t src = 0;
1216 uint32_t retries = 0;
1217
1218 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1219
1220 /* --- Set MSE Stream Attribute -
1221 * Setup VC Payload Table on Tx Side,
1222 * Issue allocation change trigger
1223 * to commit payload on both tx and rx side
1224 */
1225
1226 /* we should clean-up table each time */
1227
1228 if (table->stream_count >= 1) {
1229 fill_stream_allocation_row_info(
1230 &table->stream_allocations[0],
1231 &src,
1232 &slots);
1233 } else {
1234 src = 0;
1235 slots = 0;
1236 }
1237
1238 REG_UPDATE_2(DP_MSE_SAT0,
1239 DP_MSE_SAT_SRC0, src,
1240 DP_MSE_SAT_SLOT_COUNT0, slots);
1241
1242 if (table->stream_count >= 2) {
1243 fill_stream_allocation_row_info(
1244 &table->stream_allocations[1],
1245 &src,
1246 &slots);
1247 } else {
1248 src = 0;
1249 slots = 0;
1250 }
1251
1252 REG_UPDATE_2(DP_MSE_SAT0,
1253 DP_MSE_SAT_SRC1, src,
1254 DP_MSE_SAT_SLOT_COUNT1, slots);
1255
1256 if (table->stream_count >= 3) {
1257 fill_stream_allocation_row_info(
1258 &table->stream_allocations[2],
1259 &src,
1260 &slots);
1261 } else {
1262 src = 0;
1263 slots = 0;
1264 }
1265
1266 REG_UPDATE_2(DP_MSE_SAT1,
1267 DP_MSE_SAT_SRC2, src,
1268 DP_MSE_SAT_SLOT_COUNT2, slots);
1269
1270 if (table->stream_count >= 4) {
1271 fill_stream_allocation_row_info(
1272 &table->stream_allocations[3],
1273 &src,
1274 &slots);
1275 } else {
1276 src = 0;
1277 slots = 0;
1278 }
1279
1280 REG_UPDATE_2(DP_MSE_SAT1,
1281 DP_MSE_SAT_SRC3, src,
1282 DP_MSE_SAT_SLOT_COUNT3, slots);
1283
1284 /* --- wait for transaction finish */
1285
1286 /* send allocation change trigger (ACT) ?
1287 * this step first sends the ACT,
1288 * then double buffers the SAT into the hardware
1289 * making the new allocation active on the DP MST mode link
1290 */
1291
1292 /* DP_MSE_SAT_UPDATE:
1293 * 0 - No Action
1294 * 1 - Update SAT with trigger
1295 * 2 - Update SAT without trigger
1296 */
1297 REG_UPDATE(DP_MSE_SAT_UPDATE,
1298 DP_MSE_SAT_UPDATE, 1);
1299
1300 /* wait for update to complete
1301 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1302 * then wait for the transmission
1303 * of at least 16 MTP headers on immediate local link.
1304 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1305 * a value of 1 indicates that DP MST mode
1306 * is in the 16 MTP keepout region after a VC has been added.
1307 * MST stream bandwidth (VC rate) can be configured
1308 * after this bit is cleared
1309 */
1310 do {
1311 udelay(10);
1312
1313 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1314
1315 REG_GET(DP_MSE_SAT_UPDATE,
1316 DP_MSE_SAT_UPDATE, &value1);
1317
1318 REG_GET(DP_MSE_SAT_UPDATE,
1319 DP_MSE_16_MTP_KEEPOUT, &value2);
1320
1321 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1322 if (!value1 && !value2)
1323 break;
1324 ++retries;
1325 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1326 }
1327
1328 void dcn10_link_encoder_connect_dig_be_to_fe(
1329 struct link_encoder *enc,
1330 enum engine_id engine,
1331 bool connect)
1332 {
1333 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1334 uint32_t field;
1335
1336 if (engine != ENGINE_ID_UNKNOWN) {
1337
1338 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1339
1340 if (connect)
1341 field |= get_frontend_source(engine);
1342 else
1343 field &= ~get_frontend_source(engine);
1344
1345 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1346 }
1347 }
1348
1349
1350 #define HPD_REG(reg)\
1351 (enc10->hpd_regs->reg)
1352
1353 #define HPD_REG_READ(reg_name) \
1354 dm_read_reg(CTX, HPD_REG(reg_name))
1355
1356 #define HPD_REG_UPDATE_N(reg_name, n, ...) \
1357 generic_reg_update_ex(CTX, \
1358 HPD_REG(reg_name), \
1359 n, __VA_ARGS__)
1360
1361 #define HPD_REG_UPDATE(reg_name, field, val) \
1362 HPD_REG_UPDATE_N(reg_name, 1, \
1363 FN(reg_name, field), val)
1364
1365 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1366 {
1367 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1368
1369 HPD_REG_UPDATE(DC_HPD_CONTROL,
1370 DC_HPD_EN, 1);
1371 }
1372
1373 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1374 {
1375 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1376
1377 HPD_REG_UPDATE(DC_HPD_CONTROL,
1378 DC_HPD_EN, 0);
1379 }
1380
1381 #define AUX_REG(reg)\
1382 (enc10->aux_regs->reg)
1383
1384 #define AUX_REG_READ(reg_name) \
1385 dm_read_reg(CTX, AUX_REG(reg_name))
1386
1387 #define AUX_REG_UPDATE_N(reg_name, n, ...) \
1388 generic_reg_update_ex(CTX, \
1389 AUX_REG(reg_name), \
1390 n, __VA_ARGS__)
1391
1392 #define AUX_REG_UPDATE(reg_name, field, val) \
1393 AUX_REG_UPDATE_N(reg_name, 1, \
1394 FN(reg_name, field), val)
1395
1396 #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
1397 AUX_REG_UPDATE_N(reg, 2,\
1398 FN(reg, f1), v1,\
1399 FN(reg, f2), v2)
1400
1401 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
1402 {
1403 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1404
1405 AUX_REG_UPDATE_2(AUX_CONTROL,
1406 AUX_HPD_SEL, hpd_source,
1407 AUX_LS_READ_EN, 0);
1408
1409 /* 1/4 window (the maximum allowed) */
1410 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1411 AUX_RX_RECEIVE_WINDOW, 0);
1412 }
1413
1414 enum signal_type dcn10_get_dig_mode(
1415 struct link_encoder *enc)
1416 {
1417 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1418 uint32_t value;
1419 REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
1420 switch (value) {
1421 case 1:
1422 return SIGNAL_TYPE_DISPLAY_PORT;
1423 case 2:
1424 return SIGNAL_TYPE_DVI_SINGLE_LINK;
1425 case 3:
1426 return SIGNAL_TYPE_HDMI_TYPE_A;
1427 case 5:
1428 return SIGNAL_TYPE_DISPLAY_PORT_MST;
1429 default:
1430 return SIGNAL_TYPE_NONE;
1431 }
1432 return SIGNAL_TYPE_NONE;
1433 }
1434
1435 void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
1436 struct dc_link_settings *link_settings)
1437 {
1438 /* Set Default link settings */
1439 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1440 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
1441
1442 /* Higher link settings based on feature supported */
1443 if (enc->features.flags.bits.IS_HBR2_CAPABLE)
1444 max_link_cap.link_rate = LINK_RATE_HIGH2;
1445
1446 if (enc->features.flags.bits.IS_HBR3_CAPABLE)
1447 max_link_cap.link_rate = LINK_RATE_HIGH3;
1448
1449 *link_settings = max_link_cap;
1450 }
Linux with added FPC-III support