?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_optc.c
blobf033397a84e9a2eeb03ef3c320024ee641879e29
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28 #include "dcn10_optc.h"
29 #include "dc.h"
30
31 #define REG(reg)\
32 optc1->tg_regs->reg
33
34 #define CTX \
35 optc1->base.ctx
36
37 #undef FN
38 #define FN(reg_name, field_name) \
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
40
41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
42
43 /**
44 * apply_front_porch_workaround TODO FPGA still need?
45 *
46 * This is a workaround for a bug that has existed since R5xx and has not been
47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
48 */
49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
50 {
51 if (timing->flags.INTERLACE == 1) {
52 if (timing->v_front_porch < 2)
53 timing->v_front_porch = 2;
54 } else {
55 if (timing->v_front_porch < 1)
56 timing->v_front_porch = 1;
57 }
58 }
59
60 void optc1_program_global_sync(
61 struct timing_generator *optc,
62 int vready_offset,
63 int vstartup_start,
64 int vupdate_offset,
65 int vupdate_width)
66 {
67 struct optc *optc1 = DCN10TG_FROM_TG(optc);
68
69 optc1->vready_offset = vready_offset;
70 optc1->vstartup_start = vstartup_start;
71 optc1->vupdate_offset = vupdate_offset;
72 optc1->vupdate_width = vupdate_width;
73
74 if (optc1->vstartup_start == 0) {
75 BREAK_TO_DEBUGGER();
76 return;
77 }
78
79 REG_SET(OTG_VSTARTUP_PARAM, 0,
80 VSTARTUP_START, optc1->vstartup_start);
81
82 REG_SET_2(OTG_VUPDATE_PARAM, 0,
83 VUPDATE_OFFSET, optc1->vupdate_offset,
84 VUPDATE_WIDTH, optc1->vupdate_width);
85
86 REG_SET(OTG_VREADY_PARAM, 0,
87 VREADY_OFFSET, optc1->vready_offset);
88 }
89
90 static void optc1_disable_stereo(struct timing_generator *optc)
91 {
92 struct optc *optc1 = DCN10TG_FROM_TG(optc);
93
94 REG_SET(OTG_STEREO_CONTROL, 0,
95 OTG_STEREO_EN, 0);
96
97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
98 OTG_3D_STRUCTURE_EN, 0,
99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
100 }
101
102 void optc1_setup_vertical_interrupt0(
103 struct timing_generator *optc,
104 uint32_t start_line,
105 uint32_t end_line)
106 {
107 struct optc *optc1 = DCN10TG_FROM_TG(optc);
108
109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
112 }
113
114 void optc1_setup_vertical_interrupt1(
115 struct timing_generator *optc,
116 uint32_t start_line)
117 {
118 struct optc *optc1 = DCN10TG_FROM_TG(optc);
119
120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
122 }
123
124 void optc1_setup_vertical_interrupt2(
125 struct timing_generator *optc,
126 uint32_t start_line)
127 {
128 struct optc *optc1 = DCN10TG_FROM_TG(optc);
129
130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
132 }
133
134 /**
135 * program_timing_generator used by mode timing set
136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
137 * Including SYNC. Call BIOS command table to program Timings.
138 */
139 void optc1_program_timing(
140 struct timing_generator *optc,
141 const struct dc_crtc_timing *dc_crtc_timing,
142 int vready_offset,
143 int vstartup_start,
144 int vupdate_offset,
145 int vupdate_width,
146 const enum signal_type signal,
147 bool use_vbios)
148 {
149 struct dc_crtc_timing patched_crtc_timing;
150 uint32_t asic_blank_end;
151 uint32_t asic_blank_start;
152 uint32_t v_total;
153 uint32_t v_sync_end;
154 uint32_t h_sync_polarity, v_sync_polarity;
155 uint32_t start_point = 0;
156 uint32_t field_num = 0;
157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
158
159 struct optc *optc1 = DCN10TG_FROM_TG(optc);
160
161 optc1->signal = signal;
162 optc1->vready_offset = vready_offset;
163 optc1->vstartup_start = vstartup_start;
164 optc1->vupdate_offset = vupdate_offset;
165 optc1->vupdate_width = vupdate_width;
166 patched_crtc_timing = *dc_crtc_timing;
167 apply_front_porch_workaround(&patched_crtc_timing);
168
169 /* Load horizontal timing */
170
171 /* CRTC_H_TOTAL = vesa.h_total - 1 */
172 REG_SET(OTG_H_TOTAL, 0,
173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
174
175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
176 REG_UPDATE_2(OTG_H_SYNC_A,
177 OTG_H_SYNC_A_START, 0,
178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
179
180 /* blank_start = line end - front porch */
181 asic_blank_start = patched_crtc_timing.h_total -
182 patched_crtc_timing.h_front_porch;
183
184 /* blank_end = blank_start - active */
185 asic_blank_end = asic_blank_start -
186 patched_crtc_timing.h_border_right -
187 patched_crtc_timing.h_addressable -
188 patched_crtc_timing.h_border_left;
189
190 REG_UPDATE_2(OTG_H_BLANK_START_END,
191 OTG_H_BLANK_START, asic_blank_start,
192 OTG_H_BLANK_END, asic_blank_end);
193
194 /* h_sync polarity */
195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
196 0 : 1;
197
198 REG_UPDATE(OTG_H_SYNC_A_CNTL,
199 OTG_H_SYNC_A_POL, h_sync_polarity);
200
201 v_total = patched_crtc_timing.v_total - 1;
202
203 REG_SET(OTG_V_TOTAL, 0,
204 OTG_V_TOTAL, v_total);
205
206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
207 * OTG_V_TOTAL_MIN are equal to V_TOTAL.
208 */
209 REG_SET(OTG_V_TOTAL_MAX, 0,
210 OTG_V_TOTAL_MAX, v_total);
211 REG_SET(OTG_V_TOTAL_MIN, 0,
212 OTG_V_TOTAL_MIN, v_total);
213
214 /* v_sync_start = 0, v_sync_end = v_sync_width */
215 v_sync_end = patched_crtc_timing.v_sync_width;
216
217 REG_UPDATE_2(OTG_V_SYNC_A,
218 OTG_V_SYNC_A_START, 0,
219 OTG_V_SYNC_A_END, v_sync_end);
220
221 /* blank_start = frame end - front porch */
222 asic_blank_start = patched_crtc_timing.v_total -
223 patched_crtc_timing.v_front_porch;
224
225 /* blank_end = blank_start - active */
226 asic_blank_end = asic_blank_start -
227 patched_crtc_timing.v_border_bottom -
228 patched_crtc_timing.v_addressable -
229 patched_crtc_timing.v_border_top;
230
231 REG_UPDATE_2(OTG_V_BLANK_START_END,
232 OTG_V_BLANK_START, asic_blank_start,
233 OTG_V_BLANK_END, asic_blank_end);
234
235 /* v_sync polarity */
236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
237 0 : 1;
238
239 REG_UPDATE(OTG_V_SYNC_A_CNTL,
240 OTG_V_SYNC_A_POL, v_sync_polarity);
241
242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
244 optc1->signal == SIGNAL_TYPE_EDP) {
245 start_point = 1;
246 if (patched_crtc_timing.flags.INTERLACE == 1)
247 field_num = 1;
248 }
249
250 /* Interlace */
251 if (REG(OTG_INTERLACE_CONTROL)) {
252 if (patched_crtc_timing.flags.INTERLACE == 1)
253 REG_UPDATE(OTG_INTERLACE_CONTROL,
254 OTG_INTERLACE_ENABLE, 1);
255 else
256 REG_UPDATE(OTG_INTERLACE_CONTROL,
257 OTG_INTERLACE_ENABLE, 0);
258 }
259
260 /* VTG enable set to 0 first VInit */
261 REG_UPDATE(CONTROL,
262 VTG0_ENABLE, 0);
263
264 /* original code is using VTG offset to address OTG reg, seems wrong */
265 REG_UPDATE_2(OTG_CONTROL,
266 OTG_START_POINT_CNTL, start_point,
267 OTG_FIELD_NUMBER_CNTL, field_num);
268
269 optc->funcs->program_global_sync(optc,
270 vready_offset,
271 vstartup_start,
272 vupdate_offset,
273 vupdate_width);
274
275 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);
276
277 /* TODO
278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
279 * program_horz_count_by_2
280 * for DVI 30bpp mode, 0 otherwise
281 * program_horz_count_by_2(optc, &patched_crtc_timing);
282 */
283
284 /* Enable stereo - only when we need to pack 3D frame. Other types
285 * of stereo handled in explicit call
286 */
287
288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
289 h_div = H_TIMING_DIV_BY2;
290
291 if (REG(OPTC_DATA_FORMAT_CONTROL)) {
292 uint32_t data_fmt = 0;
293
294 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
295 data_fmt = 1;
296 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
297 data_fmt = 2;
298
299 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
300 }
301
302 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
303 if (optc1->opp_count == 4)
304 h_div = H_TIMING_DIV_BY4;
305
306 REG_UPDATE(OTG_H_TIMING_CNTL,
307 OTG_H_TIMING_DIV_MODE, h_div);
308 } else {
309 REG_UPDATE(OTG_H_TIMING_CNTL,
310 OTG_H_TIMING_DIV_BY2, h_div);
311 }
312 }
313
314 void optc1_set_vtg_params(struct timing_generator *optc,
315 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
316 {
317 struct dc_crtc_timing patched_crtc_timing;
318 uint32_t asic_blank_end;
319 uint32_t v_init;
320 uint32_t v_fp2 = 0;
321 int32_t vertical_line_start;
322
323 struct optc *optc1 = DCN10TG_FROM_TG(optc);
324
325 patched_crtc_timing = *dc_crtc_timing;
326 apply_front_porch_workaround(&patched_crtc_timing);
327
328 /* VCOUNT_INIT is the start of blank */
329 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
330
331 /* end of blank = v_init - active */
332 asic_blank_end = v_init -
333 patched_crtc_timing.v_border_bottom -
334 patched_crtc_timing.v_addressable -
335 patched_crtc_timing.v_border_top;
336
337 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
338 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
339 if (vertical_line_start < 0)
340 v_fp2 = -vertical_line_start;
341
342 /* Interlace */
343 if (REG(OTG_INTERLACE_CONTROL)) {
344 if (patched_crtc_timing.flags.INTERLACE == 1) {
345 v_init = v_init / 2;
346 if ((optc1->vstartup_start/2)*2 > asic_blank_end)
347 v_fp2 = v_fp2 / 2;
348 }
349 }
350
351 if (program_fp2)
352 REG_UPDATE_2(CONTROL,
353 VTG0_FP2, v_fp2,
354 VTG0_VCOUNT_INIT, v_init);
355 else
356 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);
357 }
358
359 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
360 {
361 struct optc *optc1 = DCN10TG_FROM_TG(optc);
362
363 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
364
365 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
366 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
367 }
368
369 /**
370 * optc1_set_timing_double_buffer() - DRR double buffering control
371 *
372 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
373 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
374 *
375 * Options: any time, start of frame, dp start of frame (range timing)
376 */
377 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
378 {
379 struct optc *optc1 = DCN10TG_FROM_TG(optc);
380 uint32_t mode = enable ? 2 : 0;
381
382 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
383 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
384 }
385
386 /**
387 * unblank_crtc
388 * Call ASIC Control Object to UnBlank CRTC.
389 */
390 static void optc1_unblank_crtc(struct timing_generator *optc)
391 {
392 struct optc *optc1 = DCN10TG_FROM_TG(optc);
393
394 REG_UPDATE_2(OTG_BLANK_CONTROL,
395 OTG_BLANK_DATA_EN, 0,
396 OTG_BLANK_DE_MODE, 0);
397
398 /* W/A for automated testing
399 * Automated testing will fail underflow test as there
400 * sporadic underflows which occur during the optc blank
401 * sequence. As a w/a, clear underflow on unblank.
402 * This prevents the failure, but will not mask actual
403 * underflow that affect real use cases.
404 */
405 optc1_clear_optc_underflow(optc);
406 }
407
408 /**
409 * blank_crtc
410 * Call ASIC Control Object to Blank CRTC.
411 */
412
413 static void optc1_blank_crtc(struct timing_generator *optc)
414 {
415 struct optc *optc1 = DCN10TG_FROM_TG(optc);
416
417 REG_UPDATE_2(OTG_BLANK_CONTROL,
418 OTG_BLANK_DATA_EN, 1,
419 OTG_BLANK_DE_MODE, 0);
420
421 optc1_set_blank_data_double_buffer(optc, false);
422 }
423
424 void optc1_set_blank(struct timing_generator *optc,
425 bool enable_blanking)
426 {
427 if (enable_blanking)
428 optc1_blank_crtc(optc);
429 else
430 optc1_unblank_crtc(optc);
431 }
432
433 bool optc1_is_blanked(struct timing_generator *optc)
434 {
435 struct optc *optc1 = DCN10TG_FROM_TG(optc);
436 uint32_t blank_en;
437 uint32_t blank_state;
438
439 REG_GET_2(OTG_BLANK_CONTROL,
440 OTG_BLANK_DATA_EN, &blank_en,
441 OTG_CURRENT_BLANK_STATE, &blank_state);
442
443 return blank_en && blank_state;
444 }
445
446 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
447 {
448 struct optc *optc1 = DCN10TG_FROM_TG(optc);
449
450 if (enable) {
451 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
452 OPTC_INPUT_CLK_EN, 1,
453 OPTC_INPUT_CLK_GATE_DIS, 1);
454
455 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
456 OPTC_INPUT_CLK_ON, 1,
457 1, 1000);
458
459 /* Enable clock */
460 REG_UPDATE_2(OTG_CLOCK_CONTROL,
461 OTG_CLOCK_EN, 1,
462 OTG_CLOCK_GATE_DIS, 1);
463 REG_WAIT(OTG_CLOCK_CONTROL,
464 OTG_CLOCK_ON, 1,
465 1, 1000);
466 } else {
467 REG_UPDATE_2(OTG_CLOCK_CONTROL,
468 OTG_CLOCK_GATE_DIS, 0,
469 OTG_CLOCK_EN, 0);
470
471 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
472 OPTC_INPUT_CLK_GATE_DIS, 0,
473 OPTC_INPUT_CLK_EN, 0);
474 }
475 }
476
477 /**
478 * Enable CRTC
479 * Enable CRTC - call ASIC Control Object to enable Timing generator.
480 */
481 static bool optc1_enable_crtc(struct timing_generator *optc)
482 {
483 /* TODO FPGA wait for answer
484 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
485 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
486 */
487 struct optc *optc1 = DCN10TG_FROM_TG(optc);
488
489 /* opp instance for OTG. For DCN1.0, ODM is remoed.
490 * OPP and OPTC should 1:1 mapping
491 */
492 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
493 OPTC_SRC_SEL, optc->inst);
494
495 /* VTG enable first is for HW workaround */
496 REG_UPDATE(CONTROL,
497 VTG0_ENABLE, 1);
498
499 REG_SEQ_START();
500
501 /* Enable CRTC */
502 REG_UPDATE_2(OTG_CONTROL,
503 OTG_DISABLE_POINT_CNTL, 3,
504 OTG_MASTER_EN, 1);
505
506 REG_SEQ_SUBMIT();
507 REG_SEQ_WAIT_DONE();
508
509 return true;
510 }
511
512 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
513 bool optc1_disable_crtc(struct timing_generator *optc)
514 {
515 struct optc *optc1 = DCN10TG_FROM_TG(optc);
516
517 /* disable otg request until end of the first line
518 * in the vertical blank region
519 */
520 REG_UPDATE_2(OTG_CONTROL,
521 OTG_DISABLE_POINT_CNTL, 3,
522 OTG_MASTER_EN, 0);
523
524 REG_UPDATE(CONTROL,
525 VTG0_ENABLE, 0);
526
527 /* CRTC disabled, so disable clock. */
528 REG_WAIT(OTG_CLOCK_CONTROL,
529 OTG_BUSY, 0,
530 1, 100000);
531
532 return true;
533 }
534
535
536 void optc1_program_blank_color(
537 struct timing_generator *optc,
538 const struct tg_color *black_color)
539 {
540 struct optc *optc1 = DCN10TG_FROM_TG(optc);
541
542 REG_SET_3(OTG_BLACK_COLOR, 0,
543 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
544 OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
545 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
546 }
547
548 bool optc1_validate_timing(
549 struct timing_generator *optc,
550 const struct dc_crtc_timing *timing)
551 {
552 uint32_t v_blank;
553 uint32_t h_blank;
554 uint32_t min_v_blank;
555 struct optc *optc1 = DCN10TG_FROM_TG(optc);
556
557 ASSERT(timing != NULL);
558
559 v_blank = (timing->v_total - timing->v_addressable -
560 timing->v_border_top - timing->v_border_bottom);
561
562 h_blank = (timing->h_total - timing->h_addressable -
563 timing->h_border_right -
564 timing->h_border_left);
565
566 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
567 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
568 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
569 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
570 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
571 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
572 return false;
573
574 /* Temporarily blocking interlacing mode until it's supported */
575 if (timing->flags.INTERLACE == 1)
576 return false;
577
578 /* Check maximum number of pixels supported by Timing Generator
579 * (Currently will never fail, in order to fail needs display which
580 * needs more than 8192 horizontal and
581 * more than 8192 vertical total pixels)
582 */
583 if (timing->h_total > optc1->max_h_total ||
584 timing->v_total > optc1->max_v_total)
585 return false;
586
587
588 if (h_blank < optc1->min_h_blank)
589 return false;
590
591 if (timing->h_sync_width < optc1->min_h_sync_width ||
592 timing->v_sync_width < optc1->min_v_sync_width)
593 return false;
594
595 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
596
597 if (v_blank < min_v_blank)
598 return false;
599
600 return true;
601
602 }
603
604 /*
605 * get_vblank_counter
606 *
607 * @brief
608 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
609 * holds the counter of frames.
610 *
611 * @param
612 * struct timing_generator *optc - [in] timing generator which controls the
613 * desired CRTC
614 *
615 * @return
616 * Counter of frames, which should equal to number of vblanks.
617 */
618 uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
619 {
620 struct optc *optc1 = DCN10TG_FROM_TG(optc);
621 uint32_t frame_count;
622
623 REG_GET(OTG_STATUS_FRAME_COUNT,
624 OTG_FRAME_COUNT, &frame_count);
625
626 return frame_count;
627 }
628
629 void optc1_lock(struct timing_generator *optc)
630 {
631 struct optc *optc1 = DCN10TG_FROM_TG(optc);
632 uint32_t regval = 0;
633
634 regval = REG_READ(OTG_CONTROL);
635
636 /* otg is not running, do not need to be locked */
637 if ((regval & 0x1) == 0x0)
638 return;
639
640 REG_SET(OTG_GLOBAL_CONTROL0, 0,
641 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
642 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
643 OTG_MASTER_UPDATE_LOCK, 1);
644
645 /* Should be fast, status does not update on maximus */
646 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
647
648 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
649 UPDATE_LOCK_STATUS, 1,
650 1, 10);
651 }
652 }
653
654 void optc1_unlock(struct timing_generator *optc)
655 {
656 struct optc *optc1 = DCN10TG_FROM_TG(optc);
657
658 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
659 OTG_MASTER_UPDATE_LOCK, 0);
660 }
661
662 void optc1_get_position(struct timing_generator *optc,
663 struct crtc_position *position)
664 {
665 struct optc *optc1 = DCN10TG_FROM_TG(optc);
666
667 REG_GET_2(OTG_STATUS_POSITION,
668 OTG_HORZ_COUNT, &position->horizontal_count,
669 OTG_VERT_COUNT, &position->vertical_count);
670
671 REG_GET(OTG_NOM_VERT_POSITION,
672 OTG_VERT_COUNT_NOM, &position->nominal_vcount);
673 }
674
675 bool optc1_is_counter_moving(struct timing_generator *optc)
676 {
677 struct crtc_position position1, position2;
678
679 optc->funcs->get_position(optc, &position1);
680 optc->funcs->get_position(optc, &position2);
681
682 if (position1.horizontal_count == position2.horizontal_count &&
683 position1.vertical_count == position2.vertical_count)
684 return false;
685 else
686 return true;
687 }
688
689 bool optc1_did_triggered_reset_occur(
690 struct timing_generator *optc)
691 {
692 struct optc *optc1 = DCN10TG_FROM_TG(optc);
693 uint32_t occurred_force, occurred_vsync;
694
695 REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
696 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
697
698 REG_GET(OTG_VERT_SYNC_CONTROL,
699 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
700
701 return occurred_vsync != 0 || occurred_force != 0;
702 }
703
704 void optc1_disable_reset_trigger(struct timing_generator *optc)
705 {
706 struct optc *optc1 = DCN10TG_FROM_TG(optc);
707
708 REG_WRITE(OTG_TRIGA_CNTL, 0);
709
710 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
711 OTG_FORCE_COUNT_NOW_CLEAR, 1);
712
713 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
714 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
715 }
716
717 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
718 {
719 struct optc *optc1 = DCN10TG_FROM_TG(optc);
720 uint32_t falling_edge;
721
722 REG_GET(OTG_V_SYNC_A_CNTL,
723 OTG_V_SYNC_A_POL, &falling_edge);
724
725 if (falling_edge)
726 REG_SET_3(OTG_TRIGA_CNTL, 0,
727 /* vsync signal from selected OTG pipe based
728 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
729 */
730 OTG_TRIGA_SOURCE_SELECT, 20,
731 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
732 /* always detect falling edge */
733 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
734 else
735 REG_SET_3(OTG_TRIGA_CNTL, 0,
736 /* vsync signal from selected OTG pipe based
737 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
738 */
739 OTG_TRIGA_SOURCE_SELECT, 20,
740 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
741 /* always detect rising edge */
742 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
743
744 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
745 /* force H count to H_TOTAL and V count to V_TOTAL in
746 * progressive mode and V_TOTAL-1 in interlaced mode
747 */
748 OTG_FORCE_COUNT_NOW_MODE, 2);
749 }
750
751 void optc1_enable_crtc_reset(
752 struct timing_generator *optc,
753 int source_tg_inst,
754 struct crtc_trigger_info *crtc_tp)
755 {
756 struct optc *optc1 = DCN10TG_FROM_TG(optc);
757 uint32_t falling_edge = 0;
758 uint32_t rising_edge = 0;
759
760 switch (crtc_tp->event) {
761
762 case CRTC_EVENT_VSYNC_RISING:
763 rising_edge = 1;
764 break;
765
766 case CRTC_EVENT_VSYNC_FALLING:
767 falling_edge = 1;
768 break;
769 }
770
771 REG_SET_4(OTG_TRIGA_CNTL, 0,
772 /* vsync signal from selected OTG pipe based
773 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
774 */
775 OTG_TRIGA_SOURCE_SELECT, 20,
776 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
777 /* always detect falling edge */
778 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
779 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
780
781 switch (crtc_tp->delay) {
782 case TRIGGER_DELAY_NEXT_LINE:
783 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
784 OTG_AUTO_FORCE_VSYNC_MODE, 1);
785 break;
786 case TRIGGER_DELAY_NEXT_PIXEL:
787 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
788 /* force H count to H_TOTAL and V count to V_TOTAL in
789 * progressive mode and V_TOTAL-1 in interlaced mode
790 */
791 OTG_FORCE_COUNT_NOW_MODE, 2);
792 break;
793 }
794 }
795
796 void optc1_wait_for_state(struct timing_generator *optc,
797 enum crtc_state state)
798 {
799 struct optc *optc1 = DCN10TG_FROM_TG(optc);
800
801 switch (state) {
802 case CRTC_STATE_VBLANK:
803 REG_WAIT(OTG_STATUS,
804 OTG_V_BLANK, 1,
805 1, 100000); /* 1 vupdate at 10hz */
806 break;
807
808 case CRTC_STATE_VACTIVE:
809 REG_WAIT(OTG_STATUS,
810 OTG_V_ACTIVE_DISP, 1,
811 1, 100000); /* 1 vupdate at 10hz */
812 break;
813
814 default:
815 break;
816 }
817 }
818
819 void optc1_set_early_control(
820 struct timing_generator *optc,
821 uint32_t early_cntl)
822 {
823 /* asic design change, do not need this control
824 * empty for share caller logic
825 */
826 }
827
828
829 void optc1_set_static_screen_control(
830 struct timing_generator *optc,
831 uint32_t event_triggers,
832 uint32_t num_frames)
833 {
834 struct optc *optc1 = DCN10TG_FROM_TG(optc);
835
836 // By register spec, it only takes 8 bit value
837 if (num_frames > 0xFF)
838 num_frames = 0xFF;
839
840 /* Bit 8 is no longer applicable in RV for PSR case,
841 * set bit 8 to 0 if given
842 */
843 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
844 != 0)
845 event_triggers = event_triggers &
846 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
847
848 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
849 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
850 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
851 }
852
853 void optc1_setup_manual_trigger(struct timing_generator *optc)
854 {
855 struct optc *optc1 = DCN10TG_FROM_TG(optc);
856
857 REG_SET(OTG_GLOBAL_CONTROL2, 0,
858 MANUAL_FLOW_CONTROL_SEL, optc->inst);
859
860 REG_SET_8(OTG_TRIGA_CNTL, 0,
861 OTG_TRIGA_SOURCE_SELECT, 22,
862 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
863 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
864 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
865 OTG_TRIGA_POLARITY_SELECT, 0,
866 OTG_TRIGA_FREQUENCY_SELECT, 0,
867 OTG_TRIGA_DELAY, 0,
868 OTG_TRIGA_CLEAR, 1);
869 }
870
871 void optc1_program_manual_trigger(struct timing_generator *optc)
872 {
873 struct optc *optc1 = DCN10TG_FROM_TG(optc);
874
875 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
876 MANUAL_FLOW_CONTROL, 1);
877
878 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
879 MANUAL_FLOW_CONTROL, 0);
880 }
881
882
883 /**
884 *****************************************************************************
885 * Function: set_drr
886 *
887 * @brief
888 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
889 *
890 *****************************************************************************
891 */
892 void optc1_set_drr(
893 struct timing_generator *optc,
894 const struct drr_params *params)
895 {
896 struct optc *optc1 = DCN10TG_FROM_TG(optc);
897
898 if (params != NULL &&
899 params->vertical_total_max > 0 &&
900 params->vertical_total_min > 0) {
901
902 if (params->vertical_total_mid != 0) {
903
904 REG_SET(OTG_V_TOTAL_MID, 0,
905 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
906
907 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
908 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
909 OTG_VTOTAL_MID_FRAME_NUM,
910 (uint8_t)params->vertical_total_mid_frame_num);
911
912 }
913
914 REG_SET(OTG_V_TOTAL_MAX, 0,
915 OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
916
917 REG_SET(OTG_V_TOTAL_MIN, 0,
918 OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
919
920 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
921 OTG_V_TOTAL_MIN_SEL, 1,
922 OTG_V_TOTAL_MAX_SEL, 1,
923 OTG_FORCE_LOCK_ON_EVENT, 0,
924 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
925 OTG_SET_V_TOTAL_MIN_MASK, 0);
926
927 // Setup manual flow control for EOF via TRIG_A
928 optc->funcs->setup_manual_trigger(optc);
929
930 } else {
931 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
932 OTG_SET_V_TOTAL_MIN_MASK, 0,
933 OTG_V_TOTAL_MIN_SEL, 0,
934 OTG_V_TOTAL_MAX_SEL, 0,
935 OTG_FORCE_LOCK_ON_EVENT, 0);
936
937 REG_SET(OTG_V_TOTAL_MIN, 0,
938 OTG_V_TOTAL_MIN, 0);
939
940 REG_SET(OTG_V_TOTAL_MAX, 0,
941 OTG_V_TOTAL_MAX, 0);
942 }
943 }
944
945 static void optc1_set_test_pattern(
946 struct timing_generator *optc,
947 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
948 * because this is not DP-specific (which is probably somewhere in DP
949 * encoder) */
950 enum controller_dp_test_pattern test_pattern,
951 enum dc_color_depth color_depth)
952 {
953 struct optc *optc1 = DCN10TG_FROM_TG(optc);
954 enum test_pattern_color_format bit_depth;
955 enum test_pattern_dyn_range dyn_range;
956 enum test_pattern_mode mode;
957 uint32_t pattern_mask;
958 uint32_t pattern_data;
959 /* color ramp generator mixes 16-bits color */
960 uint32_t src_bpc = 16;
961 /* requested bpc */
962 uint32_t dst_bpc;
963 uint32_t index;
964 /* RGB values of the color bars.
965 * Produce two RGB colors: RGB0 - white (all Fs)
966 * and RGB1 - black (all 0s)
967 * (three RGB components for two colors)
968 */
969 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
970 0x0000, 0x0000};
971 /* dest color (converted to the specified color format) */
972 uint16_t dst_color[6];
973 uint32_t inc_base;
974
975 /* translate to bit depth */
976 switch (color_depth) {
977 case COLOR_DEPTH_666:
978 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
979 break;
980 case COLOR_DEPTH_888:
981 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
982 break;
983 case COLOR_DEPTH_101010:
984 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
985 break;
986 case COLOR_DEPTH_121212:
987 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
988 break;
989 default:
990 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
991 break;
992 }
993
994 switch (test_pattern) {
995 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
996 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
997 {
998 dyn_range = (test_pattern ==
999 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
1000 TEST_PATTERN_DYN_RANGE_CEA :
1001 TEST_PATTERN_DYN_RANGE_VESA);
1002 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
1003
1004 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
1005 OTG_TEST_PATTERN_VRES, 6,
1006 OTG_TEST_PATTERN_HRES, 6);
1007
1008 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1009 OTG_TEST_PATTERN_EN, 1,
1010 OTG_TEST_PATTERN_MODE, mode,
1011 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
1012 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1013 }
1014 break;
1015
1016 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
1017 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
1018 {
1019 mode = (test_pattern ==
1020 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
1021 TEST_PATTERN_MODE_VERTICALBARS :
1022 TEST_PATTERN_MODE_HORIZONTALBARS);
1023
1024 switch (bit_depth) {
1025 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1026 dst_bpc = 6;
1027 break;
1028 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1029 dst_bpc = 8;
1030 break;
1031 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1032 dst_bpc = 10;
1033 break;
1034 default:
1035 dst_bpc = 8;
1036 break;
1037 }
1038
1039 /* adjust color to the required colorFormat */
1040 for (index = 0; index < 6; index++) {
1041 /* dst = 2^dstBpc * src / 2^srcBpc = src >>
1042 * (srcBpc - dstBpc);
1043 */
1044 dst_color[index] =
1045 src_color[index] >> (src_bpc - dst_bpc);
1046 /* CRTC_TEST_PATTERN_DATA has 16 bits,
1047 * lowest 6 are hardwired to ZERO
1048 * color bits should be left aligned aligned to MSB
1049 * XXXXXXXXXX000000 for 10 bit,
1050 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
1051 */
1052 dst_color[index] <<= (16 - dst_bpc);
1053 }
1054
1055 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1056
1057 /* We have to write the mask before data, similar to pipeline.
1058 * For example, for 8 bpc, if we want RGB0 to be magenta,
1059 * and RGB1 to be cyan,
1060 * we need to make 7 writes:
1061 * MASK DATA
1062 * 000001 00000000 00000000 set mask to R0
1063 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0
1064 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0
1065 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1
1066 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1
1067 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1
1068 * 100000 11111111 00000000 B1 255, 0xFF00
1069 *
1070 * we will make a loop of 6 in which we prepare the mask,
1071 * then write, then prepare the color for next write.
1072 * first iteration will write mask only,
1073 * but each next iteration color prepared in
1074 * previous iteration will be written within new mask,
1075 * the last component will written separately,
1076 * mask is not changing between 6th and 7th write
1077 * and color will be prepared by last iteration
1078 */
1079
1080 /* write color, color values mask in CRTC_TEST_PATTERN_MASK
1081 * is B1, G1, R1, B0, G0, R0
1082 */
1083 pattern_data = 0;
1084 for (index = 0; index < 6; index++) {
1085 /* prepare color mask, first write PATTERN_DATA
1086 * will have all zeros
1087 */
1088 pattern_mask = (1 << index);
1089
1090 /* write color component */
1091 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1092 OTG_TEST_PATTERN_MASK, pattern_mask,
1093 OTG_TEST_PATTERN_DATA, pattern_data);
1094
1095 /* prepare next color component,
1096 * will be written in the next iteration
1097 */
1098 pattern_data = dst_color[index];
1099 }
1100 /* write last color component,
1101 * it's been already prepared in the loop
1102 */
1103 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1104 OTG_TEST_PATTERN_MASK, pattern_mask,
1105 OTG_TEST_PATTERN_DATA, pattern_data);
1106
1107 /* enable test pattern */
1108 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1109 OTG_TEST_PATTERN_EN, 1,
1110 OTG_TEST_PATTERN_MODE, mode,
1111 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1112 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1113 }
1114 break;
1115
1116 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1117 {
1118 mode = (bit_depth ==
1119 TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1120 TEST_PATTERN_MODE_DUALRAMP_RGB :
1121 TEST_PATTERN_MODE_SINGLERAMP_RGB);
1122
1123 switch (bit_depth) {
1124 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1125 dst_bpc = 6;
1126 break;
1127 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1128 dst_bpc = 8;
1129 break;
1130 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1131 dst_bpc = 10;
1132 break;
1133 default:
1134 dst_bpc = 8;
1135 break;
1136 }
1137
1138 /* increment for the first ramp for one color gradation
1139 * 1 gradation for 6-bit color is 2^10
1140 * gradations in 16-bit color
1141 */
1142 inc_base = (src_bpc - dst_bpc);
1143
1144 switch (bit_depth) {
1145 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1146 {
1147 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1148 OTG_TEST_PATTERN_INC0, inc_base,
1149 OTG_TEST_PATTERN_INC1, 0,
1150 OTG_TEST_PATTERN_HRES, 6,
1151 OTG_TEST_PATTERN_VRES, 6,
1152 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1153 }
1154 break;
1155 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1156 {
1157 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1158 OTG_TEST_PATTERN_INC0, inc_base,
1159 OTG_TEST_PATTERN_INC1, 0,
1160 OTG_TEST_PATTERN_HRES, 8,
1161 OTG_TEST_PATTERN_VRES, 6,
1162 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1163 }
1164 break;
1165 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1166 {
1167 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1168 OTG_TEST_PATTERN_INC0, inc_base,
1169 OTG_TEST_PATTERN_INC1, inc_base + 2,
1170 OTG_TEST_PATTERN_HRES, 8,
1171 OTG_TEST_PATTERN_VRES, 5,
1172 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1173 }
1174 break;
1175 default:
1176 break;
1177 }
1178
1179 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1180
1181 /* enable test pattern */
1182 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1183
1184 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1185 OTG_TEST_PATTERN_EN, 1,
1186 OTG_TEST_PATTERN_MODE, mode,
1187 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1188 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1189 }
1190 break;
1191 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1192 {
1193 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1194 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1195 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1196 }
1197 break;
1198 default:
1199 break;
1200
1201 }
1202 }
1203
1204 void optc1_get_crtc_scanoutpos(
1205 struct timing_generator *optc,
1206 uint32_t *v_blank_start,
1207 uint32_t *v_blank_end,
1208 uint32_t *h_position,
1209 uint32_t *v_position)
1210 {
1211 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1212 struct crtc_position position;
1213
1214 REG_GET_2(OTG_V_BLANK_START_END,
1215 OTG_V_BLANK_START, v_blank_start,
1216 OTG_V_BLANK_END, v_blank_end);
1217
1218 optc1_get_position(optc, &position);
1219
1220 *h_position = position.horizontal_count;
1221 *v_position = position.vertical_count;
1222 }
1223
1224 static void optc1_enable_stereo(struct timing_generator *optc,
1225 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1226 {
1227 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1228
1229 if (flags) {
1230 uint32_t stereo_en;
1231 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1232
1233 if (flags->PROGRAM_STEREO)
1234 REG_UPDATE_3(OTG_STEREO_CONTROL,
1235 OTG_STEREO_EN, stereo_en,
1236 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1237 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1238
1239 if (flags->PROGRAM_POLARITY)
1240 REG_UPDATE(OTG_STEREO_CONTROL,
1241 OTG_STEREO_EYE_FLAG_POLARITY,
1242 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1243
1244 if (flags->DISABLE_STEREO_DP_SYNC)
1245 REG_UPDATE(OTG_STEREO_CONTROL,
1246 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1247
1248 if (flags->PROGRAM_STEREO)
1249 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1250 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1251 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1252
1253 }
1254 }
1255
1256 void optc1_program_stereo(struct timing_generator *optc,
1257 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1258 {
1259 if (flags->PROGRAM_STEREO)
1260 optc1_enable_stereo(optc, timing, flags);
1261 else
1262 optc1_disable_stereo(optc);
1263 }
1264
1265
1266 bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1267 {
1268 bool ret = false;
1269 uint32_t left_eye = 0;
1270 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1271
1272 REG_GET(OTG_STEREO_STATUS,
1273 OTG_STEREO_CURRENT_EYE, &left_eye);
1274 if (left_eye == 1)
1275 ret = true;
1276 else
1277 ret = false;
1278
1279 return ret;
1280 }
1281
1282 bool optc1_get_hw_timing(struct timing_generator *tg,
1283 struct dc_crtc_timing *hw_crtc_timing)
1284 {
1285 struct dcn_otg_state s = {0};
1286
1287 if (tg == NULL || hw_crtc_timing == NULL)
1288 return false;
1289
1290 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1291
1292 hw_crtc_timing->h_total = s.h_total + 1;
1293 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1294 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
1295 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1296
1297 hw_crtc_timing->v_total = s.v_total + 1;
1298 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1299 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
1300 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1301
1302 return true;
1303 }
1304
1305
1306 void optc1_read_otg_state(struct optc *optc1,
1307 struct dcn_otg_state *s)
1308 {
1309 REG_GET(OTG_CONTROL,
1310 OTG_MASTER_EN, &s->otg_enabled);
1311
1312 REG_GET_2(OTG_V_BLANK_START_END,
1313 OTG_V_BLANK_START, &s->v_blank_start,
1314 OTG_V_BLANK_END, &s->v_blank_end);
1315
1316 REG_GET(OTG_V_SYNC_A_CNTL,
1317 OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1318
1319 REG_GET(OTG_V_TOTAL,
1320 OTG_V_TOTAL, &s->v_total);
1321
1322 REG_GET(OTG_V_TOTAL_MAX,
1323 OTG_V_TOTAL_MAX, &s->v_total_max);
1324
1325 REG_GET(OTG_V_TOTAL_MIN,
1326 OTG_V_TOTAL_MIN, &s->v_total_min);
1327
1328 REG_GET(OTG_V_TOTAL_CONTROL,
1329 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1330
1331 REG_GET(OTG_V_TOTAL_CONTROL,
1332 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1333
1334 REG_GET_2(OTG_V_SYNC_A,
1335 OTG_V_SYNC_A_START, &s->v_sync_a_start,
1336 OTG_V_SYNC_A_END, &s->v_sync_a_end);
1337
1338 REG_GET_2(OTG_H_BLANK_START_END,
1339 OTG_H_BLANK_START, &s->h_blank_start,
1340 OTG_H_BLANK_END, &s->h_blank_end);
1341
1342 REG_GET_2(OTG_H_SYNC_A,
1343 OTG_H_SYNC_A_START, &s->h_sync_a_start,
1344 OTG_H_SYNC_A_END, &s->h_sync_a_end);
1345
1346 REG_GET(OTG_H_SYNC_A_CNTL,
1347 OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1348
1349 REG_GET(OTG_H_TOTAL,
1350 OTG_H_TOTAL, &s->h_total);
1351
1352 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1353 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1354 }
1355
1356 bool optc1_get_otg_active_size(struct timing_generator *optc,
1357 uint32_t *otg_active_width,
1358 uint32_t *otg_active_height)
1359 {
1360 uint32_t otg_enabled;
1361 uint32_t v_blank_start;
1362 uint32_t v_blank_end;
1363 uint32_t h_blank_start;
1364 uint32_t h_blank_end;
1365 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1366
1367
1368 REG_GET(OTG_CONTROL,
1369 OTG_MASTER_EN, &otg_enabled);
1370
1371 if (otg_enabled == 0)
1372 return false;
1373
1374 REG_GET_2(OTG_V_BLANK_START_END,
1375 OTG_V_BLANK_START, &v_blank_start,
1376 OTG_V_BLANK_END, &v_blank_end);
1377
1378 REG_GET_2(OTG_H_BLANK_START_END,
1379 OTG_H_BLANK_START, &h_blank_start,
1380 OTG_H_BLANK_END, &h_blank_end);
1381
1382 *otg_active_width = v_blank_start - v_blank_end;
1383 *otg_active_height = h_blank_start - h_blank_end;
1384 return true;
1385 }
1386
1387 void optc1_clear_optc_underflow(struct timing_generator *optc)
1388 {
1389 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1390
1391 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1392 }
1393
1394 void optc1_tg_init(struct timing_generator *optc)
1395 {
1396 optc1_set_blank_data_double_buffer(optc, true);
1397 optc1_set_timing_double_buffer(optc, true);
1398 optc1_clear_optc_underflow(optc);
1399 }
1400
1401 bool optc1_is_tg_enabled(struct timing_generator *optc)
1402 {
1403 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1404 uint32_t otg_enabled = 0;
1405
1406 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1407
1408 return (otg_enabled != 0);
1409
1410 }
1411
1412 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1413 {
1414 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1415 uint32_t underflow_occurred = 0;
1416
1417 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1418 OPTC_UNDERFLOW_OCCURRED_STATUS,
1419 &underflow_occurred);
1420
1421 return (underflow_occurred == 1);
1422 }
1423
1424 bool optc1_configure_crc(struct timing_generator *optc,
1425 const struct crc_params *params)
1426 {
1427 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1428
1429 /* Cannot configure crc on a CRTC that is disabled */
1430 if (!optc1_is_tg_enabled(optc))
1431 return false;
1432
1433 REG_WRITE(OTG_CRC_CNTL, 0);
1434
1435 if (!params->enable)
1436 return true;
1437
1438 /* Program frame boundaries */
1439 /* Window A x axis start and end. */
1440 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1441 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1442 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1443
1444 /* Window A y axis start and end. */
1445 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1446 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1447 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1448
1449 /* Window B x axis start and end. */
1450 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1451 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1452 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1453
1454 /* Window B y axis start and end. */
1455 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1456 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1457 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1458
1459 /* Set crc mode and selection, and enable. Only using CRC0*/
1460 REG_UPDATE_3(OTG_CRC_CNTL,
1461 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1462 OTG_CRC0_SELECT, params->selection,
1463 OTG_CRC_EN, 1);
1464
1465 return true;
1466 }
1467
1468 bool optc1_get_crc(struct timing_generator *optc,
1469 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1470 {
1471 uint32_t field = 0;
1472 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1473
1474 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1475
1476 /* Early return if CRC is not enabled for this CRTC */
1477 if (!field)
1478 return false;
1479
1480 REG_GET_2(OTG_CRC0_DATA_RG,
1481 CRC0_R_CR, r_cr,
1482 CRC0_G_Y, g_y);
1483
1484 REG_GET(OTG_CRC0_DATA_B,
1485 CRC0_B_CB, b_cb);
1486
1487 return true;
1488 }
1489
1490 static const struct timing_generator_funcs dcn10_tg_funcs = {
1491 .validate_timing = optc1_validate_timing,
1492 .program_timing = optc1_program_timing,
1493 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1494 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1495 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1496 .program_global_sync = optc1_program_global_sync,
1497 .enable_crtc = optc1_enable_crtc,
1498 .disable_crtc = optc1_disable_crtc,
1499 /* used by enable_timing_synchronization. Not need for FPGA */
1500 .is_counter_moving = optc1_is_counter_moving,
1501 .get_position = optc1_get_position,
1502 .get_frame_count = optc1_get_vblank_counter,
1503 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1504 .get_otg_active_size = optc1_get_otg_active_size,
1505 .set_early_control = optc1_set_early_control,
1506 /* used by enable_timing_synchronization. Not need for FPGA */
1507 .wait_for_state = optc1_wait_for_state,
1508 .set_blank = optc1_set_blank,
1509 .is_blanked = optc1_is_blanked,
1510 .set_blank_color = optc1_program_blank_color,
1511 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1512 .enable_reset_trigger = optc1_enable_reset_trigger,
1513 .enable_crtc_reset = optc1_enable_crtc_reset,
1514 .disable_reset_trigger = optc1_disable_reset_trigger,
1515 .lock = optc1_lock,
1516 .unlock = optc1_unlock,
1517 .enable_optc_clock = optc1_enable_optc_clock,
1518 .set_drr = optc1_set_drr,
1519 .set_static_screen_control = optc1_set_static_screen_control,
1520 .set_test_pattern = optc1_set_test_pattern,
1521 .program_stereo = optc1_program_stereo,
1522 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1523 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1524 .tg_init = optc1_tg_init,
1525 .is_tg_enabled = optc1_is_tg_enabled,
1526 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1527 .clear_optc_underflow = optc1_clear_optc_underflow,
1528 .get_crc = optc1_get_crc,
1529 .configure_crc = optc1_configure_crc,
1530 .set_vtg_params = optc1_set_vtg_params,
1531 .program_manual_trigger = optc1_program_manual_trigger,
1532 .setup_manual_trigger = optc1_setup_manual_trigger,
1533 .get_hw_timing = optc1_get_hw_timing,
1534 };
1535
1536 void dcn10_timing_generator_init(struct optc *optc1)
1537 {
1538 optc1->base.funcs = &dcn10_tg_funcs;
1539
1540 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1541 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1542
1543 optc1->min_h_blank = 32;
1544 optc1->min_v_blank = 3;
1545 optc1->min_v_blank_interlace = 5;
1546 optc1->min_h_sync_width = 4;
1547 optc1->min_v_sync_width = 1;
1548 }
1549
1550 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
1551 *
1552 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1553 * containter rate.
1554 *
1555 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1556 * halved to maintain the correct pixel rate.
1557 *
1558 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1559 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
1560 *
1561 */
1562 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
1563 {
1564 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1565
1566 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
1567 && !timing->dsc_cfg.ycbcr422_simple);
1568 return two_pix;
1569 }
1570
Linux with added FPC-III support