drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_TIMING_GENERATOR_DCN10_H__
  27 #define __DC_TIMING_GENERATOR_DCN10_H__
  28
  29 #include "timing_generator.h"
  30
  31 #define DCN10TG_FROM_TG(tg)\
  32         container_of(tg, struct optc, base)
  33
  34 #define TG_COMMON_REG_LIST_DCN(inst) \
  35         SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
  36         SRI(OTG_VUPDATE_PARAM, OTG, inst),\
  37         SRI(OTG_VREADY_PARAM, OTG, inst),\
  38         SRI(OTG_BLANK_CONTROL, OTG, inst),\
  39         SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
  40         SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
  41         SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
  42         SRI(OTG_H_TOTAL, OTG, inst),\
  43         SRI(OTG_H_BLANK_START_END, OTG, inst),\
  44         SRI(OTG_H_SYNC_A, OTG, inst),\
  45         SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
  46         SRI(OTG_H_TIMING_CNTL, OTG, inst),\
  47         SRI(OTG_V_TOTAL, OTG, inst),\
  48         SRI(OTG_V_BLANK_START_END, OTG, inst),\
  49         SRI(OTG_V_SYNC_A, OTG, inst),\
  50         SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
  51         SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
  52         SRI(OTG_CONTROL, OTG, inst),\
  53         SRI(OTG_STEREO_CONTROL, OTG, inst),\
  54         SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
  55         SRI(OTG_STEREO_STATUS, OTG, inst),\
  56         SRI(OTG_V_TOTAL_MAX, OTG, inst),\
  57         SRI(OTG_V_TOTAL_MID, OTG, inst),\
  58         SRI(OTG_V_TOTAL_MIN, OTG, inst),\
  59         SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
  60         SRI(OTG_TRIGA_CNTL, OTG, inst),\
  61         SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
  62         SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
  63         SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
  64         SRI(OTG_STATUS, OTG, inst),\
  65         SRI(OTG_STATUS_POSITION, OTG, inst),\
  66         SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
  67         SRI(OTG_BLACK_COLOR, OTG, inst),\
  68         SRI(OTG_CLOCK_CONTROL, OTG, inst),\
  69         SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
  70         SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
  71         SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
  72         SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
  73         SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
  74         SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
  75         SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
  76         SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
  77         SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
  78         SRI(CONTROL, VTG, inst),\
  79         SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
  80         SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
  81         SRI(OTG_GSL_CONTROL, OTG, inst),\
  82         SRI(OTG_CRC_CNTL, OTG, inst),\
  83         SRI(OTG_CRC0_DATA_RG, OTG, inst),\
  84         SRI(OTG_CRC0_DATA_B, OTG, inst),\
  85         SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
  86         SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
  87         SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
  88         SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
  89         SR(GSL_SOURCE_SELECT),\
  90         SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
  91         SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
  92
  93 #define TG_COMMON_REG_LIST_DCN1_0(inst) \
  94         TG_COMMON_REG_LIST_DCN(inst),\
  95         SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
  96         SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
  97         SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
  98         SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
  99
 100
 101 struct dcn_optc_registers {
 102         uint32_t OTG_GLOBAL_CONTROL1;
 103         uint32_t OTG_GLOBAL_CONTROL2;
 104         uint32_t OTG_VERT_SYNC_CONTROL;
 105         uint32_t OTG_MASTER_UPDATE_MODE;
 106         uint32_t OTG_GSL_CONTROL;
 107         uint32_t OTG_VSTARTUP_PARAM;
 108         uint32_t OTG_VUPDATE_PARAM;
 109         uint32_t OTG_VREADY_PARAM;
 110         uint32_t OTG_BLANK_CONTROL;
 111         uint32_t OTG_MASTER_UPDATE_LOCK;
 112         uint32_t OTG_GLOBAL_CONTROL0;
 113         uint32_t OTG_DOUBLE_BUFFER_CONTROL;
 114         uint32_t OTG_H_TOTAL;
 115         uint32_t OTG_H_BLANK_START_END;
 116         uint32_t OTG_H_SYNC_A;
 117         uint32_t OTG_H_SYNC_A_CNTL;
 118         uint32_t OTG_H_TIMING_CNTL;
 119         uint32_t OTG_V_TOTAL;
 120         uint32_t OTG_V_BLANK_START_END;
 121         uint32_t OTG_V_SYNC_A;
 122         uint32_t OTG_V_SYNC_A_CNTL;
 123         uint32_t OTG_INTERLACE_CONTROL;
 124         uint32_t OTG_CONTROL;
 125         uint32_t OTG_STEREO_CONTROL;
 126         uint32_t OTG_3D_STRUCTURE_CONTROL;
 127         uint32_t OTG_STEREO_STATUS;
 128         uint32_t OTG_V_TOTAL_MAX;
 129         uint32_t OTG_V_TOTAL_MID;
 130         uint32_t OTG_V_TOTAL_MIN;
 131         uint32_t OTG_V_TOTAL_CONTROL;
 132         uint32_t OTG_TRIGA_CNTL;
 133         uint32_t OTG_TRIGA_MANUAL_TRIG;
 134         uint32_t OTG_MANUAL_FLOW_CONTROL;
 135         uint32_t OTG_FORCE_COUNT_NOW_CNTL;
 136         uint32_t OTG_STATIC_SCREEN_CONTROL;
 137         uint32_t OTG_STATUS_FRAME_COUNT;
 138         uint32_t OTG_STATUS;
 139         uint32_t OTG_STATUS_POSITION;
 140         uint32_t OTG_NOM_VERT_POSITION;
 141         uint32_t OTG_BLACK_COLOR;
 142         uint32_t OTG_TEST_PATTERN_PARAMETERS;
 143         uint32_t OTG_TEST_PATTERN_CONTROL;
 144         uint32_t OTG_TEST_PATTERN_COLOR;
 145         uint32_t OTG_CLOCK_CONTROL;
 146         uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
 147         uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
 148         uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL;
 149         uint32_t OTG_VERTICAL_INTERRUPT1_POSITION;
 150         uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
 151         uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
 152         uint32_t OPTC_INPUT_CLOCK_CONTROL;
 153         uint32_t OPTC_DATA_SOURCE_SELECT;
 154         uint32_t OPTC_MEMORY_CONFIG;
 155         uint32_t OPTC_INPUT_GLOBAL_CONTROL;
 156         uint32_t CONTROL;
 157         uint32_t OTG_GSL_WINDOW_X;
 158         uint32_t OTG_GSL_WINDOW_Y;
 159         uint32_t OTG_VUPDATE_KEEPOUT;
 160         uint32_t OTG_CRC_CNTL;
 161         uint32_t OTG_CRC_CNTL2;
 162         uint32_t OTG_CRC0_DATA_RG;
 163         uint32_t OTG_CRC0_DATA_B;
 164         uint32_t OTG_CRC0_WINDOWA_X_CONTROL;
 165         uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
 166         uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
 167         uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
 168         uint32_t GSL_SOURCE_SELECT;
 169         uint32_t DWB_SOURCE_SELECT;
 170         uint32_t OTG_DSC_START_POSITION;
 171         uint32_t OPTC_DATA_FORMAT_CONTROL;
 172         uint32_t OPTC_BYTES_PER_PIXEL;
 173         uint32_t OPTC_WIDTH_CONTROL;
 174         uint32_t OTG_BLANK_DATA_COLOR;
 175         uint32_t OTG_BLANK_DATA_COLOR_EXT;
 176         uint32_t OTG_DRR_TRIGGER_WINDOW;
 177         uint32_t OTG_M_CONST_DTO0;
 178         uint32_t OTG_M_CONST_DTO1;
 179         uint32_t OTG_DRR_V_TOTAL_CHANGE;
 180         uint32_t OTG_GLOBAL_CONTROL4;
 181 };
 182
 183 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
 184         SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
 185         SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
 186         SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
 187         SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
 188         SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
 189         SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
 190         SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
 191         SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
 192         SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
 193         SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
 194         SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
 195         SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
 196         SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
 197         SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
 198         SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
 199         SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
 200         SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
 201         SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
 202         SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
 203         SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
 204         SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
 205         SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
 206         SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
 207         SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
 208         SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
 209         SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
 210         SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
 211         SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
 212         SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
 213         SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
 214         SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
 215         SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
 216         SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
 217         SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
 218         SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
 219         SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
 220         SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
 221         SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
 222         SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
 223         SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
 224         SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
 225         SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
 226         SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
 227         SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
 228         SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
 229         SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
 230         SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
 231         SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
 232         SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
 233         SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
 234         SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
 235         SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
 236         SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
 237         SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
 238         SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
 239         SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
 240         SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
 241         SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
 242         SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
 243         SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
 244         SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
 245         SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
 246         SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
 247         SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
 248         SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
 249         SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
 250         SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
 251         SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
 252         SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
 253         SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
 254         SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
 255         SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
 256         SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
 257         SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
 258         SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
 259         SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
 260         SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
 261         SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
 262         SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
 263         SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
 264         SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
 265         SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
 266         SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
 267         SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
 268         SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
 269         SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
 270         SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
 271         SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
 272         SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
 273         SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
 274         SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
 275         SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
 276         SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
 277         SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
 278         SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
 279         SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
 280         SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\
 281         SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
 282         SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
 283         SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
 284         SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
 285         SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
 286         SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
 287         SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
 288         SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
 289         SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
 290         SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
 291         SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
 292         SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
 293         SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
 294         SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
 295         SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
 296         SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
 297         SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
 298         SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
 299         SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
 300         SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
 301         SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
 302         SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
 303         SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
 304         SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
 305
 306
 307
 308 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
 309         TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
 310         SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
 311         SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
 312         SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
 313         SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
 314         SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
 315         SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
 316         SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
 317         SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
 318         SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
 319         SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
 320         SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
 321         SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
 322         SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\
 323
 324 #define TG_REG_FIELD_LIST_DCN1_0(type) \
 325         type VSTARTUP_START;\
 326         type VUPDATE_OFFSET;\
 327         type VUPDATE_WIDTH;\
 328         type VREADY_OFFSET;\
 329         type OTG_BLANK_DATA_EN;\
 330         type OTG_BLANK_DE_MODE;\
 331         type OTG_CURRENT_BLANK_STATE;\
 332         type OTG_MASTER_UPDATE_LOCK;\
 333         type UPDATE_LOCK_STATUS;\
 334         type OTG_UPDATE_PENDING;\
 335         type OTG_MASTER_UPDATE_LOCK_SEL;\
 336         type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
 337         type OTG_H_TOTAL;\
 338         type OTG_H_BLANK_START;\
 339         type OTG_H_BLANK_END;\
 340         type OTG_H_SYNC_A_START;\
 341         type OTG_H_SYNC_A_END;\
 342         type OTG_H_SYNC_A_POL;\
 343         type OTG_H_TIMING_DIV_BY2;\
 344         type OTG_V_TOTAL;\
 345         type OTG_V_BLANK_START;\
 346         type OTG_V_BLANK_END;\
 347         type OTG_V_SYNC_A_START;\
 348         type OTG_V_SYNC_A_END;\
 349         type OTG_V_SYNC_A_POL;\
 350         type OTG_INTERLACE_ENABLE;\
 351         type OTG_MASTER_EN;\
 352         type OTG_START_POINT_CNTL;\
 353         type OTG_DISABLE_POINT_CNTL;\
 354         type OTG_FIELD_NUMBER_CNTL;\
 355         type OTG_STEREO_EN;\
 356         type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
 357         type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
 358         type OTG_STEREO_EYE_FLAG_POLARITY;\
 359         type OTG_STEREO_CURRENT_EYE;\
 360         type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
 361         type OTG_3D_STRUCTURE_EN;\
 362         type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
 363         type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
 364         type OTG_V_TOTAL_MAX;\
 365         type OTG_V_TOTAL_MID;\
 366         type OTG_V_TOTAL_MIN;\
 367         type OTG_V_TOTAL_MIN_SEL;\
 368         type OTG_V_TOTAL_MAX_SEL;\
 369         type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
 370         type OTG_VTOTAL_MID_FRAME_NUM;\
 371         type OTG_FORCE_LOCK_ON_EVENT;\
 372         type OTG_SET_V_TOTAL_MIN_MASK_EN;\
 373         type OTG_SET_V_TOTAL_MIN_MASK;\
 374         type OTG_FORCE_COUNT_NOW_CLEAR;\
 375         type OTG_FORCE_COUNT_NOW_MODE;\
 376         type OTG_FORCE_COUNT_NOW_OCCURRED;\
 377         type OTG_TRIGA_SOURCE_SELECT;\
 378         type OTG_TRIGA_SOURCE_PIPE_SELECT;\
 379         type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
 380         type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
 381         type OTG_TRIGA_POLARITY_SELECT;\
 382         type OTG_TRIGA_FREQUENCY_SELECT;\
 383         type OTG_TRIGA_DELAY;\
 384         type OTG_TRIGA_CLEAR;\
 385         type OTG_TRIGA_MANUAL_TRIG;\
 386         type OTG_STATIC_SCREEN_EVENT_MASK;\
 387         type OTG_STATIC_SCREEN_FRAME_COUNT;\
 388         type OTG_FRAME_COUNT;\
 389         type OTG_V_BLANK;\
 390         type OTG_V_ACTIVE_DISP;\
 391         type OTG_HORZ_COUNT;\
 392         type OTG_VERT_COUNT;\
 393         type OTG_VERT_COUNT_NOM;\
 394         type OTG_BLACK_COLOR_B_CB;\
 395         type OTG_BLACK_COLOR_G_Y;\
 396         type OTG_BLACK_COLOR_R_CR;\
 397         type OTG_BLANK_DATA_COLOR_BLUE_CB;\
 398         type OTG_BLANK_DATA_COLOR_GREEN_Y;\
 399         type OTG_BLANK_DATA_COLOR_RED_CR;\
 400         type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\
 401         type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\
 402         type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\
 403         type OTG_VTOTAL_MID_REPLACING_MIN_EN;\
 404         type OTG_TEST_PATTERN_INC0;\
 405         type OTG_TEST_PATTERN_INC1;\
 406         type OTG_TEST_PATTERN_VRES;\
 407         type OTG_TEST_PATTERN_HRES;\
 408         type OTG_TEST_PATTERN_RAMP0_OFFSET;\
 409         type OTG_TEST_PATTERN_EN;\
 410         type OTG_TEST_PATTERN_MODE;\
 411         type OTG_TEST_PATTERN_DYNAMIC_RANGE;\
 412         type OTG_TEST_PATTERN_COLOR_FORMAT;\
 413         type OTG_TEST_PATTERN_MASK;\
 414         type OTG_TEST_PATTERN_DATA;\
 415         type OTG_BUSY;\
 416         type OTG_CLOCK_EN;\
 417         type OTG_CLOCK_ON;\
 418         type OTG_CLOCK_GATE_DIS;\
 419         type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
 420         type OTG_VERTICAL_INTERRUPT0_LINE_START;\
 421         type OTG_VERTICAL_INTERRUPT0_LINE_END;\
 422         type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\
 423         type OTG_VERTICAL_INTERRUPT1_LINE_START;\
 424         type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
 425         type OTG_VERTICAL_INTERRUPT2_LINE_START;\
 426         type OPTC_INPUT_CLK_EN;\
 427         type OPTC_INPUT_CLK_ON;\
 428         type OPTC_INPUT_CLK_GATE_DIS;\
 429         type OPTC_UNDERFLOW_OCCURRED_STATUS;\
 430         type OPTC_UNDERFLOW_CLEAR;\
 431         type OPTC_SRC_SEL;\
 432         type VTG0_ENABLE;\
 433         type VTG0_FP2;\
 434         type VTG0_VCOUNT_INIT;\
 435         type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\
 436         type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\
 437         type OTG_AUTO_FORCE_VSYNC_MODE;\
 438         type MASTER_UPDATE_INTERLACED_MODE;\
 439         type OTG_GSL0_EN;\
 440         type OTG_GSL1_EN;\
 441         type OTG_GSL2_EN;\
 442         type OTG_GSL_MASTER_EN;\
 443         type OTG_GSL_FORCE_DELAY;\
 444         type OTG_GSL_CHECK_ALL_FIELDS;\
 445         type OTG_GSL_WINDOW_START_X;\
 446         type OTG_GSL_WINDOW_END_X;\
 447         type OTG_GSL_WINDOW_START_Y;\
 448         type OTG_GSL_WINDOW_END_Y;\
 449         type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\
 450         type OTG_GSL_MASTER_MODE;\
 451         type OTG_MASTER_UPDATE_LOCK_GSL_EN;\
 452         type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\
 453         type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\
 454         type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\
 455         type OTG_CRC_CONT_EN;\
 456         type OTG_CRC0_SELECT;\
 457         type OTG_CRC_EN;\
 458         type CRC0_R_CR;\
 459         type CRC0_G_Y;\
 460         type CRC0_B_CB;\
 461         type OTG_CRC0_WINDOWA_X_START;\
 462         type OTG_CRC0_WINDOWA_X_END;\
 463         type OTG_CRC0_WINDOWA_Y_START;\
 464         type OTG_CRC0_WINDOWA_Y_END;\
 465         type OTG_CRC0_WINDOWB_X_START;\
 466         type OTG_CRC0_WINDOWB_X_END;\
 467         type OTG_CRC0_WINDOWB_Y_START;\
 468         type OTG_CRC0_WINDOWB_Y_END;\
 469         type GSL0_READY_SOURCE_SEL;\
 470         type GSL1_READY_SOURCE_SEL;\
 471         type GSL2_READY_SOURCE_SEL;\
 472         type MANUAL_FLOW_CONTROL;\
 473         type MANUAL_FLOW_CONTROL_SEL;
 474
 475 #define TG_REG_FIELD_LIST(type) \
 476         TG_REG_FIELD_LIST_DCN1_0(type)\
 477         type OTG_V_SYNC_MODE;\
 478         type OTG_DRR_TRIGGER_WINDOW_START_X;\
 479         type OTG_DRR_TRIGGER_WINDOW_END_X;\
 480         type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\
 481         type OTG_OUT_MUX;\
 482         type OTG_M_CONST_DTO_PHASE;\
 483         type OTG_M_CONST_DTO_MODULO;\
 484         type MASTER_UPDATE_LOCK_DB_X;\
 485         type MASTER_UPDATE_LOCK_DB_Y;\
 486         type MASTER_UPDATE_LOCK_DB_EN;\
 487         type GLOBAL_UPDATE_LOCK_EN;\
 488         type DIG_UPDATE_LOCATION;\
 489         type OTG_DSC_START_POSITION_X;\
 490         type OTG_DSC_START_POSITION_LINE_NUM;\
 491         type OPTC_NUM_OF_INPUT_SEGMENT;\
 492         type OPTC_SEG0_SRC_SEL;\
 493         type OPTC_SEG1_SRC_SEL;\
 494         type OPTC_SEG2_SRC_SEL;\
 495         type OPTC_SEG3_SRC_SEL;\
 496         type OPTC_MEM_SEL;\
 497         type OPTC_DATA_FORMAT;\
 498         type OPTC_DSC_MODE;\
 499         type OPTC_DSC_BYTES_PER_PIXEL;\
 500         type OPTC_DSC_SLICE_WIDTH;\
 501         type OPTC_SEGMENT_WIDTH;\
 502         type OPTC_DWB0_SOURCE_SELECT;\
 503         type OPTC_DWB1_SOURCE_SELECT;\
 504         type MASTER_UPDATE_LOCK_DB_START_X;\
 505         type MASTER_UPDATE_LOCK_DB_END_X;\
 506         type MASTER_UPDATE_LOCK_DB_START_Y;\
 507         type MASTER_UPDATE_LOCK_DB_END_Y;\
 508         type DIG_UPDATE_POSITION_X;\
 509         type DIG_UPDATE_POSITION_Y;\
 510         type OTG_H_TIMING_DIV_MODE;\
 511         type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
 512         type OTG_CRC_DSC_MODE;\
 513         type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
 514         type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
 515         type OTG_CRC_DATA_FORMAT;
 516
 517
 518 struct dcn_optc_shift {
 519         TG_REG_FIELD_LIST(uint8_t)
 520 };
 521
 522 struct dcn_optc_mask {
 523         TG_REG_FIELD_LIST(uint32_t)
 524 };
 525
 526 struct optc {
 527         struct timing_generator base;
 528
 529         const struct dcn_optc_registers *tg_regs;
 530         const struct dcn_optc_shift *tg_shift;
 531         const struct dcn_optc_mask *tg_mask;
 532
 533         int opp_count;
 534
 535         uint32_t max_h_total;
 536         uint32_t max_v_total;
 537
 538         uint32_t min_h_blank;
 539
 540         uint32_t min_h_sync_width;
 541         uint32_t min_v_sync_width;
 542         uint32_t min_v_blank;
 543         uint32_t min_v_blank_interlace;
 544
 545         int vstartup_start;
 546         int vupdate_offset;
 547         int vupdate_width;
 548         int vready_offset;
 549         enum signal_type signal;
 550 };
 551
 552 void dcn10_timing_generator_init(struct optc *optc);
 553
 554 struct dcn_otg_state {
 555         uint32_t v_blank_start;
 556         uint32_t v_blank_end;
 557         uint32_t v_sync_a_pol;
 558         uint32_t v_total;
 559         uint32_t v_total_max;
 560         uint32_t v_total_min;
 561         uint32_t v_total_min_sel;
 562         uint32_t v_total_max_sel;
 563         uint32_t v_sync_a_start;
 564         uint32_t v_sync_a_end;
 565         uint32_t h_blank_start;
 566         uint32_t h_blank_end;
 567         uint32_t h_sync_a_start;
 568         uint32_t h_sync_a_end;
 569         uint32_t h_sync_a_pol;
 570         uint32_t h_total;
 571         uint32_t underflow_occurred_status;
 572         uint32_t otg_enabled;
 573         uint32_t blank_enabled;
 574 };
 575
 576 void optc1_read_otg_state(struct optc *optc1,
 577                 struct dcn_otg_state *s);
 578
 579 bool optc1_get_hw_timing(struct timing_generator *tg,
 580                 struct dc_crtc_timing *hw_crtc_timing);
 581
 582 bool optc1_validate_timing(
 583         struct timing_generator *optc,
 584         const struct dc_crtc_timing *timing);
 585
 586 void optc1_program_timing(
 587         struct timing_generator *optc,
 588         const struct dc_crtc_timing *dc_crtc_timing,
 589         int vready_offset,
 590         int vstartup_start,
 591         int vupdate_offset,
 592         int vupdate_width,
 593         const enum signal_type signal,
 594         bool use_vbios);
 595
 596 void optc1_setup_vertical_interrupt0(
 597                 struct timing_generator *optc,
 598                 uint32_t start_line,
 599                 uint32_t end_line);
 600 void optc1_setup_vertical_interrupt1(
 601                 struct timing_generator *optc,
 602                 uint32_t start_line);
 603 void optc1_setup_vertical_interrupt2(
 604                 struct timing_generator *optc,
 605                 uint32_t start_line);
 606
 607 void optc1_program_global_sync(
 608                 struct timing_generator *optc,
 609                 int vready_offset,
 610                 int vstartup_start,
 611                 int vupdate_offset,
 612                 int vupdate_width);
 613
 614 bool optc1_disable_crtc(struct timing_generator *optc);
 615
 616 bool optc1_is_counter_moving(struct timing_generator *optc);
 617
 618 void optc1_get_position(struct timing_generator *optc,
 619                 struct crtc_position *position);
 620
 621 uint32_t optc1_get_vblank_counter(struct timing_generator *optc);
 622
 623 void optc1_get_crtc_scanoutpos(
 624         struct timing_generator *optc,
 625         uint32_t *v_blank_start,
 626         uint32_t *v_blank_end,
 627         uint32_t *h_position,
 628         uint32_t *v_position);
 629
 630 void optc1_set_early_control(
 631         struct timing_generator *optc,
 632         uint32_t early_cntl);
 633
 634 void optc1_wait_for_state(struct timing_generator *optc,
 635                 enum crtc_state state);
 636
 637 void optc1_set_blank(struct timing_generator *optc,
 638                 bool enable_blanking);
 639
 640 bool optc1_is_blanked(struct timing_generator *optc);
 641
 642 void optc1_program_blank_color(
 643                 struct timing_generator *optc,
 644                 const struct tg_color *black_color);
 645
 646 bool optc1_did_triggered_reset_occur(
 647         struct timing_generator *optc);
 648
 649 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);
 650
 651 void optc1_disable_reset_trigger(struct timing_generator *optc);
 652
 653 void optc1_lock(struct timing_generator *optc);
 654
 655 void optc1_unlock(struct timing_generator *optc);
 656
 657 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
 658
 659 void optc1_set_drr(
 660         struct timing_generator *optc,
 661         const struct drr_params *params);
 662
 663 void optc1_set_static_screen_control(
 664         struct timing_generator *optc,
 665         uint32_t event_triggers,
 666         uint32_t num_frames);
 667
 668 void optc1_program_stereo(struct timing_generator *optc,
 669         const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
 670
 671 bool optc1_is_stereo_left_eye(struct timing_generator *optc);
 672
 673 void optc1_clear_optc_underflow(struct timing_generator *optc);
 674
 675 void optc1_tg_init(struct timing_generator *optc);
 676
 677 bool optc1_is_tg_enabled(struct timing_generator *optc);
 678
 679 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);
 680
 681 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
 682
 683 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);
 684
 685 bool optc1_get_otg_active_size(struct timing_generator *optc,
 686                 uint32_t *otg_active_width,
 687                 uint32_t *otg_active_height);
 688
 689 void optc1_enable_crtc_reset(
 690                 struct timing_generator *optc,
 691                 int source_tg_inst,
 692                 struct crtc_trigger_info *crtc_tp);
 693
 694 bool optc1_configure_crc(struct timing_generator *optc,
 695                           const struct crc_params *params);
 696
 697 bool optc1_get_crc(struct timing_generator *optc,
 698                     uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
 699
 700 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
 701
 702 void optc1_set_vtg_params(struct timing_generator *optc,
 703                 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
 704
 705 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */