drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_LINK_DP_H__
  27 #define __DC_LINK_DP_H__
  28
  29 #define LINK_TRAINING_ATTEMPTS 4
  30 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
  31 #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/
  32 #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
  33
  34 struct dc_link;
  35 struct dc_stream_state;
  36 struct dc_link_settings;
  37
  38 bool dp_verify_link_cap(
  39         struct dc_link *link,
  40         struct dc_link_settings *known_limit_link_setting,
  41         int *fail_count);
  42
  43 bool dp_verify_link_cap_with_retries(
  44         struct dc_link *link,
  45         struct dc_link_settings *known_limit_link_setting,
  46         int attempts);
  47
  48 bool dp_verify_mst_link_cap(
  49         struct dc_link *link);
  50
  51 bool dp_validate_mode_timing(
  52         struct dc_link *link,
  53         const struct dc_crtc_timing *timing);
  54
  55 void decide_link_settings(
  56         struct dc_stream_state *stream,
  57         struct dc_link_settings *link_setting);
  58
  59 bool perform_link_training_with_retries(
  60         const struct dc_link_settings *link_setting,
  61         bool skip_video_pattern,
  62         int attempts,
  63         struct pipe_ctx *pipe_ctx,
  64         enum signal_type signal);
  65
  66 bool is_mst_supported(struct dc_link *link);
  67
  68 bool detect_dp_sink_caps(struct dc_link *link);
  69
  70 void detect_edp_sink_caps(struct dc_link *link);
  71
  72 bool is_dp_active_dongle(const struct dc_link *link);
  73
  74 void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
  75
  76 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
  77 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
  78
  79 bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
  80
  81 void dpcd_set_source_specific_data(struct dc_link *link);
  82
  83 void dp_set_fec_ready(struct dc_link *link, bool ready);
  84 void dp_set_fec_enable(struct dc_link *link, bool enable);
  85 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
  86 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
  87 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
  88 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
  89
  90 #endif /* __DC_LINK_DP_H__ */