drivers/gpu/drm/amd/include/amd_shared.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __AMD_SHARED_H__
  24 #define __AMD_SHARED_H__
  25
  26 #include <drm/amd_asic_type.h>
  27
  28
  29 #define AMD_MAX_USEC_TIMEOUT            1000000  /* 1000 ms */
  30
  31 /*
  32  * Chip flags
  33  */
  34 enum amd_chip_flags {
  35         AMD_ASIC_MASK = 0x0000ffffUL,
  36         AMD_FLAGS_MASK  = 0xffff0000UL,
  37         AMD_IS_MOBILITY = 0x00010000UL,
  38         AMD_IS_APU      = 0x00020000UL,
  39         AMD_IS_PX       = 0x00040000UL,
  40         AMD_EXP_HW_SUPPORT = 0x00080000UL,
  41 };
  42
  43 enum amd_apu_flags {
  44         AMD_APU_IS_RAVEN = 0x00000001UL,
  45         AMD_APU_IS_RAVEN2 = 0x00000002UL,
  46         AMD_APU_IS_PICASSO = 0x00000004UL,
  47         AMD_APU_IS_RENOIR = 0x00000008UL,
  48         AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
  49         AMD_APU_IS_VANGOGH = 0x00000020UL,
  50 };
  51
  52 /**
  53 * DOC: IP Blocks
  54 *
  55 * GPUs are composed of IP (intellectual property) blocks. These
  56 * IP blocks provide various functionalities: display, graphics,
  57 * video decode, etc. The IP blocks that comprise a particular GPU
  58 * are listed in the GPU's respective SoC file. amdgpu_device.c
  59 * acquires the list of IP blocks for the GPU in use on initialization.
  60 * It can then operate on this list to perform standard driver operations
  61 * such as: init, fini, suspend, resume, etc.
  62 *
  63 *
  64 * IP block implementations are named using the following convention:
  65 * <functionality>_v<version> (E.g.: gfx_v6_0).
  66 */
  67
  68 /**
  69 * enum amd_ip_block_type - Used to classify IP blocks by functionality.
  70 *
  71 * @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
  72 * @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
  73 * @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
  74 * @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
  75 * @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
  76 * @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
  77 * @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
  78 * @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
  79 * @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
  80 * @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
  81 * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
  82 * @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
  83 * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
  84 * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
  85 */
  86 enum amd_ip_block_type {
  87         AMD_IP_BLOCK_TYPE_COMMON,
  88         AMD_IP_BLOCK_TYPE_GMC,
  89         AMD_IP_BLOCK_TYPE_IH,
  90         AMD_IP_BLOCK_TYPE_SMC,
  91         AMD_IP_BLOCK_TYPE_PSP,
  92         AMD_IP_BLOCK_TYPE_DCE,
  93         AMD_IP_BLOCK_TYPE_GFX,
  94         AMD_IP_BLOCK_TYPE_SDMA,
  95         AMD_IP_BLOCK_TYPE_UVD,
  96         AMD_IP_BLOCK_TYPE_VCE,
  97         AMD_IP_BLOCK_TYPE_ACP,
  98         AMD_IP_BLOCK_TYPE_VCN,
  99         AMD_IP_BLOCK_TYPE_MES,
 100         AMD_IP_BLOCK_TYPE_JPEG
 101 };
 102
 103 enum amd_clockgating_state {
 104         AMD_CG_STATE_GATE = 0,
 105         AMD_CG_STATE_UNGATE,
 106 };
 107
 108
 109 enum amd_powergating_state {
 110         AMD_PG_STATE_GATE = 0,
 111         AMD_PG_STATE_UNGATE,
 112 };
 113
 114
 115 /* CG flags */
 116 #define AMD_CG_SUPPORT_GFX_MGCG                 (1 << 0)
 117 #define AMD_CG_SUPPORT_GFX_MGLS                 (1 << 1)
 118 #define AMD_CG_SUPPORT_GFX_CGCG                 (1 << 2)
 119 #define AMD_CG_SUPPORT_GFX_CGLS                 (1 << 3)
 120 #define AMD_CG_SUPPORT_GFX_CGTS                 (1 << 4)
 121 #define AMD_CG_SUPPORT_GFX_CGTS_LS              (1 << 5)
 122 #define AMD_CG_SUPPORT_GFX_CP_LS                (1 << 6)
 123 #define AMD_CG_SUPPORT_GFX_RLC_LS               (1 << 7)
 124 #define AMD_CG_SUPPORT_MC_LS                    (1 << 8)
 125 #define AMD_CG_SUPPORT_MC_MGCG                  (1 << 9)
 126 #define AMD_CG_SUPPORT_SDMA_LS                  (1 << 10)
 127 #define AMD_CG_SUPPORT_SDMA_MGCG                (1 << 11)
 128 #define AMD_CG_SUPPORT_BIF_LS                   (1 << 12)
 129 #define AMD_CG_SUPPORT_UVD_MGCG                 (1 << 13)
 130 #define AMD_CG_SUPPORT_VCE_MGCG                 (1 << 14)
 131 #define AMD_CG_SUPPORT_HDP_LS                   (1 << 15)
 132 #define AMD_CG_SUPPORT_HDP_MGCG                 (1 << 16)
 133 #define AMD_CG_SUPPORT_ROM_MGCG                 (1 << 17)
 134 #define AMD_CG_SUPPORT_DRM_LS                   (1 << 18)
 135 #define AMD_CG_SUPPORT_BIF_MGCG                 (1 << 19)
 136 #define AMD_CG_SUPPORT_GFX_3D_CGCG              (1 << 20)
 137 #define AMD_CG_SUPPORT_GFX_3D_CGLS              (1 << 21)
 138 #define AMD_CG_SUPPORT_DRM_MGCG                 (1 << 22)
 139 #define AMD_CG_SUPPORT_DF_MGCG                  (1 << 23)
 140 #define AMD_CG_SUPPORT_VCN_MGCG                 (1 << 24)
 141 #define AMD_CG_SUPPORT_HDP_DS                   (1 << 25)
 142 #define AMD_CG_SUPPORT_HDP_SD                   (1 << 26)
 143 #define AMD_CG_SUPPORT_IH_CG                    (1 << 27)
 144 #define AMD_CG_SUPPORT_ATHUB_LS                 (1 << 28)
 145 #define AMD_CG_SUPPORT_ATHUB_MGCG               (1 << 29)
 146 #define AMD_CG_SUPPORT_JPEG_MGCG                (1 << 30)
 147 #define AMD_CG_SUPPORT_GFX_FGCG                 (1 << 31)
 148 /* PG flags */
 149 #define AMD_PG_SUPPORT_GFX_PG                   (1 << 0)
 150 #define AMD_PG_SUPPORT_GFX_SMG                  (1 << 1)
 151 #define AMD_PG_SUPPORT_GFX_DMG                  (1 << 2)
 152 #define AMD_PG_SUPPORT_UVD                      (1 << 3)
 153 #define AMD_PG_SUPPORT_VCE                      (1 << 4)
 154 #define AMD_PG_SUPPORT_CP                       (1 << 5)
 155 #define AMD_PG_SUPPORT_GDS                      (1 << 6)
 156 #define AMD_PG_SUPPORT_RLC_SMU_HS               (1 << 7)
 157 #define AMD_PG_SUPPORT_SDMA                     (1 << 8)
 158 #define AMD_PG_SUPPORT_ACP                      (1 << 9)
 159 #define AMD_PG_SUPPORT_SAMU                     (1 << 10)
 160 #define AMD_PG_SUPPORT_GFX_QUICK_MG             (1 << 11)
 161 #define AMD_PG_SUPPORT_GFX_PIPELINE             (1 << 12)
 162 #define AMD_PG_SUPPORT_MMHUB                    (1 << 13)
 163 #define AMD_PG_SUPPORT_VCN                      (1 << 14)
 164 #define AMD_PG_SUPPORT_VCN_DPG                  (1 << 15)
 165 #define AMD_PG_SUPPORT_ATHUB                    (1 << 16)
 166 #define AMD_PG_SUPPORT_JPEG                     (1 << 17)
 167
 168 /**
 169  * enum PP_FEATURE_MASK - Used to mask power play features.
 170  *
 171  * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
 172  * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
 173  * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
 174  * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.
 175  * @PP_POWER_CONTAINMENT_MASK: Power containment.
 176  * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.
 177  * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.
 178  * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.
 179  * @PP_ULV_MASK: Ultra low voltage.
 180  * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.
 181  * @PP_CLOCK_STRETCH_MASK: Clock stretching.
 182  * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.
 183  * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
 184  * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.
 185  * @PP_OVERDRIVE_MASK: Over- and under-clocking support.
 186  * @PP_GFXOFF_MASK: Dynamic graphics engine power control.
 187  * @PP_ACG_MASK: Adaptive clock generator.
 188  * @PP_STUTTER_MODE: Stutter mode.
 189  * @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
 190  *
 191  * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to
 192  * the kernel's command line parameters. This is usually done through a system's
 193  * boot loader (E.g. GRUB). If manually loading the driver, pass
 194  * ppfeaturemask=<mask> as a modprobe parameter.
 195  */
 196 enum PP_FEATURE_MASK {
 197         PP_SCLK_DPM_MASK = 0x1,
 198         PP_MCLK_DPM_MASK = 0x2,
 199         PP_PCIE_DPM_MASK = 0x4,
 200         PP_SCLK_DEEP_SLEEP_MASK = 0x8,
 201         PP_POWER_CONTAINMENT_MASK = 0x10,
 202         PP_UVD_HANDSHAKE_MASK = 0x20,
 203         PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
 204         PP_VBI_TIME_SUPPORT_MASK = 0x80,
 205         PP_ULV_MASK = 0x100,
 206         PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
 207         PP_CLOCK_STRETCH_MASK = 0x400,
 208         PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
 209         PP_SOCCLK_DPM_MASK = 0x1000,
 210         PP_DCEFCLK_DPM_MASK = 0x2000,
 211         PP_OVERDRIVE_MASK = 0x4000,
 212         PP_GFXOFF_MASK = 0x8000,
 213         PP_ACG_MASK = 0x10000,
 214         PP_STUTTER_MODE = 0x20000,
 215         PP_AVFS_MASK = 0x40000,
 216 };
 217
 218 enum DC_FEATURE_MASK {
 219         DC_FBC_MASK = 0x1,
 220         DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
 221         DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
 222         DC_PSR_MASK = 0x8,
 223 };
 224
 225 enum DC_DEBUG_MASK {
 226         DC_DISABLE_PIPE_SPLIT = 0x1,
 227         DC_DISABLE_STUTTER = 0x2,
 228         DC_DISABLE_DSC = 0x4,
 229         DC_DISABLE_CLOCK_GATING = 0x8
 230 };
 231
 232 enum amd_dpm_forced_level;
 233
 234 /**
 235  * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
 236  * @name: Name of IP block
 237  * @early_init: sets up early driver state (pre sw_init),
 238  *              does not configure hw - Optional
 239  * @late_init: sets up late driver/hw state (post hw_init) - Optional
 240  * @sw_init: sets up driver state, does not configure hw
 241  * @sw_fini: tears down driver state, does not configure hw
 242  * @hw_init: sets up the hw state
 243  * @hw_fini: tears down the hw state
 244  * @late_fini: final cleanup
 245  * @suspend: handles IP specific hw/sw changes for suspend
 246  * @resume: handles IP specific hw/sw changes for resume
 247  * @is_idle: returns current IP block idle status
 248  * @wait_for_idle: poll for idle
 249  * @check_soft_reset: check soft reset the IP block
 250  * @pre_soft_reset: pre soft reset the IP block
 251  * @soft_reset: soft reset the IP block
 252  * @post_soft_reset: post soft reset the IP block
 253  * @set_clockgating_state: enable/disable cg for the IP block
 254  * @set_powergating_state: enable/disable pg for the IP block
 255  * @get_clockgating_state: get current clockgating status
 256  * @enable_umd_pstate: enable UMD powerstate
 257  *
 258  * These hooks provide an interface for controlling the operational state
 259  * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
 260  * the driver can make chip-wide state changes by walking this list and
 261  * making calls to hooks from each IP block. This list is ordered to ensure
 262  * that the driver initializes the IP blocks in a safe sequence.
 263  */
 264 struct amd_ip_funcs {
 265         char *name;
 266         int (*early_init)(void *handle);
 267         int (*late_init)(void *handle);
 268         int (*sw_init)(void *handle);
 269         int (*sw_fini)(void *handle);
 270         int (*hw_init)(void *handle);
 271         int (*hw_fini)(void *handle);
 272         void (*late_fini)(void *handle);
 273         int (*suspend)(void *handle);
 274         int (*resume)(void *handle);
 275         bool (*is_idle)(void *handle);
 276         int (*wait_for_idle)(void *handle);
 277         bool (*check_soft_reset)(void *handle);
 278         int (*pre_soft_reset)(void *handle);
 279         int (*soft_reset)(void *handle);
 280         int (*post_soft_reset)(void *handle);
 281         int (*set_clockgating_state)(void *handle,
 282                                      enum amd_clockgating_state state);
 283         int (*set_powergating_state)(void *handle,
 284                                      enum amd_powergating_state state);
 285         void (*get_clockgating_state)(void *handle, u32 *flags);
 286         int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level);
 287 };
 288
 289
 290 #endif /* __AMD_SHARED_H__ */