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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / amd / include / vega10_ip_offset.h
blob3a22a5d169193fadf712ba39e4af419a14f1aea9
1 /*
2 * Copyright (C) 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21 #ifndef _vega10_ip_offset_HEADER
22 #define _vega10_ip_offset_HEADER
23
24 #define MAX_INSTANCE 5
25 #define MAX_SEGMENT 5
26
27 struct IP_BASE_INSTANCE
28 {
29 unsigned int segment[MAX_SEGMENT];
30 };
31
32 struct IP_BASE
33 {
34 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
35 };
36
37
38 static const struct IP_BASE __maybe_unused NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } } } };
43 static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } } } };
48 static const struct IP_BASE __maybe_unused DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
49 { { 0, 0, 0, 0, 0 } },
50 { { 0, 0, 0, 0, 0 } },
51 { { 0, 0, 0, 0, 0 } },
52 { { 0, 0, 0, 0, 0 } } } };
53 static const struct IP_BASE __maybe_unused DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
54 { { 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0 } } } };
58 static const struct IP_BASE __maybe_unused MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0 } },
60 { { 0, 0, 0, 0, 0 } },
61 { { 0, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0 } } } };
63 static const struct IP_BASE __maybe_unused MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0 } },
67 { { 0, 0, 0, 0, 0 } } } };
68 static const struct IP_BASE __maybe_unused MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0 } },
71 { { 0, 0, 0, 0, 0 } },
72 { { 0, 0, 0, 0, 0 } } } };
73 static const struct IP_BASE __maybe_unused DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
74 { { 0, 0, 0, 0, 0 } },
75 { { 0, 0, 0, 0, 0 } },
76 { { 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0 } } } };
78 static const struct IP_BASE __maybe_unused UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
79 { { 0, 0, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0 } },
81 { { 0, 0, 0, 0, 0 } },
82 { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
83 static const struct IP_BASE __maybe_unused VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0 } },
86 { { 0, 0, 0, 0, 0 } },
87 { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
88 static const struct IP_BASE __maybe_unused DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
89 { { 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0 } } } }; // not exist
93 static const struct IP_BASE __maybe_unused DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0 } },
95 { { 0, 0, 0, 0, 0 } },
96 { { 0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0 } } } }; // not exist
98 static const struct IP_BASE __maybe_unused DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0 } },
100 { { 0, 0, 0, 0, 0 } },
101 { { 0, 0, 0, 0, 0 } },
102 { { 0, 0, 0, 0, 0 } } } }; // not exist
103 static const struct IP_BASE __maybe_unused DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0 } } } }; // not exist
108 static const struct IP_BASE __maybe_unused DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
109 { { 0, 0, 0, 0, 0 } },
110 { { 0, 0, 0, 0, 0 } },
111 { { 0, 0, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
113 static const struct IP_BASE __maybe_unused ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0 } },
116 { { 0, 0, 0, 0, 0 } },
117 { { 0, 0, 0, 0, 0 } } } }; // not exist
118 static const struct IP_BASE __maybe_unused SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0 } },
121 { { 0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0 } } } }; // not exist
123 static const struct IP_BASE __maybe_unused L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
124 { { 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0 } } } };
128 static const struct IP_BASE __maybe_unused IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0 } } } };
133 static const struct IP_BASE __maybe_unused ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0 } },
135 { { 0, 0, 0, 0, 0 } },
136 { { 0, 0, 0, 0, 0 } },
137 { { 0, 0, 0, 0, 0 } } } };
138 static const struct IP_BASE __maybe_unused VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
139 { { 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0 } },
141 { { 0, 0, 0, 0, 0 } },
142 { { 0, 0, 0, 0, 0 } } } };
143 static const struct IP_BASE __maybe_unused GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
144 { { 0, 0, 0, 0, 0 } },
145 { { 0, 0, 0, 0, 0 } },
146 { { 0, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0 } } } };
148 static const struct IP_BASE __maybe_unused MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
149 { { 0, 0, 0, 0, 0 } },
150 { { 0, 0, 0, 0, 0 } },
151 { { 0, 0, 0, 0, 0 } },
152 { { 0, 0, 0, 0, 0 } } } };
153 static const struct IP_BASE __maybe_unused RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
154 { { 0, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0 } },
156 { { 0, 0, 0, 0, 0 } },
157 { { 0, 0, 0, 0, 0 } } } };
158 static const struct IP_BASE __maybe_unused HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
159 { { 0, 0, 0, 0, 0 } },
160 { { 0, 0, 0, 0, 0 } },
161 { { 0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0 } } } };
163 static const struct IP_BASE __maybe_unused OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
164 { { 0, 0, 0, 0, 0 } },
165 { { 0, 0, 0, 0, 0 } },
166 { { 0, 0, 0, 0, 0 } },
167 { { 0, 0, 0, 0, 0 } } } };
168 static const struct IP_BASE __maybe_unused SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
169 { { 0, 0, 0, 0, 0 } },
170 { { 0, 0, 0, 0, 0 } },
171 { { 0, 0, 0, 0, 0 } },
172 { { 0, 0, 0, 0, 0 } } } };
173 static const struct IP_BASE __maybe_unused SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
174 { { 0, 0, 0, 0, 0 } },
175 { { 0, 0, 0, 0, 0 } },
176 { { 0, 0, 0, 0, 0 } },
177 { { 0, 0, 0, 0, 0 } } } };
178 static const struct IP_BASE __maybe_unused XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
179 { { 0, 0, 0, 0, 0 } },
180 { { 0, 0, 0, 0, 0 } },
181 { { 0, 0, 0, 0, 0 } },
182 { { 0, 0, 0, 0, 0 } } } };
183 static const struct IP_BASE __maybe_unused UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
184 { { 0, 0, 0, 0, 0 } },
185 { { 0, 0, 0, 0, 0 } },
186 { { 0, 0, 0, 0, 0 } },
187 { { 0, 0, 0, 0, 0 } } } };
188 static const struct IP_BASE __maybe_unused THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
189 { { 0, 0, 0, 0, 0 } },
190 { { 0, 0, 0, 0, 0 } },
191 { { 0, 0, 0, 0, 0 } },
192 { { 0, 0, 0, 0, 0 } } } };
193 static const struct IP_BASE __maybe_unused SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
194 { { 0, 0, 0, 0, 0 } },
195 { { 0, 0, 0, 0, 0 } },
196 { { 0, 0, 0, 0, 0 } },
197 { { 0, 0, 0, 0, 0 } } } };
198 static const struct IP_BASE __maybe_unused PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
199 { { 0, 0, 0, 0, 0 } },
200 { { 0, 0, 0, 0, 0 } },
201 { { 0, 0, 0, 0, 0 } },
202 { { 0, 0, 0, 0, 0 } } } };
203 static const struct IP_BASE __maybe_unused CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
204 { { 0x00016E00, 0, 0, 0, 0 } },
205 { { 0x00017000, 0, 0, 0, 0 } },
206 { { 0x00017200, 0, 0, 0, 0 } },
207 { { 0x00017E00, 0, 0, 0, 0 } } } };
208 static const struct IP_BASE __maybe_unused FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
209 { { 0, 0, 0, 0, 0 } },
210 { { 0, 0, 0, 0, 0 } },
211 { { 0, 0, 0, 0, 0 } },
212 { { 0, 0, 0, 0, 0 } } } };
213
214
215 #define NBIF_BASE__INST0_SEG0 0x00000000
216 #define NBIF_BASE__INST0_SEG1 0x00000014
217 #define NBIF_BASE__INST0_SEG2 0x00000D20
218 #define NBIF_BASE__INST0_SEG3 0x00010400
219 #define NBIF_BASE__INST0_SEG4 0
220
221 #define NBIF_BASE__INST1_SEG0 0
222 #define NBIF_BASE__INST1_SEG1 0
223 #define NBIF_BASE__INST1_SEG2 0
224 #define NBIF_BASE__INST1_SEG3 0
225 #define NBIF_BASE__INST1_SEG4 0
226
227 #define NBIF_BASE__INST2_SEG0 0
228 #define NBIF_BASE__INST2_SEG1 0
229 #define NBIF_BASE__INST2_SEG2 0
230 #define NBIF_BASE__INST2_SEG3 0
231 #define NBIF_BASE__INST2_SEG4 0
232
233 #define NBIF_BASE__INST3_SEG0 0
234 #define NBIF_BASE__INST3_SEG1 0
235 #define NBIF_BASE__INST3_SEG2 0
236 #define NBIF_BASE__INST3_SEG3 0
237 #define NBIF_BASE__INST3_SEG4 0
238
239 #define NBIF_BASE__INST4_SEG0 0
240 #define NBIF_BASE__INST4_SEG1 0
241 #define NBIF_BASE__INST4_SEG2 0
242 #define NBIF_BASE__INST4_SEG3 0
243 #define NBIF_BASE__INST4_SEG4 0
244
245 #define NBIO_BASE__INST0_SEG0 0x00000000
246 #define NBIO_BASE__INST0_SEG1 0x00000014
247 #define NBIO_BASE__INST0_SEG2 0x00000D20
248 #define NBIO_BASE__INST0_SEG3 0x00010400
249 #define NBIO_BASE__INST0_SEG4 0
250
251 #define NBIO_BASE__INST1_SEG0 0
252 #define NBIO_BASE__INST1_SEG1 0
253 #define NBIO_BASE__INST1_SEG2 0
254 #define NBIO_BASE__INST1_SEG3 0
255 #define NBIO_BASE__INST1_SEG4 0
256
257 #define NBIO_BASE__INST2_SEG0 0
258 #define NBIO_BASE__INST2_SEG1 0
259 #define NBIO_BASE__INST2_SEG2 0
260 #define NBIO_BASE__INST2_SEG3 0
261 #define NBIO_BASE__INST2_SEG4 0
262
263 #define NBIO_BASE__INST3_SEG0 0
264 #define NBIO_BASE__INST3_SEG1 0
265 #define NBIO_BASE__INST3_SEG2 0
266 #define NBIO_BASE__INST3_SEG3 0
267 #define NBIO_BASE__INST3_SEG4 0
268
269 #define NBIO_BASE__INST4_SEG0 0
270 #define NBIO_BASE__INST4_SEG1 0
271 #define NBIO_BASE__INST4_SEG2 0
272 #define NBIO_BASE__INST4_SEG3 0
273 #define NBIO_BASE__INST4_SEG4 0
274
275 #define DCE_BASE__INST0_SEG0 0x00000012
276 #define DCE_BASE__INST0_SEG1 0x000000C0
277 #define DCE_BASE__INST0_SEG2 0x000034C0
278 #define DCE_BASE__INST0_SEG3 0
279 #define DCE_BASE__INST0_SEG4 0
280
281 #define DCE_BASE__INST1_SEG0 0
282 #define DCE_BASE__INST1_SEG1 0
283 #define DCE_BASE__INST1_SEG2 0
284 #define DCE_BASE__INST1_SEG3 0
285 #define DCE_BASE__INST1_SEG4 0
286
287 #define DCE_BASE__INST2_SEG0 0
288 #define DCE_BASE__INST2_SEG1 0
289 #define DCE_BASE__INST2_SEG2 0
290 #define DCE_BASE__INST2_SEG3 0
291 #define DCE_BASE__INST2_SEG4 0
292
293 #define DCE_BASE__INST3_SEG0 0
294 #define DCE_BASE__INST3_SEG1 0
295 #define DCE_BASE__INST3_SEG2 0
296 #define DCE_BASE__INST3_SEG3 0
297 #define DCE_BASE__INST3_SEG4 0
298
299 #define DCE_BASE__INST4_SEG0 0
300 #define DCE_BASE__INST4_SEG1 0
301 #define DCE_BASE__INST4_SEG2 0
302 #define DCE_BASE__INST4_SEG3 0
303 #define DCE_BASE__INST4_SEG4 0
304
305 #define DCN_BASE__INST0_SEG0 0x00000012
306 #define DCN_BASE__INST0_SEG1 0x000000C0
307 #define DCN_BASE__INST0_SEG2 0x000034C0
308 #define DCN_BASE__INST0_SEG3 0
309 #define DCN_BASE__INST0_SEG4 0
310
311 #define DCN_BASE__INST1_SEG0 0
312 #define DCN_BASE__INST1_SEG1 0
313 #define DCN_BASE__INST1_SEG2 0
314 #define DCN_BASE__INST1_SEG3 0
315 #define DCN_BASE__INST1_SEG4 0
316
317 #define DCN_BASE__INST2_SEG0 0
318 #define DCN_BASE__INST2_SEG1 0
319 #define DCN_BASE__INST2_SEG2 0
320 #define DCN_BASE__INST2_SEG3 0
321 #define DCN_BASE__INST2_SEG4 0
322
323 #define DCN_BASE__INST3_SEG0 0
324 #define DCN_BASE__INST3_SEG1 0
325 #define DCN_BASE__INST3_SEG2 0
326 #define DCN_BASE__INST3_SEG3 0
327 #define DCN_BASE__INST3_SEG4 0
328
329 #define DCN_BASE__INST4_SEG0 0
330 #define DCN_BASE__INST4_SEG1 0
331 #define DCN_BASE__INST4_SEG2 0
332 #define DCN_BASE__INST4_SEG3 0
333 #define DCN_BASE__INST4_SEG4 0
334
335 #define MP0_BASE__INST0_SEG0 0x00016000
336 #define MP0_BASE__INST0_SEG1 0
337 #define MP0_BASE__INST0_SEG2 0
338 #define MP0_BASE__INST0_SEG3 0
339 #define MP0_BASE__INST0_SEG4 0
340
341 #define MP0_BASE__INST1_SEG0 0
342 #define MP0_BASE__INST1_SEG1 0
343 #define MP0_BASE__INST1_SEG2 0
344 #define MP0_BASE__INST1_SEG3 0
345 #define MP0_BASE__INST1_SEG4 0
346
347 #define MP0_BASE__INST2_SEG0 0
348 #define MP0_BASE__INST2_SEG1 0
349 #define MP0_BASE__INST2_SEG2 0
350 #define MP0_BASE__INST2_SEG3 0
351 #define MP0_BASE__INST2_SEG4 0
352
353 #define MP0_BASE__INST3_SEG0 0
354 #define MP0_BASE__INST3_SEG1 0
355 #define MP0_BASE__INST3_SEG2 0
356 #define MP0_BASE__INST3_SEG3 0
357 #define MP0_BASE__INST3_SEG4 0
358
359 #define MP0_BASE__INST4_SEG0 0
360 #define MP0_BASE__INST4_SEG1 0
361 #define MP0_BASE__INST4_SEG2 0
362 #define MP0_BASE__INST4_SEG3 0
363 #define MP0_BASE__INST4_SEG4 0
364
365 #define MP1_BASE__INST0_SEG0 0x00016200
366 #define MP1_BASE__INST0_SEG1 0
367 #define MP1_BASE__INST0_SEG2 0
368 #define MP1_BASE__INST0_SEG3 0
369 #define MP1_BASE__INST0_SEG4 0
370
371 #define MP1_BASE__INST1_SEG0 0
372 #define MP1_BASE__INST1_SEG1 0
373 #define MP1_BASE__INST1_SEG2 0
374 #define MP1_BASE__INST1_SEG3 0
375 #define MP1_BASE__INST1_SEG4 0
376
377 #define MP1_BASE__INST2_SEG0 0
378 #define MP1_BASE__INST2_SEG1 0
379 #define MP1_BASE__INST2_SEG2 0
380 #define MP1_BASE__INST2_SEG3 0
381 #define MP1_BASE__INST2_SEG4 0
382
383 #define MP1_BASE__INST3_SEG0 0
384 #define MP1_BASE__INST3_SEG1 0
385 #define MP1_BASE__INST3_SEG2 0
386 #define MP1_BASE__INST3_SEG3 0
387 #define MP1_BASE__INST3_SEG4 0
388
389 #define MP1_BASE__INST4_SEG0 0
390 #define MP1_BASE__INST4_SEG1 0
391 #define MP1_BASE__INST4_SEG2 0
392 #define MP1_BASE__INST4_SEG3 0
393 #define MP1_BASE__INST4_SEG4 0
394
395 #define MP2_BASE__INST0_SEG0 0x00016400
396 #define MP2_BASE__INST0_SEG1 0
397 #define MP2_BASE__INST0_SEG2 0
398 #define MP2_BASE__INST0_SEG3 0
399 #define MP2_BASE__INST0_SEG4 0
400
401 #define MP2_BASE__INST1_SEG0 0
402 #define MP2_BASE__INST1_SEG1 0
403 #define MP2_BASE__INST1_SEG2 0
404 #define MP2_BASE__INST1_SEG3 0
405 #define MP2_BASE__INST1_SEG4 0
406
407 #define MP2_BASE__INST2_SEG0 0
408 #define MP2_BASE__INST2_SEG1 0
409 #define MP2_BASE__INST2_SEG2 0
410 #define MP2_BASE__INST2_SEG3 0
411 #define MP2_BASE__INST2_SEG4 0
412
413 #define MP2_BASE__INST3_SEG0 0
414 #define MP2_BASE__INST3_SEG1 0
415 #define MP2_BASE__INST3_SEG2 0
416 #define MP2_BASE__INST3_SEG3 0
417 #define MP2_BASE__INST3_SEG4 0
418
419 #define MP2_BASE__INST4_SEG0 0
420 #define MP2_BASE__INST4_SEG1 0
421 #define MP2_BASE__INST4_SEG2 0
422 #define MP2_BASE__INST4_SEG3 0
423 #define MP2_BASE__INST4_SEG4 0
424
425 #define DF_BASE__INST0_SEG0 0x00007000
426 #define DF_BASE__INST0_SEG1 0
427 #define DF_BASE__INST0_SEG2 0
428 #define DF_BASE__INST0_SEG3 0
429 #define DF_BASE__INST0_SEG4 0
430
431 #define DF_BASE__INST1_SEG0 0
432 #define DF_BASE__INST1_SEG1 0
433 #define DF_BASE__INST1_SEG2 0
434 #define DF_BASE__INST1_SEG3 0
435 #define DF_BASE__INST1_SEG4 0
436
437 #define DF_BASE__INST2_SEG0 0
438 #define DF_BASE__INST2_SEG1 0
439 #define DF_BASE__INST2_SEG2 0
440 #define DF_BASE__INST2_SEG3 0
441 #define DF_BASE__INST2_SEG4 0
442
443 #define DF_BASE__INST3_SEG0 0
444 #define DF_BASE__INST3_SEG1 0
445 #define DF_BASE__INST3_SEG2 0
446 #define DF_BASE__INST3_SEG3 0
447 #define DF_BASE__INST3_SEG4 0
448
449 #define DF_BASE__INST4_SEG0 0
450 #define DF_BASE__INST4_SEG1 0
451 #define DF_BASE__INST4_SEG2 0
452 #define DF_BASE__INST4_SEG3 0
453 #define DF_BASE__INST4_SEG4 0
454
455 #define UVD_BASE__INST0_SEG0 0x00007800
456 #define UVD_BASE__INST0_SEG1 0x00007E00
457 #define UVD_BASE__INST0_SEG2 0
458 #define UVD_BASE__INST0_SEG3 0
459 #define UVD_BASE__INST0_SEG4 0
460
461 #define UVD_BASE__INST1_SEG0 0
462 #define UVD_BASE__INST1_SEG1 0
463 #define UVD_BASE__INST1_SEG2 0
464 #define UVD_BASE__INST1_SEG3 0
465 #define UVD_BASE__INST1_SEG4 0
466
467 #define UVD_BASE__INST2_SEG0 0
468 #define UVD_BASE__INST2_SEG1 0
469 #define UVD_BASE__INST2_SEG2 0
470 #define UVD_BASE__INST2_SEG3 0
471 #define UVD_BASE__INST2_SEG4 0
472
473 #define UVD_BASE__INST3_SEG0 0
474 #define UVD_BASE__INST3_SEG1 0
475 #define UVD_BASE__INST3_SEG2 0
476 #define UVD_BASE__INST3_SEG3 0
477 #define UVD_BASE__INST3_SEG4 0
478
479 #define UVD_BASE__INST4_SEG0 0
480 #define UVD_BASE__INST4_SEG1 0
481 #define UVD_BASE__INST4_SEG2 0
482 #define UVD_BASE__INST4_SEG3 0
483 #define UVD_BASE__INST4_SEG4 0
484
485 #define VCN_BASE__INST0_SEG0 0x00007800
486 #define VCN_BASE__INST0_SEG1 0x00007E00
487 #define VCN_BASE__INST0_SEG2 0
488 #define VCN_BASE__INST0_SEG3 0
489 #define VCN_BASE__INST0_SEG4 0
490
491 #define VCN_BASE__INST1_SEG0 0
492 #define VCN_BASE__INST1_SEG1 0
493 #define VCN_BASE__INST1_SEG2 0
494 #define VCN_BASE__INST1_SEG3 0
495 #define VCN_BASE__INST1_SEG4 0
496
497 #define VCN_BASE__INST2_SEG0 0
498 #define VCN_BASE__INST2_SEG1 0
499 #define VCN_BASE__INST2_SEG2 0
500 #define VCN_BASE__INST2_SEG3 0
501 #define VCN_BASE__INST2_SEG4 0
502
503 #define VCN_BASE__INST3_SEG0 0
504 #define VCN_BASE__INST3_SEG1 0
505 #define VCN_BASE__INST3_SEG2 0
506 #define VCN_BASE__INST3_SEG3 0
507 #define VCN_BASE__INST3_SEG4 0
508
509 #define VCN_BASE__INST4_SEG0 0
510 #define VCN_BASE__INST4_SEG1 0
511 #define VCN_BASE__INST4_SEG2 0
512 #define VCN_BASE__INST4_SEG3 0
513 #define VCN_BASE__INST4_SEG4 0
514
515 #define DBGU_BASE__INST0_SEG0 0x00000180
516 #define DBGU_BASE__INST0_SEG1 0x000001A0
517 #define DBGU_BASE__INST0_SEG2 0
518 #define DBGU_BASE__INST0_SEG3 0
519 #define DBGU_BASE__INST0_SEG4 0
520
521 #define DBGU_BASE__INST1_SEG0 0
522 #define DBGU_BASE__INST1_SEG1 0
523 #define DBGU_BASE__INST1_SEG2 0
524 #define DBGU_BASE__INST1_SEG3 0
525 #define DBGU_BASE__INST1_SEG4 0
526
527 #define DBGU_BASE__INST2_SEG0 0
528 #define DBGU_BASE__INST2_SEG1 0
529 #define DBGU_BASE__INST2_SEG2 0
530 #define DBGU_BASE__INST2_SEG3 0
531 #define DBGU_BASE__INST2_SEG4 0
532
533 #define DBGU_BASE__INST3_SEG0 0
534 #define DBGU_BASE__INST3_SEG1 0
535 #define DBGU_BASE__INST3_SEG2 0
536 #define DBGU_BASE__INST3_SEG3 0
537 #define DBGU_BASE__INST3_SEG4 0
538
539 #define DBGU_BASE__INST4_SEG0 0
540 #define DBGU_BASE__INST4_SEG1 0
541 #define DBGU_BASE__INST4_SEG2 0
542 #define DBGU_BASE__INST4_SEG3 0
543 #define DBGU_BASE__INST4_SEG4 0
544
545 #define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
546 #define DBGU_NBIO_BASE__INST0_SEG1 0
547 #define DBGU_NBIO_BASE__INST0_SEG2 0
548 #define DBGU_NBIO_BASE__INST0_SEG3 0
549 #define DBGU_NBIO_BASE__INST0_SEG4 0
550
551 #define DBGU_NBIO_BASE__INST1_SEG0 0
552 #define DBGU_NBIO_BASE__INST1_SEG1 0
553 #define DBGU_NBIO_BASE__INST1_SEG2 0
554 #define DBGU_NBIO_BASE__INST1_SEG3 0
555 #define DBGU_NBIO_BASE__INST1_SEG4 0
556
557 #define DBGU_NBIO_BASE__INST2_SEG0 0
558 #define DBGU_NBIO_BASE__INST2_SEG1 0
559 #define DBGU_NBIO_BASE__INST2_SEG2 0
560 #define DBGU_NBIO_BASE__INST2_SEG3 0
561 #define DBGU_NBIO_BASE__INST2_SEG4 0
562
563 #define DBGU_NBIO_BASE__INST3_SEG0 0
564 #define DBGU_NBIO_BASE__INST3_SEG1 0
565 #define DBGU_NBIO_BASE__INST3_SEG2 0
566 #define DBGU_NBIO_BASE__INST3_SEG3 0
567 #define DBGU_NBIO_BASE__INST3_SEG4 0
568
569 #define DBGU_NBIO_BASE__INST4_SEG0 0
570 #define DBGU_NBIO_BASE__INST4_SEG1 0
571 #define DBGU_NBIO_BASE__INST4_SEG2 0
572 #define DBGU_NBIO_BASE__INST4_SEG3 0
573 #define DBGU_NBIO_BASE__INST4_SEG4 0
574
575 #define DBGU_IO_BASE__INST0_SEG0 0x000001E0
576 #define DBGU_IO_BASE__INST0_SEG1 0
577 #define DBGU_IO_BASE__INST0_SEG2 0
578 #define DBGU_IO_BASE__INST0_SEG3 0
579 #define DBGU_IO_BASE__INST0_SEG4 0
580
581 #define DBGU_IO_BASE__INST1_SEG0 0
582 #define DBGU_IO_BASE__INST1_SEG1 0
583 #define DBGU_IO_BASE__INST1_SEG2 0
584 #define DBGU_IO_BASE__INST1_SEG3 0
585 #define DBGU_IO_BASE__INST1_SEG4 0
586
587 #define DBGU_IO_BASE__INST2_SEG0 0
588 #define DBGU_IO_BASE__INST2_SEG1 0
589 #define DBGU_IO_BASE__INST2_SEG2 0
590 #define DBGU_IO_BASE__INST2_SEG3 0
591 #define DBGU_IO_BASE__INST2_SEG4 0
592
593 #define DBGU_IO_BASE__INST3_SEG0 0
594 #define DBGU_IO_BASE__INST3_SEG1 0
595 #define DBGU_IO_BASE__INST3_SEG2 0
596 #define DBGU_IO_BASE__INST3_SEG3 0
597 #define DBGU_IO_BASE__INST3_SEG4 0
598
599 #define DBGU_IO_BASE__INST4_SEG0 0
600 #define DBGU_IO_BASE__INST4_SEG1 0
601 #define DBGU_IO_BASE__INST4_SEG2 0
602 #define DBGU_IO_BASE__INST4_SEG3 0
603 #define DBGU_IO_BASE__INST4_SEG4 0
604
605 #define DFX_DAP_BASE__INST0_SEG0 0x000005A0
606 #define DFX_DAP_BASE__INST0_SEG1 0
607 #define DFX_DAP_BASE__INST0_SEG2 0
608 #define DFX_DAP_BASE__INST0_SEG3 0
609 #define DFX_DAP_BASE__INST0_SEG4 0
610
611 #define DFX_DAP_BASE__INST1_SEG0 0
612 #define DFX_DAP_BASE__INST1_SEG1 0
613 #define DFX_DAP_BASE__INST1_SEG2 0
614 #define DFX_DAP_BASE__INST1_SEG3 0
615 #define DFX_DAP_BASE__INST1_SEG4 0
616
617 #define DFX_DAP_BASE__INST2_SEG0 0
618 #define DFX_DAP_BASE__INST2_SEG1 0
619 #define DFX_DAP_BASE__INST2_SEG2 0
620 #define DFX_DAP_BASE__INST2_SEG3 0
621 #define DFX_DAP_BASE__INST2_SEG4 0
622
623 #define DFX_DAP_BASE__INST3_SEG0 0
624 #define DFX_DAP_BASE__INST3_SEG1 0
625 #define DFX_DAP_BASE__INST3_SEG2 0
626 #define DFX_DAP_BASE__INST3_SEG3 0
627 #define DFX_DAP_BASE__INST3_SEG4 0
628
629 #define DFX_DAP_BASE__INST4_SEG0 0
630 #define DFX_DAP_BASE__INST4_SEG1 0
631 #define DFX_DAP_BASE__INST4_SEG2 0
632 #define DFX_DAP_BASE__INST4_SEG3 0
633 #define DFX_DAP_BASE__INST4_SEG4 0
634
635 #define DFX_BASE__INST0_SEG0 0x00000580
636 #define DFX_BASE__INST0_SEG1 0
637 #define DFX_BASE__INST0_SEG2 0
638 #define DFX_BASE__INST0_SEG3 0
639 #define DFX_BASE__INST0_SEG4 0
640
641 #define DFX_BASE__INST1_SEG0 0
642 #define DFX_BASE__INST1_SEG1 0
643 #define DFX_BASE__INST1_SEG2 0
644 #define DFX_BASE__INST1_SEG3 0
645 #define DFX_BASE__INST1_SEG4 0
646
647 #define DFX_BASE__INST2_SEG0 0
648 #define DFX_BASE__INST2_SEG1 0
649 #define DFX_BASE__INST2_SEG2 0
650 #define DFX_BASE__INST2_SEG3 0
651 #define DFX_BASE__INST2_SEG4 0
652
653 #define DFX_BASE__INST3_SEG0 0
654 #define DFX_BASE__INST3_SEG1 0
655 #define DFX_BASE__INST3_SEG2 0
656 #define DFX_BASE__INST3_SEG3 0
657 #define DFX_BASE__INST3_SEG4 0
658
659 #define DFX_BASE__INST4_SEG0 0
660 #define DFX_BASE__INST4_SEG1 0
661 #define DFX_BASE__INST4_SEG2 0
662 #define DFX_BASE__INST4_SEG3 0
663 #define DFX_BASE__INST4_SEG4 0
664
665 #define ISP_BASE__INST0_SEG0 0x00018000
666 #define ISP_BASE__INST0_SEG1 0
667 #define ISP_BASE__INST0_SEG2 0
668 #define ISP_BASE__INST0_SEG3 0
669 #define ISP_BASE__INST0_SEG4 0
670
671 #define ISP_BASE__INST1_SEG0 0
672 #define ISP_BASE__INST1_SEG1 0
673 #define ISP_BASE__INST1_SEG2 0
674 #define ISP_BASE__INST1_SEG3 0
675 #define ISP_BASE__INST1_SEG4 0
676
677 #define ISP_BASE__INST2_SEG0 0
678 #define ISP_BASE__INST2_SEG1 0
679 #define ISP_BASE__INST2_SEG2 0
680 #define ISP_BASE__INST2_SEG3 0
681 #define ISP_BASE__INST2_SEG4 0
682
683 #define ISP_BASE__INST3_SEG0 0
684 #define ISP_BASE__INST3_SEG1 0
685 #define ISP_BASE__INST3_SEG2 0
686 #define ISP_BASE__INST3_SEG3 0
687 #define ISP_BASE__INST3_SEG4 0
688
689 #define ISP_BASE__INST4_SEG0 0
690 #define ISP_BASE__INST4_SEG1 0
691 #define ISP_BASE__INST4_SEG2 0
692 #define ISP_BASE__INST4_SEG3 0
693 #define ISP_BASE__INST4_SEG4 0
694
695 #define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
696 #define SYSTEMHUB_BASE__INST0_SEG1 0
697 #define SYSTEMHUB_BASE__INST0_SEG2 0
698 #define SYSTEMHUB_BASE__INST0_SEG3 0
699 #define SYSTEMHUB_BASE__INST0_SEG4 0
700
701 #define SYSTEMHUB_BASE__INST1_SEG0 0
702 #define SYSTEMHUB_BASE__INST1_SEG1 0
703 #define SYSTEMHUB_BASE__INST1_SEG2 0
704 #define SYSTEMHUB_BASE__INST1_SEG3 0
705 #define SYSTEMHUB_BASE__INST1_SEG4 0
706
707 #define SYSTEMHUB_BASE__INST2_SEG0 0
708 #define SYSTEMHUB_BASE__INST2_SEG1 0
709 #define SYSTEMHUB_BASE__INST2_SEG2 0
710 #define SYSTEMHUB_BASE__INST2_SEG3 0
711 #define SYSTEMHUB_BASE__INST2_SEG4 0
712
713 #define SYSTEMHUB_BASE__INST3_SEG0 0
714 #define SYSTEMHUB_BASE__INST3_SEG1 0
715 #define SYSTEMHUB_BASE__INST3_SEG2 0
716 #define SYSTEMHUB_BASE__INST3_SEG3 0
717 #define SYSTEMHUB_BASE__INST3_SEG4 0
718
719 #define SYSTEMHUB_BASE__INST4_SEG0 0
720 #define SYSTEMHUB_BASE__INST4_SEG1 0
721 #define SYSTEMHUB_BASE__INST4_SEG2 0
722 #define SYSTEMHUB_BASE__INST4_SEG3 0
723 #define SYSTEMHUB_BASE__INST4_SEG4 0
724
725 #define L2IMU_BASE__INST0_SEG0 0x00007DC0
726 #define L2IMU_BASE__INST0_SEG1 0
727 #define L2IMU_BASE__INST0_SEG2 0
728 #define L2IMU_BASE__INST0_SEG3 0
729 #define L2IMU_BASE__INST0_SEG4 0
730
731 #define L2IMU_BASE__INST1_SEG0 0
732 #define L2IMU_BASE__INST1_SEG1 0
733 #define L2IMU_BASE__INST1_SEG2 0
734 #define L2IMU_BASE__INST1_SEG3 0
735 #define L2IMU_BASE__INST1_SEG4 0
736
737 #define L2IMU_BASE__INST2_SEG0 0
738 #define L2IMU_BASE__INST2_SEG1 0
739 #define L2IMU_BASE__INST2_SEG2 0
740 #define L2IMU_BASE__INST2_SEG3 0
741 #define L2IMU_BASE__INST2_SEG4 0
742
743 #define L2IMU_BASE__INST3_SEG0 0
744 #define L2IMU_BASE__INST3_SEG1 0
745 #define L2IMU_BASE__INST3_SEG2 0
746 #define L2IMU_BASE__INST3_SEG3 0
747 #define L2IMU_BASE__INST3_SEG4 0
748
749 #define L2IMU_BASE__INST4_SEG0 0
750 #define L2IMU_BASE__INST4_SEG1 0
751 #define L2IMU_BASE__INST4_SEG2 0
752 #define L2IMU_BASE__INST4_SEG3 0
753 #define L2IMU_BASE__INST4_SEG4 0
754
755 #define IOHC_BASE__INST0_SEG0 0x00010000
756 #define IOHC_BASE__INST0_SEG1 0
757 #define IOHC_BASE__INST0_SEG2 0
758 #define IOHC_BASE__INST0_SEG3 0
759 #define IOHC_BASE__INST0_SEG4 0
760
761 #define IOHC_BASE__INST1_SEG0 0
762 #define IOHC_BASE__INST1_SEG1 0
763 #define IOHC_BASE__INST1_SEG2 0
764 #define IOHC_BASE__INST1_SEG3 0
765 #define IOHC_BASE__INST1_SEG4 0
766
767 #define IOHC_BASE__INST2_SEG0 0
768 #define IOHC_BASE__INST2_SEG1 0
769 #define IOHC_BASE__INST2_SEG2 0
770 #define IOHC_BASE__INST2_SEG3 0
771 #define IOHC_BASE__INST2_SEG4 0
772
773 #define IOHC_BASE__INST3_SEG0 0
774 #define IOHC_BASE__INST3_SEG1 0
775 #define IOHC_BASE__INST3_SEG2 0
776 #define IOHC_BASE__INST3_SEG3 0
777 #define IOHC_BASE__INST3_SEG4 0
778
779 #define IOHC_BASE__INST4_SEG0 0
780 #define IOHC_BASE__INST4_SEG1 0
781 #define IOHC_BASE__INST4_SEG2 0
782 #define IOHC_BASE__INST4_SEG3 0
783 #define IOHC_BASE__INST4_SEG4 0
784
785 #define ATHUB_BASE__INST0_SEG0 0x00000C20
786 #define ATHUB_BASE__INST0_SEG1 0
787 #define ATHUB_BASE__INST0_SEG2 0
788 #define ATHUB_BASE__INST0_SEG3 0
789 #define ATHUB_BASE__INST0_SEG4 0
790
791 #define ATHUB_BASE__INST1_SEG0 0
792 #define ATHUB_BASE__INST1_SEG1 0
793 #define ATHUB_BASE__INST1_SEG2 0
794 #define ATHUB_BASE__INST1_SEG3 0
795 #define ATHUB_BASE__INST1_SEG4 0
796
797 #define ATHUB_BASE__INST2_SEG0 0
798 #define ATHUB_BASE__INST2_SEG1 0
799 #define ATHUB_BASE__INST2_SEG2 0
800 #define ATHUB_BASE__INST2_SEG3 0
801 #define ATHUB_BASE__INST2_SEG4 0
802
803 #define ATHUB_BASE__INST3_SEG0 0
804 #define ATHUB_BASE__INST3_SEG1 0
805 #define ATHUB_BASE__INST3_SEG2 0
806 #define ATHUB_BASE__INST3_SEG3 0
807 #define ATHUB_BASE__INST3_SEG4 0
808
809 #define ATHUB_BASE__INST4_SEG0 0
810 #define ATHUB_BASE__INST4_SEG1 0
811 #define ATHUB_BASE__INST4_SEG2 0
812 #define ATHUB_BASE__INST4_SEG3 0
813 #define ATHUB_BASE__INST4_SEG4 0
814
815 #define VCE_BASE__INST0_SEG0 0x00007E00
816 #define VCE_BASE__INST0_SEG1 0x00048800
817 #define VCE_BASE__INST0_SEG2 0
818 #define VCE_BASE__INST0_SEG3 0
819 #define VCE_BASE__INST0_SEG4 0
820
821 #define VCE_BASE__INST1_SEG0 0
822 #define VCE_BASE__INST1_SEG1 0
823 #define VCE_BASE__INST1_SEG2 0
824 #define VCE_BASE__INST1_SEG3 0
825 #define VCE_BASE__INST1_SEG4 0
826
827 #define VCE_BASE__INST2_SEG0 0
828 #define VCE_BASE__INST2_SEG1 0
829 #define VCE_BASE__INST2_SEG2 0
830 #define VCE_BASE__INST2_SEG3 0
831 #define VCE_BASE__INST2_SEG4 0
832
833 #define VCE_BASE__INST3_SEG0 0
834 #define VCE_BASE__INST3_SEG1 0
835 #define VCE_BASE__INST3_SEG2 0
836 #define VCE_BASE__INST3_SEG3 0
837 #define VCE_BASE__INST3_SEG4 0
838
839 #define VCE_BASE__INST4_SEG0 0
840 #define VCE_BASE__INST4_SEG1 0
841 #define VCE_BASE__INST4_SEG2 0
842 #define VCE_BASE__INST4_SEG3 0
843 #define VCE_BASE__INST4_SEG4 0
844
845 #define GC_BASE__INST0_SEG0 0x00002000
846 #define GC_BASE__INST0_SEG1 0x0000A000
847 #define GC_BASE__INST0_SEG2 0
848 #define GC_BASE__INST0_SEG3 0
849 #define GC_BASE__INST0_SEG4 0
850
851 #define GC_BASE__INST1_SEG0 0
852 #define GC_BASE__INST1_SEG1 0
853 #define GC_BASE__INST1_SEG2 0
854 #define GC_BASE__INST1_SEG3 0
855 #define GC_BASE__INST1_SEG4 0
856
857 #define GC_BASE__INST2_SEG0 0
858 #define GC_BASE__INST2_SEG1 0
859 #define GC_BASE__INST2_SEG2 0
860 #define GC_BASE__INST2_SEG3 0
861 #define GC_BASE__INST2_SEG4 0
862
863 #define GC_BASE__INST3_SEG0 0
864 #define GC_BASE__INST3_SEG1 0
865 #define GC_BASE__INST3_SEG2 0
866 #define GC_BASE__INST3_SEG3 0
867 #define GC_BASE__INST3_SEG4 0
868
869 #define GC_BASE__INST4_SEG0 0
870 #define GC_BASE__INST4_SEG1 0
871 #define GC_BASE__INST4_SEG2 0
872 #define GC_BASE__INST4_SEG3 0
873 #define GC_BASE__INST4_SEG4 0
874
875 #define MMHUB_BASE__INST0_SEG0 0x0001A000
876 #define MMHUB_BASE__INST0_SEG1 0
877 #define MMHUB_BASE__INST0_SEG2 0
878 #define MMHUB_BASE__INST0_SEG3 0
879 #define MMHUB_BASE__INST0_SEG4 0
880
881 #define MMHUB_BASE__INST1_SEG0 0
882 #define MMHUB_BASE__INST1_SEG1 0
883 #define MMHUB_BASE__INST1_SEG2 0
884 #define MMHUB_BASE__INST1_SEG3 0
885 #define MMHUB_BASE__INST1_SEG4 0
886
887 #define MMHUB_BASE__INST2_SEG0 0
888 #define MMHUB_BASE__INST2_SEG1 0
889 #define MMHUB_BASE__INST2_SEG2 0
890 #define MMHUB_BASE__INST2_SEG3 0
891 #define MMHUB_BASE__INST2_SEG4 0
892
893 #define MMHUB_BASE__INST3_SEG0 0
894 #define MMHUB_BASE__INST3_SEG1 0
895 #define MMHUB_BASE__INST3_SEG2 0
896 #define MMHUB_BASE__INST3_SEG3 0
897 #define MMHUB_BASE__INST3_SEG4 0
898
899 #define MMHUB_BASE__INST4_SEG0 0
900 #define MMHUB_BASE__INST4_SEG1 0
901 #define MMHUB_BASE__INST4_SEG2 0
902 #define MMHUB_BASE__INST4_SEG3 0
903 #define MMHUB_BASE__INST4_SEG4 0
904
905 #define RSMU_BASE__INST0_SEG0 0x00012000
906 #define RSMU_BASE__INST0_SEG1 0
907 #define RSMU_BASE__INST0_SEG2 0
908 #define RSMU_BASE__INST0_SEG3 0
909 #define RSMU_BASE__INST0_SEG4 0
910
911 #define RSMU_BASE__INST1_SEG0 0
912 #define RSMU_BASE__INST1_SEG1 0
913 #define RSMU_BASE__INST1_SEG2 0
914 #define RSMU_BASE__INST1_SEG3 0
915 #define RSMU_BASE__INST1_SEG4 0
916
917 #define RSMU_BASE__INST2_SEG0 0
918 #define RSMU_BASE__INST2_SEG1 0
919 #define RSMU_BASE__INST2_SEG2 0
920 #define RSMU_BASE__INST2_SEG3 0
921 #define RSMU_BASE__INST2_SEG4 0
922
923 #define RSMU_BASE__INST3_SEG0 0
924 #define RSMU_BASE__INST3_SEG1 0
925 #define RSMU_BASE__INST3_SEG2 0
926 #define RSMU_BASE__INST3_SEG3 0
927 #define RSMU_BASE__INST3_SEG4 0
928
929 #define RSMU_BASE__INST4_SEG0 0
930 #define RSMU_BASE__INST4_SEG1 0
931 #define RSMU_BASE__INST4_SEG2 0
932 #define RSMU_BASE__INST4_SEG3 0
933 #define RSMU_BASE__INST4_SEG4 0
934
935 #define HDP_BASE__INST0_SEG0 0x00000F20
936 #define HDP_BASE__INST0_SEG1 0
937 #define HDP_BASE__INST0_SEG2 0
938 #define HDP_BASE__INST0_SEG3 0
939 #define HDP_BASE__INST0_SEG4 0
940
941 #define HDP_BASE__INST1_SEG0 0
942 #define HDP_BASE__INST1_SEG1 0
943 #define HDP_BASE__INST1_SEG2 0
944 #define HDP_BASE__INST1_SEG3 0
945 #define HDP_BASE__INST1_SEG4 0
946
947 #define HDP_BASE__INST2_SEG0 0
948 #define HDP_BASE__INST2_SEG1 0
949 #define HDP_BASE__INST2_SEG2 0
950 #define HDP_BASE__INST2_SEG3 0
951 #define HDP_BASE__INST2_SEG4 0
952
953 #define HDP_BASE__INST3_SEG0 0
954 #define HDP_BASE__INST3_SEG1 0
955 #define HDP_BASE__INST3_SEG2 0
956 #define HDP_BASE__INST3_SEG3 0
957 #define HDP_BASE__INST3_SEG4 0
958
959 #define HDP_BASE__INST4_SEG0 0
960 #define HDP_BASE__INST4_SEG1 0
961 #define HDP_BASE__INST4_SEG2 0
962 #define HDP_BASE__INST4_SEG3 0
963 #define HDP_BASE__INST4_SEG4 0
964
965 #define OSSSYS_BASE__INST0_SEG0 0x000010A0
966 #define OSSSYS_BASE__INST0_SEG1 0
967 #define OSSSYS_BASE__INST0_SEG2 0
968 #define OSSSYS_BASE__INST0_SEG3 0
969 #define OSSSYS_BASE__INST0_SEG4 0
970
971 #define OSSSYS_BASE__INST1_SEG0 0
972 #define OSSSYS_BASE__INST1_SEG1 0
973 #define OSSSYS_BASE__INST1_SEG2 0
974 #define OSSSYS_BASE__INST1_SEG3 0
975 #define OSSSYS_BASE__INST1_SEG4 0
976
977 #define OSSSYS_BASE__INST2_SEG0 0
978 #define OSSSYS_BASE__INST2_SEG1 0
979 #define OSSSYS_BASE__INST2_SEG2 0
980 #define OSSSYS_BASE__INST2_SEG3 0
981 #define OSSSYS_BASE__INST2_SEG4 0
982
983 #define OSSSYS_BASE__INST3_SEG0 0
984 #define OSSSYS_BASE__INST3_SEG1 0
985 #define OSSSYS_BASE__INST3_SEG2 0
986 #define OSSSYS_BASE__INST3_SEG3 0
987 #define OSSSYS_BASE__INST3_SEG4 0
988
989 #define OSSSYS_BASE__INST4_SEG0 0
990 #define OSSSYS_BASE__INST4_SEG1 0
991 #define OSSSYS_BASE__INST4_SEG2 0
992 #define OSSSYS_BASE__INST4_SEG3 0
993 #define OSSSYS_BASE__INST4_SEG4 0
994
995 #define SDMA0_BASE__INST0_SEG0 0x00001260
996 #define SDMA0_BASE__INST0_SEG1 0
997 #define SDMA0_BASE__INST0_SEG2 0
998 #define SDMA0_BASE__INST0_SEG3 0
999 #define SDMA0_BASE__INST0_SEG4 0
1000
1001 #define SDMA0_BASE__INST1_SEG0 0
1002 #define SDMA0_BASE__INST1_SEG1 0
1003 #define SDMA0_BASE__INST1_SEG2 0
1004 #define SDMA0_BASE__INST1_SEG3 0
1005 #define SDMA0_BASE__INST1_SEG4 0
1006
1007 #define SDMA0_BASE__INST2_SEG0 0
1008 #define SDMA0_BASE__INST2_SEG1 0
1009 #define SDMA0_BASE__INST2_SEG2 0
1010 #define SDMA0_BASE__INST2_SEG3 0
1011 #define SDMA0_BASE__INST2_SEG4 0
1012
1013 #define SDMA0_BASE__INST3_SEG0 0
1014 #define SDMA0_BASE__INST3_SEG1 0
1015 #define SDMA0_BASE__INST3_SEG2 0
1016 #define SDMA0_BASE__INST3_SEG3 0
1017 #define SDMA0_BASE__INST3_SEG4 0
1018
1019 #define SDMA0_BASE__INST4_SEG0 0
1020 #define SDMA0_BASE__INST4_SEG1 0
1021 #define SDMA0_BASE__INST4_SEG2 0
1022 #define SDMA0_BASE__INST4_SEG3 0
1023 #define SDMA0_BASE__INST4_SEG4 0
1024
1025 #define SDMA1_BASE__INST0_SEG0 0x00001460
1026 #define SDMA1_BASE__INST0_SEG1 0
1027 #define SDMA1_BASE__INST0_SEG2 0
1028 #define SDMA1_BASE__INST0_SEG3 0
1029 #define SDMA1_BASE__INST0_SEG4 0
1030
1031 #define SDMA1_BASE__INST1_SEG0 0
1032 #define SDMA1_BASE__INST1_SEG1 0
1033 #define SDMA1_BASE__INST1_SEG2 0
1034 #define SDMA1_BASE__INST1_SEG3 0
1035 #define SDMA1_BASE__INST1_SEG4 0
1036
1037 #define SDMA1_BASE__INST2_SEG0 0
1038 #define SDMA1_BASE__INST2_SEG1 0
1039 #define SDMA1_BASE__INST2_SEG2 0
1040 #define SDMA1_BASE__INST2_SEG3 0
1041 #define SDMA1_BASE__INST2_SEG4 0
1042
1043 #define SDMA1_BASE__INST3_SEG0 0
1044 #define SDMA1_BASE__INST3_SEG1 0
1045 #define SDMA1_BASE__INST3_SEG2 0
1046 #define SDMA1_BASE__INST3_SEG3 0
1047 #define SDMA1_BASE__INST3_SEG4 0
1048
1049 #define SDMA1_BASE__INST4_SEG0 0
1050 #define SDMA1_BASE__INST4_SEG1 0
1051 #define SDMA1_BASE__INST4_SEG2 0
1052 #define SDMA1_BASE__INST4_SEG3 0
1053 #define SDMA1_BASE__INST4_SEG4 0
1054
1055 #define XDMA_BASE__INST0_SEG0 0x00003400
1056 #define XDMA_BASE__INST0_SEG1 0
1057 #define XDMA_BASE__INST0_SEG2 0
1058 #define XDMA_BASE__INST0_SEG3 0
1059 #define XDMA_BASE__INST0_SEG4 0
1060
1061 #define XDMA_BASE__INST1_SEG0 0
1062 #define XDMA_BASE__INST1_SEG1 0
1063 #define XDMA_BASE__INST1_SEG2 0
1064 #define XDMA_BASE__INST1_SEG3 0
1065 #define XDMA_BASE__INST1_SEG4 0
1066
1067 #define XDMA_BASE__INST2_SEG0 0
1068 #define XDMA_BASE__INST2_SEG1 0
1069 #define XDMA_BASE__INST2_SEG2 0
1070 #define XDMA_BASE__INST2_SEG3 0
1071 #define XDMA_BASE__INST2_SEG4 0
1072
1073 #define XDMA_BASE__INST3_SEG0 0
1074 #define XDMA_BASE__INST3_SEG1 0
1075 #define XDMA_BASE__INST3_SEG2 0
1076 #define XDMA_BASE__INST3_SEG3 0
1077 #define XDMA_BASE__INST3_SEG4 0
1078
1079 #define XDMA_BASE__INST4_SEG0 0
1080 #define XDMA_BASE__INST4_SEG1 0
1081 #define XDMA_BASE__INST4_SEG2 0
1082 #define XDMA_BASE__INST4_SEG3 0
1083 #define XDMA_BASE__INST4_SEG4 0
1084
1085 #define UMC_BASE__INST0_SEG0 0x00014000
1086 #define UMC_BASE__INST0_SEG1 0
1087 #define UMC_BASE__INST0_SEG2 0
1088 #define UMC_BASE__INST0_SEG3 0
1089 #define UMC_BASE__INST0_SEG4 0
1090
1091 #define UMC_BASE__INST1_SEG0 0
1092 #define UMC_BASE__INST1_SEG1 0
1093 #define UMC_BASE__INST1_SEG2 0
1094 #define UMC_BASE__INST1_SEG3 0
1095 #define UMC_BASE__INST1_SEG4 0
1096
1097 #define UMC_BASE__INST2_SEG0 0
1098 #define UMC_BASE__INST2_SEG1 0
1099 #define UMC_BASE__INST2_SEG2 0
1100 #define UMC_BASE__INST2_SEG3 0
1101 #define UMC_BASE__INST2_SEG4 0
1102
1103 #define UMC_BASE__INST3_SEG0 0
1104 #define UMC_BASE__INST3_SEG1 0
1105 #define UMC_BASE__INST3_SEG2 0
1106 #define UMC_BASE__INST3_SEG3 0
1107 #define UMC_BASE__INST3_SEG4 0
1108
1109 #define UMC_BASE__INST4_SEG0 0
1110 #define UMC_BASE__INST4_SEG1 0
1111 #define UMC_BASE__INST4_SEG2 0
1112 #define UMC_BASE__INST4_SEG3 0
1113 #define UMC_BASE__INST4_SEG4 0
1114
1115 #define THM_BASE__INST0_SEG0 0x00016600
1116 #define THM_BASE__INST0_SEG1 0
1117 #define THM_BASE__INST0_SEG2 0
1118 #define THM_BASE__INST0_SEG3 0
1119 #define THM_BASE__INST0_SEG4 0
1120
1121 #define THM_BASE__INST1_SEG0 0
1122 #define THM_BASE__INST1_SEG1 0
1123 #define THM_BASE__INST1_SEG2 0
1124 #define THM_BASE__INST1_SEG3 0
1125 #define THM_BASE__INST1_SEG4 0
1126
1127 #define THM_BASE__INST2_SEG0 0
1128 #define THM_BASE__INST2_SEG1 0
1129 #define THM_BASE__INST2_SEG2 0
1130 #define THM_BASE__INST2_SEG3 0
1131 #define THM_BASE__INST2_SEG4 0
1132
1133 #define THM_BASE__INST3_SEG0 0
1134 #define THM_BASE__INST3_SEG1 0
1135 #define THM_BASE__INST3_SEG2 0
1136 #define THM_BASE__INST3_SEG3 0
1137 #define THM_BASE__INST3_SEG4 0
1138
1139 #define THM_BASE__INST4_SEG0 0
1140 #define THM_BASE__INST4_SEG1 0
1141 #define THM_BASE__INST4_SEG2 0
1142 #define THM_BASE__INST4_SEG3 0
1143 #define THM_BASE__INST4_SEG4 0
1144
1145 #define SMUIO_BASE__INST0_SEG0 0x00016800
1146 #define SMUIO_BASE__INST0_SEG1 0
1147 #define SMUIO_BASE__INST0_SEG2 0
1148 #define SMUIO_BASE__INST0_SEG3 0
1149 #define SMUIO_BASE__INST0_SEG4 0
1150
1151 #define SMUIO_BASE__INST1_SEG0 0
1152 #define SMUIO_BASE__INST1_SEG1 0
1153 #define SMUIO_BASE__INST1_SEG2 0
1154 #define SMUIO_BASE__INST1_SEG3 0
1155 #define SMUIO_BASE__INST1_SEG4 0
1156
1157 #define SMUIO_BASE__INST2_SEG0 0
1158 #define SMUIO_BASE__INST2_SEG1 0
1159 #define SMUIO_BASE__INST2_SEG2 0
1160 #define SMUIO_BASE__INST2_SEG3 0
1161 #define SMUIO_BASE__INST2_SEG4 0
1162
1163 #define SMUIO_BASE__INST3_SEG0 0
1164 #define SMUIO_BASE__INST3_SEG1 0
1165 #define SMUIO_BASE__INST3_SEG2 0
1166 #define SMUIO_BASE__INST3_SEG3 0
1167 #define SMUIO_BASE__INST3_SEG4 0
1168
1169 #define SMUIO_BASE__INST4_SEG0 0
1170 #define SMUIO_BASE__INST4_SEG1 0
1171 #define SMUIO_BASE__INST4_SEG2 0
1172 #define SMUIO_BASE__INST4_SEG3 0
1173 #define SMUIO_BASE__INST4_SEG4 0
1174
1175 #define PWR_BASE__INST0_SEG0 0x00016A00
1176 #define PWR_BASE__INST0_SEG1 0
1177 #define PWR_BASE__INST0_SEG2 0
1178 #define PWR_BASE__INST0_SEG3 0
1179 #define PWR_BASE__INST0_SEG4 0
1180
1181 #define PWR_BASE__INST1_SEG0 0
1182 #define PWR_BASE__INST1_SEG1 0
1183 #define PWR_BASE__INST1_SEG2 0
1184 #define PWR_BASE__INST1_SEG3 0
1185 #define PWR_BASE__INST1_SEG4 0
1186
1187 #define PWR_BASE__INST2_SEG0 0
1188 #define PWR_BASE__INST2_SEG1 0
1189 #define PWR_BASE__INST2_SEG2 0
1190 #define PWR_BASE__INST2_SEG3 0
1191 #define PWR_BASE__INST2_SEG4 0
1192
1193 #define PWR_BASE__INST3_SEG0 0
1194 #define PWR_BASE__INST3_SEG1 0
1195 #define PWR_BASE__INST3_SEG2 0
1196 #define PWR_BASE__INST3_SEG3 0
1197 #define PWR_BASE__INST3_SEG4 0
1198
1199 #define PWR_BASE__INST4_SEG0 0
1200 #define PWR_BASE__INST4_SEG1 0
1201 #define PWR_BASE__INST4_SEG2 0
1202 #define PWR_BASE__INST4_SEG3 0
1203 #define PWR_BASE__INST4_SEG4 0
1204
1205 #define CLK_BASE__INST0_SEG0 0x00016C00
1206 #define CLK_BASE__INST0_SEG1 0
1207 #define CLK_BASE__INST0_SEG2 0
1208 #define CLK_BASE__INST0_SEG3 0
1209 #define CLK_BASE__INST0_SEG4 0
1210
1211 #define CLK_BASE__INST1_SEG0 0x00016E00
1212 #define CLK_BASE__INST1_SEG1 0
1213 #define CLK_BASE__INST1_SEG2 0
1214 #define CLK_BASE__INST1_SEG3 0
1215 #define CLK_BASE__INST1_SEG4 0
1216
1217 #define CLK_BASE__INST2_SEG0 0x00017000
1218 #define CLK_BASE__INST2_SEG1 0
1219 #define CLK_BASE__INST2_SEG2 0
1220 #define CLK_BASE__INST2_SEG3 0
1221 #define CLK_BASE__INST2_SEG4 0
1222
1223 #define CLK_BASE__INST3_SEG0 0x00017200
1224 #define CLK_BASE__INST3_SEG1 0
1225 #define CLK_BASE__INST3_SEG2 0
1226 #define CLK_BASE__INST3_SEG3 0
1227 #define CLK_BASE__INST3_SEG4 0
1228
1229 #define CLK_BASE__INST4_SEG0 0x00017E00
1230 #define CLK_BASE__INST4_SEG1 0
1231 #define CLK_BASE__INST4_SEG2 0
1232 #define CLK_BASE__INST4_SEG3 0
1233 #define CLK_BASE__INST4_SEG4 0
1234
1235 #define FUSE_BASE__INST0_SEG0 0x00017400
1236 #define FUSE_BASE__INST0_SEG1 0
1237 #define FUSE_BASE__INST0_SEG2 0
1238 #define FUSE_BASE__INST0_SEG3 0
1239 #define FUSE_BASE__INST0_SEG4 0
1240
1241 #define FUSE_BASE__INST1_SEG0 0
1242 #define FUSE_BASE__INST1_SEG1 0
1243 #define FUSE_BASE__INST1_SEG2 0
1244 #define FUSE_BASE__INST1_SEG3 0
1245 #define FUSE_BASE__INST1_SEG4 0
1246
1247 #define FUSE_BASE__INST2_SEG0 0
1248 #define FUSE_BASE__INST2_SEG1 0
1249 #define FUSE_BASE__INST2_SEG2 0
1250 #define FUSE_BASE__INST2_SEG3 0
1251 #define FUSE_BASE__INST2_SEG4 0
1252
1253 #define FUSE_BASE__INST3_SEG0 0
1254 #define FUSE_BASE__INST3_SEG1 0
1255 #define FUSE_BASE__INST3_SEG2 0
1256 #define FUSE_BASE__INST3_SEG3 0
1257 #define FUSE_BASE__INST3_SEG4 0
1258
1259 #define FUSE_BASE__INST4_SEG0 0
1260 #define FUSE_BASE__INST4_SEG1 0
1261 #define FUSE_BASE__INST4_SEG2 0
1262 #define FUSE_BASE__INST4_SEG3 0
1263 #define FUSE_BASE__INST4_SEG4 0
1264 #endif
1265
Linux with added FPC-III support