drivers/gpu/drm/ast/ast_main.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial portions
  22  * of the Software.
  23  *
  24  */
  25 /*
  26  * Authors: Dave Airlie <airlied@redhat.com>
  27  */
  28
  29 #include <linux/pci.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_drv.h>
  34 #include <drm/drm_gem.h>
  35 #include <drm/drm_gem_vram_helper.h>
  36 #include <drm/drm_managed.h>
  37
  38 #include "ast_drv.h"
  39
  40 void ast_set_index_reg_mask(struct ast_private *ast,
  41                             uint32_t base, uint8_t index,
  42                             uint8_t mask, uint8_t val)
  43 {
  44         u8 tmp;
  45         ast_io_write8(ast, base, index);
  46         tmp = (ast_io_read8(ast, base + 1) & mask) | val;
  47         ast_set_index_reg(ast, base, index, tmp);
  48 }
  49
  50 uint8_t ast_get_index_reg(struct ast_private *ast,
  51                           uint32_t base, uint8_t index)
  52 {
  53         uint8_t ret;
  54         ast_io_write8(ast, base, index);
  55         ret = ast_io_read8(ast, base + 1);
  56         return ret;
  57 }
  58
  59 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
  60                                uint32_t base, uint8_t index, uint8_t mask)
  61 {
  62         uint8_t ret;
  63         ast_io_write8(ast, base, index);
  64         ret = ast_io_read8(ast, base + 1) & mask;
  65         return ret;
  66 }
  67
  68 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
  69 {
  70         struct device_node *np = dev->pdev->dev.of_node;
  71         struct ast_private *ast = to_ast_private(dev);
  72         uint32_t data, jregd0, jregd1;
  73
  74         /* Defaults */
  75         ast->config_mode = ast_use_defaults;
  76         *scu_rev = 0xffffffff;
  77
  78         /* Check if we have device-tree properties */
  79         if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
  80                                         scu_rev)) {
  81                 /* We do, disable P2A access */
  82                 ast->config_mode = ast_use_dt;
  83                 drm_info(dev, "Using device-tree for configuration\n");
  84                 return;
  85         }
  86
  87         /* Not all families have a P2A bridge */
  88         if (dev->pdev->device != PCI_CHIP_AST2000)
  89                 return;
  90
  91         /*
  92          * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
  93          * is disabled. We force using P2A if VGA only mode bit
  94          * is set D[7]
  95          */
  96         jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
  97         jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
  98         if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
  99                 /* Double check it's actually working */
 100                 data = ast_read32(ast, 0xf004);
 101                 if (data != 0xFFFFFFFF) {
 102                         /* P2A works, grab silicon revision */
 103                         ast->config_mode = ast_use_p2a;
 104
 105                         drm_info(dev, "Using P2A bridge for configuration\n");
 106
 107                         /* Read SCU7c (silicon revision register) */
 108                         ast_write32(ast, 0xf004, 0x1e6e0000);
 109                         ast_write32(ast, 0xf000, 0x1);
 110                         *scu_rev = ast_read32(ast, 0x1207c);
 111                         return;
 112                 }
 113         }
 114
 115         /* We have a P2A bridge but it's disabled */
 116         drm_info(dev, "P2A bridge disabled, using default configuration\n");
 117 }
 118
 119 static int ast_detect_chip(struct drm_device *dev, bool *need_post)
 120 {
 121         struct ast_private *ast = to_ast_private(dev);
 122         uint32_t jreg, scu_rev;
 123
 124         /*
 125          * If VGA isn't enabled, we need to enable now or subsequent
 126          * access to the scratch registers will fail. We also inform
 127          * our caller that it needs to POST the chip
 128          * (Assumption: VGA not enabled -> need to POST)
 129          */
 130         if (!ast_is_vga_enabled(dev)) {
 131                 ast_enable_vga(dev);
 132                 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
 133                 *need_post = true;
 134         } else
 135                 *need_post = false;
 136
 137
 138         /* Enable extended register access */
 139         ast_open_key(ast);
 140         ast_enable_mmio(dev);
 141
 142         /* Find out whether P2A works or whether to use device-tree */
 143         ast_detect_config_mode(dev, &scu_rev);
 144
 145         /* Identify chipset */
 146         if (dev->pdev->revision >= 0x50) {
 147                 ast->chip = AST2600;
 148                 drm_info(dev, "AST 2600 detected\n");
 149         } else if (dev->pdev->revision >= 0x40) {
 150                 ast->chip = AST2500;
 151                 drm_info(dev, "AST 2500 detected\n");
 152         } else if (dev->pdev->revision >= 0x30) {
 153                 ast->chip = AST2400;
 154                 drm_info(dev, "AST 2400 detected\n");
 155         } else if (dev->pdev->revision >= 0x20) {
 156                 ast->chip = AST2300;
 157                 drm_info(dev, "AST 2300 detected\n");
 158         } else if (dev->pdev->revision >= 0x10) {
 159                 switch (scu_rev & 0x0300) {
 160                 case 0x0200:
 161                         ast->chip = AST1100;
 162                         drm_info(dev, "AST 1100 detected\n");
 163                         break;
 164                 case 0x0100:
 165                         ast->chip = AST2200;
 166                         drm_info(dev, "AST 2200 detected\n");
 167                         break;
 168                 case 0x0000:
 169                         ast->chip = AST2150;
 170                         drm_info(dev, "AST 2150 detected\n");
 171                         break;
 172                 default:
 173                         ast->chip = AST2100;
 174                         drm_info(dev, "AST 2100 detected\n");
 175                         break;
 176                 }
 177                 ast->vga2_clone = false;
 178         } else {
 179                 ast->chip = AST2000;
 180                 drm_info(dev, "AST 2000 detected\n");
 181         }
 182
 183         /* Check if we support wide screen */
 184         switch (ast->chip) {
 185         case AST2000:
 186                 ast->support_wide_screen = false;
 187                 break;
 188         default:
 189                 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
 190                 if (!(jreg & 0x80))
 191                         ast->support_wide_screen = true;
 192                 else if (jreg & 0x01)
 193                         ast->support_wide_screen = true;
 194                 else {
 195                         ast->support_wide_screen = false;
 196                         if (ast->chip == AST2300 &&
 197                             (scu_rev & 0x300) == 0x0) /* ast1300 */
 198                                 ast->support_wide_screen = true;
 199                         if (ast->chip == AST2400 &&
 200                             (scu_rev & 0x300) == 0x100) /* ast1400 */
 201                                 ast->support_wide_screen = true;
 202                         if (ast->chip == AST2500 &&
 203                             scu_rev == 0x100)           /* ast2510 */
 204                                 ast->support_wide_screen = true;
 205                 }
 206                 break;
 207         }
 208
 209         /* Check 3rd Tx option (digital output afaik) */
 210         ast->tx_chip_type = AST_TX_NONE;
 211
 212         /*
 213          * VGACRA3 Enhanced Color Mode Register, check if DVO is already
 214          * enabled, in that case, assume we have a SIL164 TMDS transmitter
 215          *
 216          * Don't make that assumption if we the chip wasn't enabled and
 217          * is at power-on reset, otherwise we'll incorrectly "detect" a
 218          * SIL164 when there is none.
 219          */
 220         if (!*need_post) {
 221                 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
 222                 if (jreg & 0x80)
 223                         ast->tx_chip_type = AST_TX_SIL164;
 224         }
 225
 226         if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
 227                 /*
 228                  * On AST2300 and 2400, look the configuration set by the SoC in
 229                  * the SOC scratch register #1 bits 11:8 (interestingly marked
 230                  * as "reserved" in the spec)
 231                  */
 232                 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
 233                 switch (jreg) {
 234                 case 0x04:
 235                         ast->tx_chip_type = AST_TX_SIL164;
 236                         break;
 237                 case 0x08:
 238                         ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
 239                         if (ast->dp501_fw_addr) {
 240                                 /* backup firmware */
 241                                 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
 242                                         drmm_kfree(dev, ast->dp501_fw_addr);
 243                                         ast->dp501_fw_addr = NULL;
 244                                 }
 245                         }
 246                         fallthrough;
 247                 case 0x0c:
 248                         ast->tx_chip_type = AST_TX_DP501;
 249                 }
 250         }
 251
 252         /* Print stuff for diagnostic purposes */
 253         switch(ast->tx_chip_type) {
 254         case AST_TX_SIL164:
 255                 drm_info(dev, "Using Sil164 TMDS transmitter\n");
 256                 break;
 257         case AST_TX_DP501:
 258                 drm_info(dev, "Using DP501 DisplayPort transmitter\n");
 259                 break;
 260         default:
 261                 drm_info(dev, "Analog VGA only\n");
 262         }
 263         return 0;
 264 }
 265
 266 static int ast_get_dram_info(struct drm_device *dev)
 267 {
 268         struct device_node *np = dev->pdev->dev.of_node;
 269         struct ast_private *ast = to_ast_private(dev);
 270         uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
 271         uint32_t denum, num, div, ref_pll, dsel;
 272
 273         switch (ast->config_mode) {
 274         case ast_use_dt:
 275                 /*
 276                  * If some properties are missing, use reasonable
 277                  * defaults for AST2400
 278                  */
 279                 if (of_property_read_u32(np, "aspeed,mcr-configuration",
 280                                          &mcr_cfg))
 281                         mcr_cfg = 0x00000577;
 282                 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
 283                                          &mcr_scu_mpll))
 284                         mcr_scu_mpll = 0x000050C0;
 285                 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
 286                                          &mcr_scu_strap))
 287                         mcr_scu_strap = 0;
 288                 break;
 289         case ast_use_p2a:
 290                 ast_write32(ast, 0xf004, 0x1e6e0000);
 291                 ast_write32(ast, 0xf000, 0x1);
 292                 mcr_cfg = ast_read32(ast, 0x10004);
 293                 mcr_scu_mpll = ast_read32(ast, 0x10120);
 294                 mcr_scu_strap = ast_read32(ast, 0x10170);
 295                 break;
 296         case ast_use_defaults:
 297         default:
 298                 ast->dram_bus_width = 16;
 299                 ast->dram_type = AST_DRAM_1Gx16;
 300                 if (ast->chip == AST2500)
 301                         ast->mclk = 800;
 302                 else
 303                         ast->mclk = 396;
 304                 return 0;
 305         }
 306
 307         if (mcr_cfg & 0x40)
 308                 ast->dram_bus_width = 16;
 309         else
 310                 ast->dram_bus_width = 32;
 311
 312         if (ast->chip == AST2500) {
 313                 switch (mcr_cfg & 0x03) {
 314                 case 0:
 315                         ast->dram_type = AST_DRAM_1Gx16;
 316                         break;
 317                 default:
 318                 case 1:
 319                         ast->dram_type = AST_DRAM_2Gx16;
 320                         break;
 321                 case 2:
 322                         ast->dram_type = AST_DRAM_4Gx16;
 323                         break;
 324                 case 3:
 325                         ast->dram_type = AST_DRAM_8Gx16;
 326                         break;
 327                 }
 328         } else if (ast->chip == AST2300 || ast->chip == AST2400) {
 329                 switch (mcr_cfg & 0x03) {
 330                 case 0:
 331                         ast->dram_type = AST_DRAM_512Mx16;
 332                         break;
 333                 default:
 334                 case 1:
 335                         ast->dram_type = AST_DRAM_1Gx16;
 336                         break;
 337                 case 2:
 338                         ast->dram_type = AST_DRAM_2Gx16;
 339                         break;
 340                 case 3:
 341                         ast->dram_type = AST_DRAM_4Gx16;
 342                         break;
 343                 }
 344         } else {
 345                 switch (mcr_cfg & 0x0c) {
 346                 case 0:
 347                 case 4:
 348                         ast->dram_type = AST_DRAM_512Mx16;
 349                         break;
 350                 case 8:
 351                         if (mcr_cfg & 0x40)
 352                                 ast->dram_type = AST_DRAM_1Gx16;
 353                         else
 354                                 ast->dram_type = AST_DRAM_512Mx32;
 355                         break;
 356                 case 0xc:
 357                         ast->dram_type = AST_DRAM_1Gx32;
 358                         break;
 359                 }
 360         }
 361
 362         if (mcr_scu_strap & 0x2000)
 363                 ref_pll = 14318;
 364         else
 365                 ref_pll = 12000;
 366
 367         denum = mcr_scu_mpll & 0x1f;
 368         num = (mcr_scu_mpll & 0x3fe0) >> 5;
 369         dsel = (mcr_scu_mpll & 0xc000) >> 14;
 370         switch (dsel) {
 371         case 3:
 372                 div = 0x4;
 373                 break;
 374         case 2:
 375         case 1:
 376                 div = 0x2;
 377                 break;
 378         default:
 379                 div = 0x1;
 380                 break;
 381         }
 382         ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
 383         return 0;
 384 }
 385
 386 /*
 387  * Run this function as part of the HW device cleanup; not
 388  * when the DRM device gets released.
 389  */
 390 static void ast_device_release(void *data)
 391 {
 392         struct ast_private *ast = data;
 393
 394         /* enable standard VGA decode */
 395         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
 396 }
 397
 398 struct ast_private *ast_device_create(const struct drm_driver *drv,
 399                                       struct pci_dev *pdev,
 400                                       unsigned long flags)
 401 {
 402         struct drm_device *dev;
 403         struct ast_private *ast;
 404         bool need_post;
 405         int ret = 0;
 406
 407         ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_private, base);
 408         if (IS_ERR(ast))
 409                 return ast;
 410         dev = &ast->base;
 411
 412         dev->pdev = pdev;
 413         pci_set_drvdata(pdev, dev);
 414
 415         ast->regs = pci_iomap(dev->pdev, 1, 0);
 416         if (!ast->regs)
 417                 return ERR_PTR(-EIO);
 418
 419         /*
 420          * If we don't have IO space at all, use MMIO now and
 421          * assume the chip has MMIO enabled by default (rev 0x20
 422          * and higher).
 423          */
 424         if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
 425                 drm_info(dev, "platform has no IO space, trying MMIO\n");
 426                 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
 427         }
 428
 429         /* "map" IO regs if the above hasn't done so already */
 430         if (!ast->ioregs) {
 431                 ast->ioregs = pci_iomap(dev->pdev, 2, 0);
 432                 if (!ast->ioregs)
 433                         return ERR_PTR(-EIO);
 434         }
 435
 436         ast_detect_chip(dev, &need_post);
 437
 438         ret = ast_get_dram_info(dev);
 439         if (ret)
 440                 return ERR_PTR(ret);
 441
 442         drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
 443                  ast->mclk, ast->dram_type, ast->dram_bus_width);
 444
 445         if (need_post)
 446                 ast_post_gpu(dev);
 447
 448         ret = ast_mm_init(ast);
 449         if (ret)
 450                 return ERR_PTR(ret);
 451
 452         ret = ast_mode_config_init(ast);
 453         if (ret)
 454                 return ERR_PTR(ret);
 455
 456         ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast);
 457         if (ret)
 458                 return ERR_PTR(ret);
 459
 460         return ast;
 461 }