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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / ast / ast_post.c
blob8902c2f84bf99ab0def4b95870cfcc1816d66b22
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29 #include <linux/delay.h>
30 #include <linux/pci.h>
31
32 #include <drm/drm_print.h>
33
34 #include "ast_dram_tables.h"
35 #include "ast_drv.h"
36
37 static void ast_post_chip_2300(struct drm_device *dev);
38 static void ast_post_chip_2500(struct drm_device *dev);
39
40 void ast_enable_vga(struct drm_device *dev)
41 {
42 struct ast_private *ast = to_ast_private(dev);
43
44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
46 }
47
48 void ast_enable_mmio(struct drm_device *dev)
49 {
50 struct ast_private *ast = to_ast_private(dev);
51
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
53 }
54
55
56 bool ast_is_vga_enabled(struct drm_device *dev)
57 {
58 struct ast_private *ast = to_ast_private(dev);
59 u8 ch;
60
61 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
62
63 return !!(ch & 0x01);
64 }
65
66 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
67 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
68 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
69
70 static void
71 ast_set_def_ext_reg(struct drm_device *dev)
72 {
73 struct ast_private *ast = to_ast_private(dev);
74 u8 i, index, reg;
75 const u8 *ext_reg_info;
76
77 /* reset scratch */
78 for (i = 0x81; i <= 0x9f; i++)
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
80
81 if (ast->chip == AST2300 || ast->chip == AST2400 ||
82 ast->chip == AST2500) {
83 if (dev->pdev->revision >= 0x20)
84 ext_reg_info = extreginfo_ast2300;
85 else
86 ext_reg_info = extreginfo_ast2300a0;
87 } else
88 ext_reg_info = extreginfo;
89
90 index = 0xa0;
91 while (*ext_reg_info != 0xff) {
92 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
93 index++;
94 ext_reg_info++;
95 }
96
97 /* disable standard IO/MEM decode if secondary */
98 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
99
100 /* Set Ext. Default */
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
103
104 /* Enable RAMDAC for A1 */
105 reg = 0x04;
106 if (ast->chip == AST2300 || ast->chip == AST2400 ||
107 ast->chip == AST2500)
108 reg |= 0x20;
109 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
110 }
111
112 u32 ast_mindwm(struct ast_private *ast, u32 r)
113 {
114 uint32_t data;
115
116 ast_write32(ast, 0xf004, r & 0xffff0000);
117 ast_write32(ast, 0xf000, 0x1);
118
119 do {
120 data = ast_read32(ast, 0xf004) & 0xffff0000;
121 } while (data != (r & 0xffff0000));
122 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
123 }
124
125 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
126 {
127 uint32_t data;
128 ast_write32(ast, 0xf004, r & 0xffff0000);
129 ast_write32(ast, 0xf000, 0x1);
130 do {
131 data = ast_read32(ast, 0xf004) & 0xffff0000;
132 } while (data != (r & 0xffff0000));
133 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
134 }
135
136 /*
137 * AST2100/2150 DLL CBR Setting
138 */
139 #define CBR_SIZE_AST2150 ((16 << 10) - 1)
140 #define CBR_PASSNUM_AST2150 5
141 #define CBR_THRESHOLD_AST2150 10
142 #define CBR_THRESHOLD2_AST2150 10
143 #define TIMEOUT_AST2150 5000000
144
145 #define CBR_PATNUM_AST2150 8
146
147 static const u32 pattern_AST2150[14] = {
148 0xFF00FF00,
149 0xCC33CC33,
150 0xAA55AA55,
151 0xFFFE0001,
152 0x683501FE,
153 0x0F1929B0,
154 0x2D0B4346,
155 0x60767F02,
156 0x6FBE36A6,
157 0x3A253035,
158 0x3019686D,
159 0x41C6167E,
160 0x620152BF,
161 0x20F050E0
162 };
163
164 static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
165 {
166 u32 data, timeout;
167
168 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
170 timeout = 0;
171 do {
172 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
173 if (++timeout > TIMEOUT_AST2150) {
174 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
175 return 0xffffffff;
176 }
177 } while (!data);
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
180 timeout = 0;
181 do {
182 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
183 if (++timeout > TIMEOUT_AST2150) {
184 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
185 return 0xffffffff;
186 }
187 } while (!data);
188 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
189 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
190 return data;
191 }
192
193 #if 0 /* unused in DDX driver - here for completeness */
194 static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
195 {
196 u32 data, timeout;
197
198 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
199 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
200 timeout = 0;
201 do {
202 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
203 if (++timeout > TIMEOUT_AST2150) {
204 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
205 return 0xffffffff;
206 }
207 } while (!data);
208 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
209 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
210 return data;
211 }
212 #endif
213
214 static int cbrtest_ast2150(struct ast_private *ast)
215 {
216 int i;
217
218 for (i = 0; i < 8; i++)
219 if (mmctestburst2_ast2150(ast, i))
220 return 0;
221 return 1;
222 }
223
224 static int cbrscan_ast2150(struct ast_private *ast, int busw)
225 {
226 u32 patcnt, loop;
227
228 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
229 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
230 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
231 if (cbrtest_ast2150(ast))
232 break;
233 }
234 if (loop == CBR_PASSNUM_AST2150)
235 return 0;
236 }
237 return 1;
238 }
239
240
241 static void cbrdlli_ast2150(struct ast_private *ast, int busw)
242 {
243 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
244
245 cbr_start:
246 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
247 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
248 passcnt = 0;
249
250 for (dlli = 0; dlli < 100; dlli++) {
251 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
252 data = cbrscan_ast2150(ast, busw);
253 if (data != 0) {
254 if (data & 0x1) {
255 if (dll_min[0] > dlli)
256 dll_min[0] = dlli;
257 if (dll_max[0] < dlli)
258 dll_max[0] = dlli;
259 }
260 passcnt++;
261 } else if (passcnt >= CBR_THRESHOLD_AST2150)
262 goto cbr_start;
263 }
264 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
265 goto cbr_start;
266
267 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
268 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
269 }
270
271
272
273 static void ast_init_dram_reg(struct drm_device *dev)
274 {
275 struct ast_private *ast = to_ast_private(dev);
276 u8 j;
277 u32 data, temp, i;
278 const struct ast_dramstruct *dram_reg_info;
279
280 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
281
282 if ((j & 0x80) == 0) { /* VGA only */
283 if (ast->chip == AST2000) {
284 dram_reg_info = ast2000_dram_table_data;
285 ast_write32(ast, 0xf004, 0x1e6e0000);
286 ast_write32(ast, 0xf000, 0x1);
287 ast_write32(ast, 0x10100, 0xa8);
288
289 do {
290 ;
291 } while (ast_read32(ast, 0x10100) != 0xa8);
292 } else {/* AST2100/1100 */
293 if (ast->chip == AST2100 || ast->chip == 2200)
294 dram_reg_info = ast2100_dram_table_data;
295 else
296 dram_reg_info = ast1100_dram_table_data;
297
298 ast_write32(ast, 0xf004, 0x1e6e0000);
299 ast_write32(ast, 0xf000, 0x1);
300 ast_write32(ast, 0x12000, 0x1688A8A8);
301 do {
302 ;
303 } while (ast_read32(ast, 0x12000) != 0x01);
304
305 ast_write32(ast, 0x10000, 0xfc600309);
306 do {
307 ;
308 } while (ast_read32(ast, 0x10000) != 0x01);
309 }
310
311 while (dram_reg_info->index != 0xffff) {
312 if (dram_reg_info->index == 0xff00) {/* delay fn */
313 for (i = 0; i < 15; i++)
314 udelay(dram_reg_info->data);
315 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
316 data = dram_reg_info->data;
317 if (ast->dram_type == AST_DRAM_1Gx16)
318 data = 0x00000d89;
319 else if (ast->dram_type == AST_DRAM_1Gx32)
320 data = 0x00000c8d;
321
322 temp = ast_read32(ast, 0x12070);
323 temp &= 0xc;
324 temp <<= 2;
325 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
326 } else
327 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
328 dram_reg_info++;
329 }
330
331 /* AST 2100/2150 DRAM calibration */
332 data = ast_read32(ast, 0x10120);
333 if (data == 0x5061) { /* 266Mhz */
334 data = ast_read32(ast, 0x10004);
335 if (data & 0x40)
336 cbrdlli_ast2150(ast, 16); /* 16 bits */
337 else
338 cbrdlli_ast2150(ast, 32); /* 32 bits */
339 }
340
341 switch (ast->chip) {
342 case AST2000:
343 temp = ast_read32(ast, 0x10140);
344 ast_write32(ast, 0x10140, temp | 0x40);
345 break;
346 case AST1100:
347 case AST2100:
348 case AST2200:
349 case AST2150:
350 temp = ast_read32(ast, 0x1200c);
351 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
352 temp = ast_read32(ast, 0x12040);
353 ast_write32(ast, 0x12040, temp | 0x40);
354 break;
355 default:
356 break;
357 }
358 }
359
360 /* wait ready */
361 do {
362 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
363 } while ((j & 0x40) == 0);
364 }
365
366 void ast_post_gpu(struct drm_device *dev)
367 {
368 struct ast_private *ast = to_ast_private(dev);
369 u32 reg;
370
371 pci_read_config_dword(dev->pdev, 0x04, &reg);
372 reg |= 0x3;
373 pci_write_config_dword(dev->pdev, 0x04, reg);
374
375 ast_enable_vga(dev);
376 ast_open_key(ast);
377 ast_enable_mmio(dev);
378 ast_set_def_ext_reg(dev);
379
380 if (ast->config_mode == ast_use_p2a) {
381 if (ast->chip == AST2500)
382 ast_post_chip_2500(dev);
383 else if (ast->chip == AST2300 || ast->chip == AST2400)
384 ast_post_chip_2300(dev);
385 else
386 ast_init_dram_reg(dev);
387
388 ast_init_3rdtx(dev);
389 } else {
390 if (ast->tx_chip_type != AST_TX_NONE)
391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
392 }
393 }
394
395 /* AST 2300 DRAM settings */
396 #define AST_DDR3 0
397 #define AST_DDR2 1
398
399 struct ast2300_dram_param {
400 u32 dram_type;
401 u32 dram_chipid;
402 u32 dram_freq;
403 u32 vram_size;
404 u32 odt;
405 u32 wodt;
406 u32 rodt;
407 u32 dram_config;
408 u32 reg_PERIOD;
409 u32 reg_MADJ;
410 u32 reg_SADJ;
411 u32 reg_MRS;
412 u32 reg_EMRS;
413 u32 reg_AC1;
414 u32 reg_AC2;
415 u32 reg_DQSIC;
416 u32 reg_DRV;
417 u32 reg_IOZ;
418 u32 reg_DQIDLY;
419 u32 reg_FREQ;
420 u32 madj_max;
421 u32 dll2_finetune_step;
422 };
423
424 /*
425 * DQSI DLL CBR Setting
426 */
427 #define CBR_SIZE0 ((1 << 10) - 1)
428 #define CBR_SIZE1 ((4 << 10) - 1)
429 #define CBR_SIZE2 ((64 << 10) - 1)
430 #define CBR_PASSNUM 5
431 #define CBR_PASSNUM2 5
432 #define CBR_THRESHOLD 10
433 #define CBR_THRESHOLD2 10
434 #define TIMEOUT 5000000
435 #define CBR_PATNUM 8
436
437 static const u32 pattern[8] = {
438 0xFF00FF00,
439 0xCC33CC33,
440 0xAA55AA55,
441 0x88778877,
442 0x92CC4D6E,
443 0x543D3CDE,
444 0xF1E843C7,
445 0x7C61D253
446 };
447
448 static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
449 {
450 u32 data, timeout;
451
452 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
453 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
454 timeout = 0;
455 do {
456 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
457 if (data & 0x2000)
458 return false;
459 if (++timeout > TIMEOUT) {
460 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
461 return false;
462 }
463 } while (!data);
464 ast_moutdwm(ast, 0x1e6e0070, 0x0);
465 return true;
466 }
467
468 static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
469 {
470 u32 data, timeout;
471
472 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
473 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
474 timeout = 0;
475 do {
476 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
477 if (++timeout > TIMEOUT) {
478 ast_moutdwm(ast, 0x1e6e0070, 0x0);
479 return 0xffffffff;
480 }
481 } while (!data);
482 data = ast_mindwm(ast, 0x1e6e0078);
483 data = (data | (data >> 16)) & 0xffff;
484 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
485 return data;
486 }
487
488
489 static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
490 {
491 return mmc_test(ast, datagen, 0xc1);
492 }
493
494 static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
495 {
496 return mmc_test2(ast, datagen, 0x41);
497 }
498
499 static bool mmc_test_single(struct ast_private *ast, u32 datagen)
500 {
501 return mmc_test(ast, datagen, 0xc5);
502 }
503
504 static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
505 {
506 return mmc_test2(ast, datagen, 0x05);
507 }
508
509 static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
510 {
511 return mmc_test(ast, datagen, 0x85);
512 }
513
514 static int cbr_test(struct ast_private *ast)
515 {
516 u32 data;
517 int i;
518 data = mmc_test_single2(ast, 0);
519 if ((data & 0xff) && (data & 0xff00))
520 return 0;
521 for (i = 0; i < 8; i++) {
522 data = mmc_test_burst2(ast, i);
523 if ((data & 0xff) && (data & 0xff00))
524 return 0;
525 }
526 if (!data)
527 return 3;
528 else if (data & 0xff)
529 return 2;
530 return 1;
531 }
532
533 static int cbr_scan(struct ast_private *ast)
534 {
535 u32 data, data2, patcnt, loop;
536
537 data2 = 3;
538 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
539 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
540 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
541 if ((data = cbr_test(ast)) != 0) {
542 data2 &= data;
543 if (!data2)
544 return 0;
545 break;
546 }
547 }
548 if (loop == CBR_PASSNUM2)
549 return 0;
550 }
551 return data2;
552 }
553
554 static u32 cbr_test2(struct ast_private *ast)
555 {
556 u32 data;
557
558 data = mmc_test_burst2(ast, 0);
559 if (data == 0xffff)
560 return 0;
561 data |= mmc_test_single2(ast, 0);
562 if (data == 0xffff)
563 return 0;
564
565 return ~data & 0xffff;
566 }
567
568 static u32 cbr_scan2(struct ast_private *ast)
569 {
570 u32 data, data2, patcnt, loop;
571
572 data2 = 0xffff;
573 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
574 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
575 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
576 if ((data = cbr_test2(ast)) != 0) {
577 data2 &= data;
578 if (!data2)
579 return 0;
580 break;
581 }
582 }
583 if (loop == CBR_PASSNUM2)
584 return 0;
585 }
586 return data2;
587 }
588
589 static bool cbr_test3(struct ast_private *ast)
590 {
591 if (!mmc_test_burst(ast, 0))
592 return false;
593 if (!mmc_test_single(ast, 0))
594 return false;
595 return true;
596 }
597
598 static bool cbr_scan3(struct ast_private *ast)
599 {
600 u32 patcnt, loop;
601
602 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
603 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
604 for (loop = 0; loop < 2; loop++) {
605 if (cbr_test3(ast))
606 break;
607 }
608 if (loop == 2)
609 return false;
610 }
611 return true;
612 }
613
614 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
615 {
616 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
617 bool status = false;
618 FINETUNE_START:
619 for (cnt = 0; cnt < 16; cnt++) {
620 dllmin[cnt] = 0xff;
621 dllmax[cnt] = 0x0;
622 }
623 passcnt = 0;
624 for (dlli = 0; dlli < 76; dlli++) {
625 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
626 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
627 data = cbr_scan2(ast);
628 if (data != 0) {
629 mask = 0x00010001;
630 for (cnt = 0; cnt < 16; cnt++) {
631 if (data & mask) {
632 if (dllmin[cnt] > dlli) {
633 dllmin[cnt] = dlli;
634 }
635 if (dllmax[cnt] < dlli) {
636 dllmax[cnt] = dlli;
637 }
638 }
639 mask <<= 1;
640 }
641 passcnt++;
642 } else if (passcnt >= CBR_THRESHOLD2) {
643 break;
644 }
645 }
646 gold_sadj[0] = 0x0;
647 passcnt = 0;
648 for (cnt = 0; cnt < 16; cnt++) {
649 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
650 gold_sadj[0] += dllmin[cnt];
651 passcnt++;
652 }
653 }
654 if (retry++ > 10)
655 goto FINETUNE_DONE;
656 if (passcnt != 16) {
657 goto FINETUNE_START;
658 }
659 status = true;
660 FINETUNE_DONE:
661 gold_sadj[0] = gold_sadj[0] >> 4;
662 gold_sadj[1] = gold_sadj[0];
663
664 data = 0;
665 for (cnt = 0; cnt < 8; cnt++) {
666 data >>= 3;
667 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
668 dlli = dllmin[cnt];
669 if (gold_sadj[0] >= dlli) {
670 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
671 if (dlli > 3) {
672 dlli = 3;
673 }
674 } else {
675 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
676 if (dlli > 4) {
677 dlli = 4;
678 }
679 dlli = (8 - dlli) & 0x7;
680 }
681 data |= dlli << 21;
682 }
683 }
684 ast_moutdwm(ast, 0x1E6E0080, data);
685
686 data = 0;
687 for (cnt = 8; cnt < 16; cnt++) {
688 data >>= 3;
689 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
690 dlli = dllmin[cnt];
691 if (gold_sadj[1] >= dlli) {
692 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
693 if (dlli > 3) {
694 dlli = 3;
695 } else {
696 dlli = (dlli - 1) & 0x7;
697 }
698 } else {
699 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
700 dlli += 1;
701 if (dlli > 4) {
702 dlli = 4;
703 }
704 dlli = (8 - dlli) & 0x7;
705 }
706 data |= dlli << 21;
707 }
708 }
709 ast_moutdwm(ast, 0x1E6E0084, data);
710 return status;
711 } /* finetuneDQI_L */
712
713 static void finetuneDQSI(struct ast_private *ast)
714 {
715 u32 dlli, dqsip, dqidly;
716 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
717 u32 g_dqidly, g_dqsip, g_margin, g_side;
718 u16 pass[32][2][2];
719 char tag[2][76];
720
721 /* Disable DQI CBR */
722 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
723 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
724 reg_mcr18 &= 0x0000ffff;
725 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
726
727 for (dlli = 0; dlli < 76; dlli++) {
728 tag[0][dlli] = 0x0;
729 tag[1][dlli] = 0x0;
730 }
731 for (dqidly = 0; dqidly < 32; dqidly++) {
732 pass[dqidly][0][0] = 0xff;
733 pass[dqidly][0][1] = 0x0;
734 pass[dqidly][1][0] = 0xff;
735 pass[dqidly][1][1] = 0x0;
736 }
737 for (dqidly = 0; dqidly < 32; dqidly++) {
738 passcnt[0] = passcnt[1] = 0;
739 for (dqsip = 0; dqsip < 2; dqsip++) {
740 ast_moutdwm(ast, 0x1E6E000C, 0);
741 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
742 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
743 for (dlli = 0; dlli < 76; dlli++) {
744 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
745 ast_moutdwm(ast, 0x1E6E0070, 0);
746 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
747 if (cbr_scan3(ast)) {
748 if (dlli == 0)
749 break;
750 passcnt[dqsip]++;
751 tag[dqsip][dlli] = 'P';
752 if (dlli < pass[dqidly][dqsip][0])
753 pass[dqidly][dqsip][0] = (u16) dlli;
754 if (dlli > pass[dqidly][dqsip][1])
755 pass[dqidly][dqsip][1] = (u16) dlli;
756 } else if (passcnt[dqsip] >= 5)
757 break;
758 else {
759 pass[dqidly][dqsip][0] = 0xff;
760 pass[dqidly][dqsip][1] = 0x0;
761 }
762 }
763 }
764 if (passcnt[0] == 0 && passcnt[1] == 0)
765 dqidly++;
766 }
767 /* Search margin */
768 g_dqidly = g_dqsip = g_margin = g_side = 0;
769
770 for (dqidly = 0; dqidly < 32; dqidly++) {
771 for (dqsip = 0; dqsip < 2; dqsip++) {
772 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
773 continue;
774 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
775 if ((diff+2) < g_margin)
776 continue;
777 passcnt[0] = passcnt[1] = 0;
778 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
779 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
780 if (passcnt[0] > passcnt[1])
781 passcnt[0] = passcnt[1];
782 passcnt[1] = 0;
783 if (passcnt[0] > g_side)
784 passcnt[1] = passcnt[0] - g_side;
785 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
786 g_margin = diff;
787 g_dqidly = dqidly;
788 g_dqsip = dqsip;
789 g_side = passcnt[0];
790 } else if (passcnt[1] > 1 && g_side < 8) {
791 if (diff > g_margin)
792 g_margin = diff;
793 g_dqidly = dqidly;
794 g_dqsip = dqsip;
795 g_side = passcnt[0];
796 }
797 }
798 }
799 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
800 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
801
802 }
803 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
804 {
805 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
806 bool status = false;
807
808 finetuneDQSI(ast);
809 if (finetuneDQI_L(ast, param) == false)
810 return status;
811
812 CBR_START2:
813 dllmin[0] = dllmin[1] = 0xff;
814 dllmax[0] = dllmax[1] = 0x0;
815 passcnt = 0;
816 for (dlli = 0; dlli < 76; dlli++) {
817 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
818 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
819 data = cbr_scan(ast);
820 if (data != 0) {
821 if (data & 0x1) {
822 if (dllmin[0] > dlli) {
823 dllmin[0] = dlli;
824 }
825 if (dllmax[0] < dlli) {
826 dllmax[0] = dlli;
827 }
828 }
829 if (data & 0x2) {
830 if (dllmin[1] > dlli) {
831 dllmin[1] = dlli;
832 }
833 if (dllmax[1] < dlli) {
834 dllmax[1] = dlli;
835 }
836 }
837 passcnt++;
838 } else if (passcnt >= CBR_THRESHOLD) {
839 break;
840 }
841 }
842 if (retry++ > 10)
843 goto CBR_DONE2;
844 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
845 goto CBR_START2;
846 }
847 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
848 goto CBR_START2;
849 }
850 status = true;
851 CBR_DONE2:
852 dlli = (dllmin[1] + dllmax[1]) >> 1;
853 dlli <<= 8;
854 dlli += (dllmin[0] + dllmax[0]) >> 1;
855 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
856 return status;
857 } /* CBRDLL2 */
858
859 static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
860 {
861 u32 trap, trap_AC2, trap_MRS;
862
863 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
864
865 /* Ger trap info */
866 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
867 trap_AC2 = 0x00020000 + (trap << 16);
868 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
869 trap_MRS = 0x00000010 + (trap << 4);
870 trap_MRS |= ((trap & 0x2) << 18);
871
872 param->reg_MADJ = 0x00034C4C;
873 param->reg_SADJ = 0x00001800;
874 param->reg_DRV = 0x000000F0;
875 param->reg_PERIOD = param->dram_freq;
876 param->rodt = 0;
877
878 switch (param->dram_freq) {
879 case 336:
880 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
881 param->wodt = 0;
882 param->reg_AC1 = 0x22202725;
883 param->reg_AC2 = 0xAA007613 | trap_AC2;
884 param->reg_DQSIC = 0x000000BA;
885 param->reg_MRS = 0x04001400 | trap_MRS;
886 param->reg_EMRS = 0x00000000;
887 param->reg_IOZ = 0x00000023;
888 param->reg_DQIDLY = 0x00000074;
889 param->reg_FREQ = 0x00004DC0;
890 param->madj_max = 96;
891 param->dll2_finetune_step = 3;
892 switch (param->dram_chipid) {
893 default:
894 case AST_DRAM_512Mx16:
895 case AST_DRAM_1Gx16:
896 param->reg_AC2 = 0xAA007613 | trap_AC2;
897 break;
898 case AST_DRAM_2Gx16:
899 param->reg_AC2 = 0xAA00761C | trap_AC2;
900 break;
901 case AST_DRAM_4Gx16:
902 param->reg_AC2 = 0xAA007636 | trap_AC2;
903 break;
904 }
905 break;
906 default:
907 case 396:
908 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
909 param->wodt = 1;
910 param->reg_AC1 = 0x33302825;
911 param->reg_AC2 = 0xCC009617 | trap_AC2;
912 param->reg_DQSIC = 0x000000E2;
913 param->reg_MRS = 0x04001600 | trap_MRS;
914 param->reg_EMRS = 0x00000000;
915 param->reg_IOZ = 0x00000034;
916 param->reg_DRV = 0x000000FA;
917 param->reg_DQIDLY = 0x00000089;
918 param->reg_FREQ = 0x00005040;
919 param->madj_max = 96;
920 param->dll2_finetune_step = 4;
921
922 switch (param->dram_chipid) {
923 default:
924 case AST_DRAM_512Mx16:
925 case AST_DRAM_1Gx16:
926 param->reg_AC2 = 0xCC009617 | trap_AC2;
927 break;
928 case AST_DRAM_2Gx16:
929 param->reg_AC2 = 0xCC009622 | trap_AC2;
930 break;
931 case AST_DRAM_4Gx16:
932 param->reg_AC2 = 0xCC00963F | trap_AC2;
933 break;
934 }
935 break;
936
937 case 408:
938 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
939 param->wodt = 1;
940 param->reg_AC1 = 0x33302825;
941 param->reg_AC2 = 0xCC009617 | trap_AC2;
942 param->reg_DQSIC = 0x000000E2;
943 param->reg_MRS = 0x04001600 | trap_MRS;
944 param->reg_EMRS = 0x00000000;
945 param->reg_IOZ = 0x00000023;
946 param->reg_DRV = 0x000000FA;
947 param->reg_DQIDLY = 0x00000089;
948 param->reg_FREQ = 0x000050C0;
949 param->madj_max = 96;
950 param->dll2_finetune_step = 4;
951
952 switch (param->dram_chipid) {
953 default:
954 case AST_DRAM_512Mx16:
955 case AST_DRAM_1Gx16:
956 param->reg_AC2 = 0xCC009617 | trap_AC2;
957 break;
958 case AST_DRAM_2Gx16:
959 param->reg_AC2 = 0xCC009622 | trap_AC2;
960 break;
961 case AST_DRAM_4Gx16:
962 param->reg_AC2 = 0xCC00963F | trap_AC2;
963 break;
964 }
965
966 break;
967 case 456:
968 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
969 param->wodt = 0;
970 param->reg_AC1 = 0x33302926;
971 param->reg_AC2 = 0xCD44961A;
972 param->reg_DQSIC = 0x000000FC;
973 param->reg_MRS = 0x00081830;
974 param->reg_EMRS = 0x00000000;
975 param->reg_IOZ = 0x00000045;
976 param->reg_DQIDLY = 0x00000097;
977 param->reg_FREQ = 0x000052C0;
978 param->madj_max = 88;
979 param->dll2_finetune_step = 4;
980 break;
981 case 504:
982 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
983 param->wodt = 1;
984 param->reg_AC1 = 0x33302926;
985 param->reg_AC2 = 0xDE44A61D;
986 param->reg_DQSIC = 0x00000117;
987 param->reg_MRS = 0x00081A30;
988 param->reg_EMRS = 0x00000000;
989 param->reg_IOZ = 0x070000BB;
990 param->reg_DQIDLY = 0x000000A0;
991 param->reg_FREQ = 0x000054C0;
992 param->madj_max = 79;
993 param->dll2_finetune_step = 4;
994 break;
995 case 528:
996 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
997 param->wodt = 1;
998 param->rodt = 1;
999 param->reg_AC1 = 0x33302926;
1000 param->reg_AC2 = 0xEF44B61E;
1001 param->reg_DQSIC = 0x00000125;
1002 param->reg_MRS = 0x00081A30;
1003 param->reg_EMRS = 0x00000040;
1004 param->reg_DRV = 0x000000F5;
1005 param->reg_IOZ = 0x00000023;
1006 param->reg_DQIDLY = 0x00000088;
1007 param->reg_FREQ = 0x000055C0;
1008 param->madj_max = 76;
1009 param->dll2_finetune_step = 3;
1010 break;
1011 case 576:
1012 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1013 param->reg_MADJ = 0x00136868;
1014 param->reg_SADJ = 0x00004534;
1015 param->wodt = 1;
1016 param->rodt = 1;
1017 param->reg_AC1 = 0x33302A37;
1018 param->reg_AC2 = 0xEF56B61E;
1019 param->reg_DQSIC = 0x0000013F;
1020 param->reg_MRS = 0x00101A50;
1021 param->reg_EMRS = 0x00000040;
1022 param->reg_DRV = 0x000000FA;
1023 param->reg_IOZ = 0x00000023;
1024 param->reg_DQIDLY = 0x00000078;
1025 param->reg_FREQ = 0x000057C0;
1026 param->madj_max = 136;
1027 param->dll2_finetune_step = 3;
1028 break;
1029 case 600:
1030 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1031 param->reg_MADJ = 0x00136868;
1032 param->reg_SADJ = 0x00004534;
1033 param->wodt = 1;
1034 param->rodt = 1;
1035 param->reg_AC1 = 0x32302A37;
1036 param->reg_AC2 = 0xDF56B61F;
1037 param->reg_DQSIC = 0x0000014D;
1038 param->reg_MRS = 0x00101A50;
1039 param->reg_EMRS = 0x00000004;
1040 param->reg_DRV = 0x000000F5;
1041 param->reg_IOZ = 0x00000023;
1042 param->reg_DQIDLY = 0x00000078;
1043 param->reg_FREQ = 0x000058C0;
1044 param->madj_max = 132;
1045 param->dll2_finetune_step = 3;
1046 break;
1047 case 624:
1048 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1049 param->reg_MADJ = 0x00136868;
1050 param->reg_SADJ = 0x00004534;
1051 param->wodt = 1;
1052 param->rodt = 1;
1053 param->reg_AC1 = 0x32302A37;
1054 param->reg_AC2 = 0xEF56B621;
1055 param->reg_DQSIC = 0x0000015A;
1056 param->reg_MRS = 0x02101A50;
1057 param->reg_EMRS = 0x00000004;
1058 param->reg_DRV = 0x000000F5;
1059 param->reg_IOZ = 0x00000034;
1060 param->reg_DQIDLY = 0x00000078;
1061 param->reg_FREQ = 0x000059C0;
1062 param->madj_max = 128;
1063 param->dll2_finetune_step = 3;
1064 break;
1065 } /* switch freq */
1066
1067 switch (param->dram_chipid) {
1068 case AST_DRAM_512Mx16:
1069 param->dram_config = 0x130;
1070 break;
1071 default:
1072 case AST_DRAM_1Gx16:
1073 param->dram_config = 0x131;
1074 break;
1075 case AST_DRAM_2Gx16:
1076 param->dram_config = 0x132;
1077 break;
1078 case AST_DRAM_4Gx16:
1079 param->dram_config = 0x133;
1080 break;
1081 } /* switch size */
1082
1083 switch (param->vram_size) {
1084 default:
1085 case AST_VIDMEM_SIZE_8M:
1086 param->dram_config |= 0x00;
1087 break;
1088 case AST_VIDMEM_SIZE_16M:
1089 param->dram_config |= 0x04;
1090 break;
1091 case AST_VIDMEM_SIZE_32M:
1092 param->dram_config |= 0x08;
1093 break;
1094 case AST_VIDMEM_SIZE_64M:
1095 param->dram_config |= 0x0c;
1096 break;
1097 }
1098
1099 }
1100
1101 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1102 {
1103 u32 data, data2, retry = 0;
1104
1105 ddr3_init_start:
1106 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1107 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1108 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1109 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1110 udelay(10);
1111 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1112 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1113 udelay(10);
1114 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1115 udelay(10);
1116
1117 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1118 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1119 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1120 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1121 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1122 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1123 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1124 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1125 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1126 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1127 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1128 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1129 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1130 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1131 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1132 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1133 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1134 ast_moutdwm(ast, 0x1E6E0054, 0);
1135 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1136 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1137 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1138 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1139 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1140 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1141 /* Wait MCLK2X lock to MCLK */
1142 do {
1143 data = ast_mindwm(ast, 0x1E6E001C);
1144 } while (!(data & 0x08000000));
1145 data = ast_mindwm(ast, 0x1E6E001C);
1146 data = (data >> 8) & 0xff;
1147 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1148 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1149 if ((data2 & 0xff) > param->madj_max) {
1150 break;
1151 }
1152 ast_moutdwm(ast, 0x1E6E0064, data2);
1153 if (data2 & 0x00100000) {
1154 data2 = ((data2 & 0xff) >> 3) + 3;
1155 } else {
1156 data2 = ((data2 & 0xff) >> 2) + 5;
1157 }
1158 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1159 data2 += data & 0xff;
1160 data = data | (data2 << 8);
1161 ast_moutdwm(ast, 0x1E6E0068, data);
1162 udelay(10);
1163 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1164 udelay(10);
1165 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1166 ast_moutdwm(ast, 0x1E6E0018, data);
1167 data = data | 0x200;
1168 ast_moutdwm(ast, 0x1E6E0018, data);
1169 do {
1170 data = ast_mindwm(ast, 0x1E6E001C);
1171 } while (!(data & 0x08000000));
1172
1173 data = ast_mindwm(ast, 0x1E6E001C);
1174 data = (data >> 8) & 0xff;
1175 }
1176 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1177 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1178 ast_moutdwm(ast, 0x1E6E0018, data);
1179
1180 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1181 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1182 udelay(50);
1183 /* Mode Register Setting */
1184 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1185 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1186 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1187 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1188 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1189 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1190 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1191 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1192 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1193
1194 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1195 data = 0;
1196 if (param->wodt) {
1197 data = 0x300;
1198 }
1199 if (param->rodt) {
1200 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1201 }
1202 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1203
1204 /* Calibrate the DQSI delay */
1205 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1206 goto ddr3_init_start;
1207
1208 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1209 /* ECC Memory Initialization */
1210 #ifdef ECC
1211 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1212 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1213 do {
1214 data = ast_mindwm(ast, 0x1E6E0070);
1215 } while (!(data & 0x00001000));
1216 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1217 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1218 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1219 #endif
1220
1221
1222 }
1223
1224 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1225 {
1226 u32 trap, trap_AC2, trap_MRS;
1227
1228 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1229
1230 /* Ger trap info */
1231 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1232 trap_AC2 = (trap << 20) | (trap << 16);
1233 trap_AC2 += 0x00110000;
1234 trap_MRS = 0x00000040 | (trap << 4);
1235
1236
1237 param->reg_MADJ = 0x00034C4C;
1238 param->reg_SADJ = 0x00001800;
1239 param->reg_DRV = 0x000000F0;
1240 param->reg_PERIOD = param->dram_freq;
1241 param->rodt = 0;
1242
1243 switch (param->dram_freq) {
1244 case 264:
1245 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1246 param->wodt = 0;
1247 param->reg_AC1 = 0x11101513;
1248 param->reg_AC2 = 0x78117011;
1249 param->reg_DQSIC = 0x00000092;
1250 param->reg_MRS = 0x00000842;
1251 param->reg_EMRS = 0x00000000;
1252 param->reg_DRV = 0x000000F0;
1253 param->reg_IOZ = 0x00000034;
1254 param->reg_DQIDLY = 0x0000005A;
1255 param->reg_FREQ = 0x00004AC0;
1256 param->madj_max = 138;
1257 param->dll2_finetune_step = 3;
1258 break;
1259 case 336:
1260 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1261 param->wodt = 1;
1262 param->reg_AC1 = 0x22202613;
1263 param->reg_AC2 = 0xAA009016 | trap_AC2;
1264 param->reg_DQSIC = 0x000000BA;
1265 param->reg_MRS = 0x00000A02 | trap_MRS;
1266 param->reg_EMRS = 0x00000040;
1267 param->reg_DRV = 0x000000FA;
1268 param->reg_IOZ = 0x00000034;
1269 param->reg_DQIDLY = 0x00000074;
1270 param->reg_FREQ = 0x00004DC0;
1271 param->madj_max = 96;
1272 param->dll2_finetune_step = 3;
1273 switch (param->dram_chipid) {
1274 default:
1275 case AST_DRAM_512Mx16:
1276 param->reg_AC2 = 0xAA009012 | trap_AC2;
1277 break;
1278 case AST_DRAM_1Gx16:
1279 param->reg_AC2 = 0xAA009016 | trap_AC2;
1280 break;
1281 case AST_DRAM_2Gx16:
1282 param->reg_AC2 = 0xAA009023 | trap_AC2;
1283 break;
1284 case AST_DRAM_4Gx16:
1285 param->reg_AC2 = 0xAA00903B | trap_AC2;
1286 break;
1287 }
1288 break;
1289 default:
1290 case 396:
1291 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1292 param->wodt = 1;
1293 param->rodt = 0;
1294 param->reg_AC1 = 0x33302714;
1295 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1296 param->reg_DQSIC = 0x000000E2;
1297 param->reg_MRS = 0x00000C02 | trap_MRS;
1298 param->reg_EMRS = 0x00000040;
1299 param->reg_DRV = 0x000000FA;
1300 param->reg_IOZ = 0x00000034;
1301 param->reg_DQIDLY = 0x00000089;
1302 param->reg_FREQ = 0x00005040;
1303 param->madj_max = 96;
1304 param->dll2_finetune_step = 4;
1305
1306 switch (param->dram_chipid) {
1307 case AST_DRAM_512Mx16:
1308 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1309 break;
1310 default:
1311 case AST_DRAM_1Gx16:
1312 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1313 break;
1314 case AST_DRAM_2Gx16:
1315 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1316 break;
1317 case AST_DRAM_4Gx16:
1318 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1319 break;
1320 }
1321
1322 break;
1323
1324 case 408:
1325 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1326 param->wodt = 1;
1327 param->rodt = 0;
1328 param->reg_AC1 = 0x33302714;
1329 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1330 param->reg_DQSIC = 0x000000E2;
1331 param->reg_MRS = 0x00000C02 | trap_MRS;
1332 param->reg_EMRS = 0x00000040;
1333 param->reg_DRV = 0x000000FA;
1334 param->reg_IOZ = 0x00000034;
1335 param->reg_DQIDLY = 0x00000089;
1336 param->reg_FREQ = 0x000050C0;
1337 param->madj_max = 96;
1338 param->dll2_finetune_step = 4;
1339
1340 switch (param->dram_chipid) {
1341 case AST_DRAM_512Mx16:
1342 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1343 break;
1344 default:
1345 case AST_DRAM_1Gx16:
1346 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1347 break;
1348 case AST_DRAM_2Gx16:
1349 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1350 break;
1351 case AST_DRAM_4Gx16:
1352 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1353 break;
1354 }
1355
1356 break;
1357 case 456:
1358 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1359 param->wodt = 0;
1360 param->reg_AC1 = 0x33302815;
1361 param->reg_AC2 = 0xCD44B01E;
1362 param->reg_DQSIC = 0x000000FC;
1363 param->reg_MRS = 0x00000E72;
1364 param->reg_EMRS = 0x00000000;
1365 param->reg_DRV = 0x00000000;
1366 param->reg_IOZ = 0x00000034;
1367 param->reg_DQIDLY = 0x00000097;
1368 param->reg_FREQ = 0x000052C0;
1369 param->madj_max = 88;
1370 param->dll2_finetune_step = 3;
1371 break;
1372 case 504:
1373 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1374 param->wodt = 1;
1375 param->rodt = 1;
1376 param->reg_AC1 = 0x33302815;
1377 param->reg_AC2 = 0xDE44C022;
1378 param->reg_DQSIC = 0x00000117;
1379 param->reg_MRS = 0x00000E72;
1380 param->reg_EMRS = 0x00000040;
1381 param->reg_DRV = 0x0000000A;
1382 param->reg_IOZ = 0x00000045;
1383 param->reg_DQIDLY = 0x000000A0;
1384 param->reg_FREQ = 0x000054C0;
1385 param->madj_max = 79;
1386 param->dll2_finetune_step = 3;
1387 break;
1388 case 528:
1389 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1390 param->wodt = 1;
1391 param->rodt = 1;
1392 param->reg_AC1 = 0x33302815;
1393 param->reg_AC2 = 0xEF44D024;
1394 param->reg_DQSIC = 0x00000125;
1395 param->reg_MRS = 0x00000E72;
1396 param->reg_EMRS = 0x00000004;
1397 param->reg_DRV = 0x000000F9;
1398 param->reg_IOZ = 0x00000045;
1399 param->reg_DQIDLY = 0x000000A7;
1400 param->reg_FREQ = 0x000055C0;
1401 param->madj_max = 76;
1402 param->dll2_finetune_step = 3;
1403 break;
1404 case 552:
1405 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1406 param->wodt = 1;
1407 param->rodt = 1;
1408 param->reg_AC1 = 0x43402915;
1409 param->reg_AC2 = 0xFF44E025;
1410 param->reg_DQSIC = 0x00000132;
1411 param->reg_MRS = 0x00000E72;
1412 param->reg_EMRS = 0x00000040;
1413 param->reg_DRV = 0x0000000A;
1414 param->reg_IOZ = 0x00000045;
1415 param->reg_DQIDLY = 0x000000AD;
1416 param->reg_FREQ = 0x000056C0;
1417 param->madj_max = 76;
1418 param->dll2_finetune_step = 3;
1419 break;
1420 case 576:
1421 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1422 param->wodt = 1;
1423 param->rodt = 1;
1424 param->reg_AC1 = 0x43402915;
1425 param->reg_AC2 = 0xFF44E027;
1426 param->reg_DQSIC = 0x0000013F;
1427 param->reg_MRS = 0x00000E72;
1428 param->reg_EMRS = 0x00000004;
1429 param->reg_DRV = 0x000000F5;
1430 param->reg_IOZ = 0x00000045;
1431 param->reg_DQIDLY = 0x000000B3;
1432 param->reg_FREQ = 0x000057C0;
1433 param->madj_max = 76;
1434 param->dll2_finetune_step = 3;
1435 break;
1436 }
1437
1438 switch (param->dram_chipid) {
1439 case AST_DRAM_512Mx16:
1440 param->dram_config = 0x100;
1441 break;
1442 default:
1443 case AST_DRAM_1Gx16:
1444 param->dram_config = 0x121;
1445 break;
1446 case AST_DRAM_2Gx16:
1447 param->dram_config = 0x122;
1448 break;
1449 case AST_DRAM_4Gx16:
1450 param->dram_config = 0x123;
1451 break;
1452 } /* switch size */
1453
1454 switch (param->vram_size) {
1455 default:
1456 case AST_VIDMEM_SIZE_8M:
1457 param->dram_config |= 0x00;
1458 break;
1459 case AST_VIDMEM_SIZE_16M:
1460 param->dram_config |= 0x04;
1461 break;
1462 case AST_VIDMEM_SIZE_32M:
1463 param->dram_config |= 0x08;
1464 break;
1465 case AST_VIDMEM_SIZE_64M:
1466 param->dram_config |= 0x0c;
1467 break;
1468 }
1469 }
1470
1471 static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1472 {
1473 u32 data, data2, retry = 0;
1474
1475 ddr2_init_start:
1476 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1477 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1478 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1479 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1480 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1481 udelay(10);
1482 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1483 udelay(10);
1484
1485 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1486 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1487 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1488 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1489 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1490 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1491 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1492 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1493 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1494 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1495 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1496 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1497 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1498 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1499 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1500 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1501 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1502 ast_moutdwm(ast, 0x1E6E0054, 0);
1503 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1504 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1505 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1506 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1507 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1508 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1509
1510 /* Wait MCLK2X lock to MCLK */
1511 do {
1512 data = ast_mindwm(ast, 0x1E6E001C);
1513 } while (!(data & 0x08000000));
1514 data = ast_mindwm(ast, 0x1E6E001C);
1515 data = (data >> 8) & 0xff;
1516 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1517 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1518 if ((data2 & 0xff) > param->madj_max) {
1519 break;
1520 }
1521 ast_moutdwm(ast, 0x1E6E0064, data2);
1522 if (data2 & 0x00100000) {
1523 data2 = ((data2 & 0xff) >> 3) + 3;
1524 } else {
1525 data2 = ((data2 & 0xff) >> 2) + 5;
1526 }
1527 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1528 data2 += data & 0xff;
1529 data = data | (data2 << 8);
1530 ast_moutdwm(ast, 0x1E6E0068, data);
1531 udelay(10);
1532 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1533 udelay(10);
1534 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1535 ast_moutdwm(ast, 0x1E6E0018, data);
1536 data = data | 0x200;
1537 ast_moutdwm(ast, 0x1E6E0018, data);
1538 do {
1539 data = ast_mindwm(ast, 0x1E6E001C);
1540 } while (!(data & 0x08000000));
1541
1542 data = ast_mindwm(ast, 0x1E6E001C);
1543 data = (data >> 8) & 0xff;
1544 }
1545 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1546 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1547 ast_moutdwm(ast, 0x1E6E0018, data);
1548
1549 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1550 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1551 udelay(50);
1552 /* Mode Register Setting */
1553 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1554 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1555 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1556 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1557 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1558 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1559
1560 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1561 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1562 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1563 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1564 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1565 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1567
1568 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1569 data = 0;
1570 if (param->wodt) {
1571 data = 0x500;
1572 }
1573 if (param->rodt) {
1574 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1575 }
1576 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1577 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1578
1579 /* Calibrate the DQSI delay */
1580 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1581 goto ddr2_init_start;
1582
1583 /* ECC Memory Initialization */
1584 #ifdef ECC
1585 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1586 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1587 do {
1588 data = ast_mindwm(ast, 0x1E6E0070);
1589 } while (!(data & 0x00001000));
1590 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1591 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1592 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1593 #endif
1594
1595 }
1596
1597 static void ast_post_chip_2300(struct drm_device *dev)
1598 {
1599 struct ast_private *ast = to_ast_private(dev);
1600 struct ast2300_dram_param param;
1601 u32 temp;
1602 u8 reg;
1603
1604 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1605 if ((reg & 0x80) == 0) {/* vga only */
1606 ast_write32(ast, 0xf004, 0x1e6e0000);
1607 ast_write32(ast, 0xf000, 0x1);
1608 ast_write32(ast, 0x12000, 0x1688a8a8);
1609 do {
1610 ;
1611 } while (ast_read32(ast, 0x12000) != 0x1);
1612
1613 ast_write32(ast, 0x10000, 0xfc600309);
1614 do {
1615 ;
1616 } while (ast_read32(ast, 0x10000) != 0x1);
1617
1618 /* Slow down CPU/AHB CLK in VGA only mode */
1619 temp = ast_read32(ast, 0x12008);
1620 temp |= 0x73;
1621 ast_write32(ast, 0x12008, temp);
1622
1623 param.dram_freq = 396;
1624 param.dram_type = AST_DDR3;
1625 temp = ast_mindwm(ast, 0x1e6e2070);
1626 if (temp & 0x01000000)
1627 param.dram_type = AST_DDR2;
1628 switch (temp & 0x18000000) {
1629 case 0:
1630 param.dram_chipid = AST_DRAM_512Mx16;
1631 break;
1632 default:
1633 case 0x08000000:
1634 param.dram_chipid = AST_DRAM_1Gx16;
1635 break;
1636 case 0x10000000:
1637 param.dram_chipid = AST_DRAM_2Gx16;
1638 break;
1639 case 0x18000000:
1640 param.dram_chipid = AST_DRAM_4Gx16;
1641 break;
1642 }
1643 switch (temp & 0x0c) {
1644 default:
1645 case 0x00:
1646 param.vram_size = AST_VIDMEM_SIZE_8M;
1647 break;
1648
1649 case 0x04:
1650 param.vram_size = AST_VIDMEM_SIZE_16M;
1651 break;
1652
1653 case 0x08:
1654 param.vram_size = AST_VIDMEM_SIZE_32M;
1655 break;
1656
1657 case 0x0c:
1658 param.vram_size = AST_VIDMEM_SIZE_64M;
1659 break;
1660 }
1661
1662 if (param.dram_type == AST_DDR3) {
1663 get_ddr3_info(ast, &param);
1664 ddr3_init(ast, &param);
1665 } else {
1666 get_ddr2_info(ast, &param);
1667 ddr2_init(ast, &param);
1668 }
1669
1670 temp = ast_mindwm(ast, 0x1e6e2040);
1671 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1672 }
1673
1674 /* wait ready */
1675 do {
1676 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1677 } while ((reg & 0x40) == 0);
1678 }
1679
1680 static bool cbr_test_2500(struct ast_private *ast)
1681 {
1682 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1683 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1684 if (!mmc_test_burst(ast, 0))
1685 return false;
1686 if (!mmc_test_single_2500(ast, 0))
1687 return false;
1688 return true;
1689 }
1690
1691 static bool ddr_test_2500(struct ast_private *ast)
1692 {
1693 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1694 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1695 if (!mmc_test_burst(ast, 0))
1696 return false;
1697 if (!mmc_test_burst(ast, 1))
1698 return false;
1699 if (!mmc_test_burst(ast, 2))
1700 return false;
1701 if (!mmc_test_burst(ast, 3))
1702 return false;
1703 if (!mmc_test_single_2500(ast, 0))
1704 return false;
1705 return true;
1706 }
1707
1708 static void ddr_init_common_2500(struct ast_private *ast)
1709 {
1710 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1711 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1712 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1713 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1714 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1715 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1716 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1717 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1718 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1719 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1720 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1721 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1722 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1723 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1724 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1725 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1726 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1727 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1728 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1729 }
1730
1731 static void ddr_phy_init_2500(struct ast_private *ast)
1732 {
1733 u32 data, pass, timecnt;
1734
1735 pass = 0;
1736 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1737 while (!pass) {
1738 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1739 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1740 if (!data)
1741 break;
1742 }
1743 if (timecnt != TIMEOUT) {
1744 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1745 if (!data)
1746 pass = 1;
1747 }
1748 if (!pass) {
1749 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1750 udelay(10); /* delay 10 us */
1751 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1752 }
1753 }
1754
1755 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1756 }
1757
1758 /*
1759 * Check DRAM Size
1760 * 1Gb : 0x80000000 ~ 0x87FFFFFF
1761 * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1762 * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1763 * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1764 */
1765 static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
1766 {
1767 u32 reg_04, reg_14;
1768
1769 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1770 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1771
1772 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1773 ast_moutdwm(ast, 0x90100000, 0x35363738);
1774 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1775 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1776
1777 /* Check 8Gbit */
1778 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1779 reg_04 |= 0x03;
1780 reg_14 |= (tRFC >> 24) & 0xFF;
1781 /* Check 4Gbit */
1782 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1783 reg_04 |= 0x02;
1784 reg_14 |= (tRFC >> 16) & 0xFF;
1785 /* Check 2Gbit */
1786 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1787 reg_04 |= 0x01;
1788 reg_14 |= (tRFC >> 8) & 0xFF;
1789 } else {
1790 reg_14 |= tRFC & 0xFF;
1791 }
1792 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1793 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1794 }
1795
1796 static void enable_cache_2500(struct ast_private *ast)
1797 {
1798 u32 reg_04, data;
1799
1800 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1801 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1802
1803 do
1804 data = ast_mindwm(ast, 0x1E6E0004);
1805 while (!(data & 0x80000));
1806 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1807 }
1808
1809 static void set_mpll_2500(struct ast_private *ast)
1810 {
1811 u32 addr, data, param;
1812
1813 /* Reset MMC */
1814 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1815 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1816 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1817 ast_moutdwm(ast, addr, 0x0);
1818 addr += 4;
1819 }
1820 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1821
1822 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1823 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1824 if (data) {
1825 /* CLKIN = 25MHz */
1826 param = 0x930023E0;
1827 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1828 } else {
1829 /* CLKIN = 24MHz */
1830 param = 0x93002400;
1831 }
1832 ast_moutdwm(ast, 0x1E6E2020, param);
1833 udelay(100);
1834 }
1835
1836 static void reset_mmc_2500(struct ast_private *ast)
1837 {
1838 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1839 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1840 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1841 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1842 mdelay(100);
1843 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1844 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1845 }
1846
1847 static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
1848 {
1849
1850 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1851 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1852 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1853 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1854 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1855 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1856 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1857 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1858
1859 /* DDR PHY Setting */
1860 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1861 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1862 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1863 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1864 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1865 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1866 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1867 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1868 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1869 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1870 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1871 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1872 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1873 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1874
1875 /* Controller Setting */
1876 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1877
1878 /* Wait DDR PHY init done */
1879 ddr_phy_init_2500(ast);
1880
1881 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1882 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1883 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1884
1885 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1886 enable_cache_2500(ast);
1887 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1888 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1889 }
1890
1891 static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
1892 {
1893 u32 data, data2, pass, retrycnt;
1894 u32 ddr_vref, phy_vref;
1895 u32 min_ddr_vref = 0, min_phy_vref = 0;
1896 u32 max_ddr_vref = 0, max_phy_vref = 0;
1897
1898 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1899 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1900 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1901 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1902 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1903 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1904 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1905 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1906
1907 /* DDR PHY Setting */
1908 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1909 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1910 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1911 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1912 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1913 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1914 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1915 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1916 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1917 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1918 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1919 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1920 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1921 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1922 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1923
1924 /* Controller Setting */
1925 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1926
1927 /* Train PHY Vref first */
1928 pass = 0;
1929
1930 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1931 max_phy_vref = 0x0;
1932 pass = 0;
1933 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1934 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1935 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1936 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1937 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1938 /* Fire DFI Init */
1939 ddr_phy_init_2500(ast);
1940 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1941 if (cbr_test_2500(ast)) {
1942 pass++;
1943 data = ast_mindwm(ast, 0x1E6E03D0);
1944 data2 = data >> 8;
1945 data = data & 0xff;
1946 if (data > data2)
1947 data = data2;
1948 if (max_phy_vref < data) {
1949 max_phy_vref = data;
1950 min_phy_vref = phy_vref;
1951 }
1952 } else if (pass > 0)
1953 break;
1954 }
1955 }
1956 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1957
1958 /* Train DDR Vref next */
1959 pass = 0;
1960
1961 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1962 min_ddr_vref = 0xFF;
1963 max_ddr_vref = 0x0;
1964 pass = 0;
1965 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1966 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1967 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1968 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1969 /* Fire DFI Init */
1970 ddr_phy_init_2500(ast);
1971 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1972 if (cbr_test_2500(ast)) {
1973 pass++;
1974 if (min_ddr_vref > ddr_vref)
1975 min_ddr_vref = ddr_vref;
1976 if (max_ddr_vref < ddr_vref)
1977 max_ddr_vref = ddr_vref;
1978 } else if (pass != 0)
1979 break;
1980 }
1981 }
1982
1983 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1984 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1985 ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1986 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1987
1988 /* Wait DDR PHY init done */
1989 ddr_phy_init_2500(ast);
1990
1991 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1992 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1993 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1994
1995 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1996 enable_cache_2500(ast);
1997 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1998 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1999 }
2000
2001 static bool ast_dram_init_2500(struct ast_private *ast)
2002 {
2003 u32 data;
2004 u32 max_tries = 5;
2005
2006 do {
2007 if (max_tries-- == 0)
2008 return false;
2009 set_mpll_2500(ast);
2010 reset_mmc_2500(ast);
2011 ddr_init_common_2500(ast);
2012
2013 data = ast_mindwm(ast, 0x1E6E2070);
2014 if (data & 0x01000000)
2015 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
2016 else
2017 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
2018 } while (!ddr_test_2500(ast));
2019
2020 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
2021
2022 /* Patch code */
2023 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
2024 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2025
2026 return true;
2027 }
2028
2029 void ast_post_chip_2500(struct drm_device *dev)
2030 {
2031 struct ast_private *ast = to_ast_private(dev);
2032 u32 temp;
2033 u8 reg;
2034
2035 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2036 if ((reg & 0x80) == 0) {/* vga only */
2037 /* Clear bus lock condition */
2038 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
2039 ast_moutdwm(ast, 0x1e600084, 0x00010000);
2040 ast_moutdwm(ast, 0x1e600088, 0x00000000);
2041 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2042 ast_write32(ast, 0xf004, 0x1e6e0000);
2043 ast_write32(ast, 0xf000, 0x1);
2044 ast_write32(ast, 0x12000, 0x1688a8a8);
2045 while (ast_read32(ast, 0x12000) != 0x1)
2046 ;
2047
2048 ast_write32(ast, 0x10000, 0xfc600309);
2049 while (ast_read32(ast, 0x10000) != 0x1)
2050 ;
2051
2052 /* Slow down CPU/AHB CLK in VGA only mode */
2053 temp = ast_read32(ast, 0x12008);
2054 temp |= 0x73;
2055 ast_write32(ast, 0x12008, temp);
2056
2057 /* Reset USB port to patch USB unknown device issue */
2058 ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
2059 temp = ast_mindwm(ast, 0x1e6e2094);
2060 temp |= 0x00004000;
2061 ast_moutdwm(ast, 0x1e6e2094, temp);
2062 temp = ast_mindwm(ast, 0x1e6e2070);
2063 if (temp & 0x00800000) {
2064 ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
2065 mdelay(100);
2066 ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
2067 }
2068
2069 if (!ast_dram_init_2500(ast))
2070 drm_err(dev, "DRAM init failed !\n");
2071
2072 temp = ast_mindwm(ast, 0x1e6e2040);
2073 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2074 }
2075
2076 /* wait ready */
2077 do {
2078 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2079 } while ((reg & 0x40) == 0);
2080 }
Linux with added FPC-III support