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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / bridge / tc358768.c
blob8ed8302d6bbb410077c898a3a2d777ae0b4665ae
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/i2c.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/slab.h>
16
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_drv.h>
20 #include <drm/drm_mipi_dsi.h>
21 #include <drm/drm_of.h>
22 #include <drm/drm_panel.h>
23 #include <video/mipi_display.h>
24 #include <video/videomode.h>
25
26 /* Global (16-bit addressable) */
27 #define TC358768_CHIPID 0x0000
28 #define TC358768_SYSCTL 0x0002
29 #define TC358768_CONFCTL 0x0004
30 #define TC358768_VSDLY 0x0006
31 #define TC358768_DATAFMT 0x0008
32 #define TC358768_GPIOEN 0x000E
33 #define TC358768_GPIODIR 0x0010
34 #define TC358768_GPIOIN 0x0012
35 #define TC358768_GPIOOUT 0x0014
36 #define TC358768_PLLCTL0 0x0016
37 #define TC358768_PLLCTL1 0x0018
38 #define TC358768_CMDBYTE 0x0022
39 #define TC358768_PP_MISC 0x0032
40 #define TC358768_DSITX_DT 0x0050
41 #define TC358768_FIFOSTATUS 0x00F8
42
43 /* Debug (16-bit addressable) */
44 #define TC358768_VBUFCTRL 0x00E0
45 #define TC358768_DBG_WIDTH 0x00E2
46 #define TC358768_DBG_VBLANK 0x00E4
47 #define TC358768_DBG_DATA 0x00E8
48
49 /* TX PHY (32-bit addressable) */
50 #define TC358768_CLW_DPHYCONTTX 0x0100
51 #define TC358768_D0W_DPHYCONTTX 0x0104
52 #define TC358768_D1W_DPHYCONTTX 0x0108
53 #define TC358768_D2W_DPHYCONTTX 0x010C
54 #define TC358768_D3W_DPHYCONTTX 0x0110
55 #define TC358768_CLW_CNTRL 0x0140
56 #define TC358768_D0W_CNTRL 0x0144
57 #define TC358768_D1W_CNTRL 0x0148
58 #define TC358768_D2W_CNTRL 0x014C
59 #define TC358768_D3W_CNTRL 0x0150
60
61 /* TX PPI (32-bit addressable) */
62 #define TC358768_STARTCNTRL 0x0204
63 #define TC358768_DSITXSTATUS 0x0208
64 #define TC358768_LINEINITCNT 0x0210
65 #define TC358768_LPTXTIMECNT 0x0214
66 #define TC358768_TCLK_HEADERCNT 0x0218
67 #define TC358768_TCLK_TRAILCNT 0x021C
68 #define TC358768_THS_HEADERCNT 0x0220
69 #define TC358768_TWAKEUP 0x0224
70 #define TC358768_TCLK_POSTCNT 0x0228
71 #define TC358768_THS_TRAILCNT 0x022C
72 #define TC358768_HSTXVREGCNT 0x0230
73 #define TC358768_HSTXVREGEN 0x0234
74 #define TC358768_TXOPTIONCNTRL 0x0238
75 #define TC358768_BTACNTRL1 0x023C
76
77 /* TX CTRL (32-bit addressable) */
78 #define TC358768_DSI_CONTROL 0x040C
79 #define TC358768_DSI_STATUS 0x0410
80 #define TC358768_DSI_INT 0x0414
81 #define TC358768_DSI_INT_ENA 0x0418
82 #define TC358768_DSICMD_RDFIFO 0x0430
83 #define TC358768_DSI_ACKERR 0x0434
84 #define TC358768_DSI_ACKERR_INTENA 0x0438
85 #define TC358768_DSI_ACKERR_HALT 0x043c
86 #define TC358768_DSI_RXERR 0x0440
87 #define TC358768_DSI_RXERR_INTENA 0x0444
88 #define TC358768_DSI_RXERR_HALT 0x0448
89 #define TC358768_DSI_ERR 0x044C
90 #define TC358768_DSI_ERR_INTENA 0x0450
91 #define TC358768_DSI_ERR_HALT 0x0454
92 #define TC358768_DSI_CONFW 0x0500
93 #define TC358768_DSI_LPCMD 0x0500
94 #define TC358768_DSI_RESET 0x0504
95 #define TC358768_DSI_INT_CLR 0x050C
96 #define TC358768_DSI_START 0x0518
97
98 /* DSITX CTRL (16-bit addressable) */
99 #define TC358768_DSICMD_TX 0x0600
100 #define TC358768_DSICMD_TYPE 0x0602
101 #define TC358768_DSICMD_WC 0x0604
102 #define TC358768_DSICMD_WD0 0x0610
103 #define TC358768_DSICMD_WD1 0x0612
104 #define TC358768_DSICMD_WD2 0x0614
105 #define TC358768_DSICMD_WD3 0x0616
106 #define TC358768_DSI_EVENT 0x0620
107 #define TC358768_DSI_VSW 0x0622
108 #define TC358768_DSI_VBPR 0x0624
109 #define TC358768_DSI_VACT 0x0626
110 #define TC358768_DSI_HSW 0x0628
111 #define TC358768_DSI_HBPR 0x062A
112 #define TC358768_DSI_HACT 0x062C
113
114 /* TC358768_DSI_CONTROL (0x040C) register */
115 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15)
116 #define TC358768_DSI_CONTROL_TXMD BIT(7)
117 #define TC358768_DSI_CONTROL_HSCKMD BIT(5)
118 #define TC358768_DSI_CONTROL_EOTDIS BIT(0)
119
120 /* TC358768_DSI_CONFW (0x0500) register */
121 #define TC358768_DSI_CONFW_MODE_SET (5 << 29)
122 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
123 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24)
124
125 static const char * const tc358768_supplies[] = {
126 "vddc", "vddmipi", "vddio"
127 };
128
129 struct tc358768_dsi_output {
130 struct mipi_dsi_device *dev;
131 struct drm_panel *panel;
132 struct drm_bridge *bridge;
133 };
134
135 struct tc358768_priv {
136 struct device *dev;
137 struct regmap *regmap;
138 struct gpio_desc *reset_gpio;
139 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
140 struct clk *refclk;
141 int enabled;
142 int error;
143
144 struct mipi_dsi_host dsi_host;
145 struct drm_bridge bridge;
146 struct tc358768_dsi_output output;
147
148 u32 pd_lines; /* number of Parallel Port Input Data Lines */
149 u32 dsi_lanes; /* number of DSI Lanes */
150
151 /* Parameters for PLL programming */
152 u32 fbd; /* PLL feedback divider */
153 u32 prd; /* PLL input divider */
154 u32 frs; /* PLL Freqency range for HSCK (post divider) */
155
156 u32 dsiclk; /* pll_clk / 2 */
157 };
158
159 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
160 *host)
161 {
162 return container_of(host, struct tc358768_priv, dsi_host);
163 }
164
165 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
166 *bridge)
167 {
168 return container_of(bridge, struct tc358768_priv, bridge);
169 }
170
171 static int tc358768_clear_error(struct tc358768_priv *priv)
172 {
173 int ret = priv->error;
174
175 priv->error = 0;
176 return ret;
177 }
178
179 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
180 {
181 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
182 int tmpval = val;
183 size_t count = 2;
184
185 if (priv->error)
186 return;
187
188 /* 16-bit register? */
189 if (reg < 0x100 || reg >= 0x600)
190 count = 1;
191
192 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
193 }
194
195 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
196 {
197 size_t count = 2;
198
199 if (priv->error)
200 return;
201
202 /* 16-bit register? */
203 if (reg < 0x100 || reg >= 0x600) {
204 *val = 0;
205 count = 1;
206 }
207
208 priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
209 }
210
211 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
212 u32 val)
213 {
214 u32 tmp, orig;
215
216 tc358768_read(priv, reg, &orig);
217 tmp = orig & ~mask;
218 tmp |= val & mask;
219 if (tmp != orig)
220 tc358768_write(priv, reg, tmp);
221 }
222
223 static int tc358768_sw_reset(struct tc358768_priv *priv)
224 {
225 /* Assert Reset */
226 tc358768_write(priv, TC358768_SYSCTL, 1);
227 /* Release Reset, Exit Sleep */
228 tc358768_write(priv, TC358768_SYSCTL, 0);
229
230 return tc358768_clear_error(priv);
231 }
232
233 static void tc358768_hw_enable(struct tc358768_priv *priv)
234 {
235 int ret;
236
237 if (priv->enabled)
238 return;
239
240 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
241 if (ret < 0)
242 dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
243
244 if (priv->reset_gpio)
245 usleep_range(200, 300);
246
247 /*
248 * The RESX is active low (GPIO_ACTIVE_LOW).
249 * DEASSERT (value = 0) the reset_gpio to enable the chip
250 */
251 gpiod_set_value_cansleep(priv->reset_gpio, 0);
252
253 /* wait for encoder clocks to stabilize */
254 usleep_range(1000, 2000);
255
256 priv->enabled = true;
257 }
258
259 static void tc358768_hw_disable(struct tc358768_priv *priv)
260 {
261 int ret;
262
263 if (!priv->enabled)
264 return;
265
266 /*
267 * The RESX is active low (GPIO_ACTIVE_LOW).
268 * ASSERT (value = 1) the reset_gpio to disable the chip
269 */
270 gpiod_set_value_cansleep(priv->reset_gpio, 1);
271
272 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
273 priv->supplies);
274 if (ret < 0)
275 dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
276
277 priv->enabled = false;
278 }
279
280 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
281 {
282 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines);
283 }
284
285 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
286 {
287 return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
288 }
289
290 static int tc358768_calc_pll(struct tc358768_priv *priv,
291 const struct drm_display_mode *mode,
292 bool verify_only)
293 {
294 const u32 frs_limits[] = {
295 1000000000,
296 500000000,
297 250000000,
298 125000000,
299 62500000
300 };
301 unsigned long refclk;
302 u32 prd, target_pll, i, max_pll, min_pll;
303 u32 frs, best_diff, best_pll, best_prd, best_fbd;
304
305 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
306
307 /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */
308
309 for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
310 if (target_pll >= frs_limits[i])
311 break;
312
313 if (i == ARRAY_SIZE(frs_limits) || i == 0)
314 return -EINVAL;
315
316 frs = i - 1;
317 max_pll = frs_limits[i - 1];
318 min_pll = frs_limits[i];
319
320 refclk = clk_get_rate(priv->refclk);
321
322 best_diff = UINT_MAX;
323 best_pll = 0;
324 best_prd = 0;
325 best_fbd = 0;
326
327 for (prd = 0; prd < 16; ++prd) {
328 u32 divisor = (prd + 1) * (1 << frs);
329 u32 fbd;
330
331 for (fbd = 0; fbd < 512; ++fbd) {
332 u32 pll, diff;
333
334 pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
335
336 if (pll >= max_pll || pll < min_pll)
337 continue;
338
339 diff = max(pll, target_pll) - min(pll, target_pll);
340
341 if (diff < best_diff) {
342 best_diff = diff;
343 best_pll = pll;
344 best_prd = prd;
345 best_fbd = fbd;
346
347 if (best_diff == 0)
348 goto found;
349 }
350 }
351 }
352
353 if (best_diff == UINT_MAX) {
354 dev_err(priv->dev, "could not find suitable PLL setup\n");
355 return -EINVAL;
356 }
357
358 found:
359 if (verify_only)
360 return 0;
361
362 priv->fbd = best_fbd;
363 priv->prd = best_prd;
364 priv->frs = frs;
365 priv->dsiclk = best_pll / 2;
366
367 return 0;
368 }
369
370 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
371 struct mipi_dsi_device *dev)
372 {
373 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
374 struct drm_bridge *bridge;
375 struct drm_panel *panel;
376 struct device_node *ep;
377 int ret;
378
379 if (dev->lanes > 4) {
380 dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
381 dev->lanes);
382 return -EINVAL;
383 }
384
385 /*
386 * tc358768 supports both Video and Pulse mode, but the driver only
387 * implements Video (event) mode currently
388 */
389 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
390 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
391 return -ENOTSUPP;
392 }
393
394 /*
395 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
396 * RGB888 is verified.
397 */
398 if (dev->format != MIPI_DSI_FMT_RGB888) {
399 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
400 return -ENOTSUPP;
401 }
402
403 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
404 &bridge);
405 if (ret)
406 return ret;
407
408 if (panel) {
409 bridge = drm_panel_bridge_add_typed(panel,
410 DRM_MODE_CONNECTOR_DSI);
411 if (IS_ERR(bridge))
412 return PTR_ERR(bridge);
413 }
414
415 priv->output.dev = dev;
416 priv->output.bridge = bridge;
417 priv->output.panel = panel;
418
419 priv->dsi_lanes = dev->lanes;
420
421 /* get input ep (port0/endpoint0) */
422 ret = -EINVAL;
423 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
424 if (ep) {
425 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
426
427 of_node_put(ep);
428 }
429
430 if (ret)
431 priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format);
432
433 drm_bridge_add(&priv->bridge);
434
435 return 0;
436 }
437
438 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
439 struct mipi_dsi_device *dev)
440 {
441 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
442
443 drm_bridge_remove(&priv->bridge);
444 if (priv->output.panel)
445 drm_panel_bridge_remove(priv->output.bridge);
446
447 return 0;
448 }
449
450 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
451 const struct mipi_dsi_msg *msg)
452 {
453 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
454 struct mipi_dsi_packet packet;
455 int ret;
456
457 if (!priv->enabled) {
458 dev_err(priv->dev, "Bridge is not enabled\n");
459 return -ENODEV;
460 }
461
462 if (msg->rx_len) {
463 dev_warn(priv->dev, "MIPI rx is not supported\n");
464 return -ENOTSUPP;
465 }
466
467 if (msg->tx_len > 8) {
468 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
469 return -ENOTSUPP;
470 }
471
472 ret = mipi_dsi_create_packet(&packet, msg);
473 if (ret)
474 return ret;
475
476 if (mipi_dsi_packet_format_is_short(msg->type)) {
477 tc358768_write(priv, TC358768_DSICMD_TYPE,
478 (0x10 << 8) | (packet.header[0] & 0x3f));
479 tc358768_write(priv, TC358768_DSICMD_WC, 0);
480 tc358768_write(priv, TC358768_DSICMD_WD0,
481 (packet.header[2] << 8) | packet.header[1]);
482 } else {
483 int i;
484
485 tc358768_write(priv, TC358768_DSICMD_TYPE,
486 (0x40 << 8) | (packet.header[0] & 0x3f));
487 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
488 for (i = 0; i < packet.payload_length; i += 2) {
489 u16 val = packet.payload[i];
490
491 if (i + 1 < packet.payload_length)
492 val |= packet.payload[i + 1] << 8;
493
494 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
495 }
496 }
497
498 /* start transfer */
499 tc358768_write(priv, TC358768_DSICMD_TX, 1);
500
501 ret = tc358768_clear_error(priv);
502 if (ret)
503 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
504 else
505 ret = packet.size;
506
507 return ret;
508 }
509
510 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
511 .attach = tc358768_dsi_host_attach,
512 .detach = tc358768_dsi_host_detach,
513 .transfer = tc358768_dsi_host_transfer,
514 };
515
516 static int tc358768_bridge_attach(struct drm_bridge *bridge,
517 enum drm_bridge_attach_flags flags)
518 {
519 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
520
521 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
522 dev_err(priv->dev, "needs atomic updates support\n");
523 return -ENOTSUPP;
524 }
525
526 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
527 flags);
528 }
529
530 static enum drm_mode_status
531 tc358768_bridge_mode_valid(struct drm_bridge *bridge,
532 const struct drm_display_info *info,
533 const struct drm_display_mode *mode)
534 {
535 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
536
537 if (tc358768_calc_pll(priv, mode, true))
538 return MODE_CLOCK_RANGE;
539
540 return MODE_OK;
541 }
542
543 static void tc358768_bridge_disable(struct drm_bridge *bridge)
544 {
545 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
546 int ret;
547
548 /* set FrmStop */
549 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
550
551 /* wait at least for one frame */
552 msleep(50);
553
554 /* clear PP_en */
555 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
556
557 /* set RstPtr */
558 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
559
560 ret = tc358768_clear_error(priv);
561 if (ret)
562 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
563 }
564
565 static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
566 {
567 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
568
569 tc358768_hw_disable(priv);
570 }
571
572 static int tc358768_setup_pll(struct tc358768_priv *priv,
573 const struct drm_display_mode *mode)
574 {
575 u32 fbd, prd, frs;
576 int ret;
577
578 ret = tc358768_calc_pll(priv, mode, false);
579 if (ret) {
580 dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
581 return ret;
582 }
583
584 fbd = priv->fbd;
585 prd = priv->prd;
586 frs = priv->frs;
587
588 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
589 clk_get_rate(priv->refclk), fbd, prd, frs);
590 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n",
591 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
592 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
593 tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
594 mode->clock * 1000);
595
596 /* PRD[15:12] FBD[8:0] */
597 tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd);
598
599 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
600 tc358768_write(priv, TC358768_PLLCTL1,
601 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
602
603 /* wait for lock */
604 usleep_range(1000, 2000);
605
606 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
607 tc358768_write(priv, TC358768_PLLCTL1,
608 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
609
610 return tc358768_clear_error(priv);
611 }
612
613 #define TC358768_PRECISION 1000
614 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk)
615 {
616 return (ns * TC358768_PRECISION + period_nsk) / period_nsk;
617 }
618
619 static u32 tc358768_to_ns(u32 nsk)
620 {
621 return (nsk / TC358768_PRECISION);
622 }
623
624 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
625 {
626 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
627 struct mipi_dsi_device *dsi_dev = priv->output.dev;
628 u32 val, val2, lptxcnt, hact, data_type;
629 const struct drm_display_mode *mode;
630 u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
631 u32 dsiclk, dsibclk;
632 int ret, i;
633
634 tc358768_hw_enable(priv);
635
636 ret = tc358768_sw_reset(priv);
637 if (ret) {
638 dev_err(priv->dev, "Software reset failed: %d\n", ret);
639 tc358768_hw_disable(priv);
640 return;
641 }
642
643 mode = &bridge->encoder->crtc->state->adjusted_mode;
644 ret = tc358768_setup_pll(priv, mode);
645 if (ret) {
646 dev_err(priv->dev, "PLL setup failed: %d\n", ret);
647 tc358768_hw_disable(priv);
648 return;
649 }
650
651 dsiclk = priv->dsiclk;
652 dsibclk = dsiclk / 4;
653
654 /* Data Format Control Register */
655 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
656 switch (dsi_dev->format) {
657 case MIPI_DSI_FMT_RGB888:
658 val |= (0x3 << 4);
659 hact = mode->hdisplay * 3;
660 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
661 break;
662 case MIPI_DSI_FMT_RGB666:
663 val |= (0x4 << 4);
664 hact = mode->hdisplay * 3;
665 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
666 break;
667
668 case MIPI_DSI_FMT_RGB666_PACKED:
669 val |= (0x4 << 4) | BIT(3);
670 hact = mode->hdisplay * 18 / 8;
671 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
672 break;
673
674 case MIPI_DSI_FMT_RGB565:
675 val |= (0x5 << 4);
676 hact = mode->hdisplay * 2;
677 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
678 break;
679 default:
680 dev_err(priv->dev, "Invalid data format (%u)\n",
681 dsi_dev->format);
682 tc358768_hw_disable(priv);
683 return;
684 }
685
686 /* VSDly[9:0] */
687 tc358768_write(priv, TC358768_VSDLY, 1);
688
689 tc358768_write(priv, TC358768_DATAFMT, val);
690 tc358768_write(priv, TC358768_DSITX_DT, data_type);
691
692 /* Enable D-PHY (HiZ->LP11) */
693 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
694 /* Enable lanes */
695 for (i = 0; i < dsi_dev->lanes; i++)
696 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
697
698 /* DSI Timings */
699 dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION,
700 dsibclk);
701 dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk);
702 ui_nsk = dsiclk_nsk / 2;
703 phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk;
704 dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk);
705 dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk);
706 dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk);
707 dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk);
708
709 /* LP11 > 100us for D-PHY Rx Init */
710 val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
711 dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val);
712 tc358768_write(priv, TC358768_LINEINITCNT, val);
713
714 /* LPTimeCnt > 50ns */
715 val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1;
716 lptxcnt = val;
717 dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val);
718 tc358768_write(priv, TC358768_LPTXTIMECNT, val);
719
720 /* 38ns < TCLK_PREPARE < 95ns */
721 val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
722 /* TCLK_PREPARE > 300ns */
723 val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk),
724 dsibclk_nsk);
725 val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8;
726 dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
727 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
728
729 /* TCLK_TRAIL > 60ns + 3*UI */
730 val = 60 + tc358768_to_ns(3 * ui_nsk);
731 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5;
732 dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
733 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
734
735 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
736 val = 50 + tc358768_to_ns(4 * ui_nsk);
737 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
738 /* THS_ZERO > 145ns + 10*UI */
739 val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk);
740 val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8;
741 dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
742 tc358768_write(priv, TC358768_THS_HEADERCNT, val);
743
744 /* TWAKEUP > 1ms in lptxcnt steps */
745 val = tc358768_ns_to_cnt(1020000, dsibclk_nsk);
746 val = val / (lptxcnt + 1) - 1;
747 dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val);
748 tc358768_write(priv, TC358768_TWAKEUP, val);
749
750 /* TCLK_POSTCNT > 60ns + 52*UI */
751 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk),
752 dsibclk_nsk) - 3;
753 dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
754 tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
755
756 /* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */
757 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk),
758 dsibclk_nsk) - 5;
759 dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
760 tc358768_write(priv, TC358768_THS_TRAILCNT, val);
761
762 val = BIT(0);
763 for (i = 0; i < dsi_dev->lanes; i++)
764 val |= BIT(i + 1);
765 tc358768_write(priv, TC358768_HSTXVREGEN, val);
766
767 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
768 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1);
769
770 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
771 val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
772 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
773 val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
774 dsibclk_nsk) - 2;
775 val |= val2 << 16;
776 dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val);
777 tc358768_write(priv, TC358768_BTACNTRL1, val);
778
779 /* START[0] */
780 tc358768_write(priv, TC358768_STARTCNTRL, 1);
781
782 /* Set event mode */
783 tc358768_write(priv, TC358768_DSI_EVENT, 1);
784
785 /* vsw (+ vbp) */
786 tc358768_write(priv, TC358768_DSI_VSW,
787 mode->vtotal - mode->vsync_start);
788 /* vbp (not used in event mode) */
789 tc358768_write(priv, TC358768_DSI_VBPR, 0);
790 /* vact */
791 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
792
793 /* (hsw + hbp) * byteclk * ndl / pclk */
794 val = (u32)div_u64((mode->htotal - mode->hsync_start) *
795 ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
796 mode->clock * 1000);
797 tc358768_write(priv, TC358768_DSI_HSW, val);
798 /* hbp (not used in event mode) */
799 tc358768_write(priv, TC358768_DSI_HBPR, 0);
800 /* hact (bytes) */
801 tc358768_write(priv, TC358768_DSI_HACT, hact);
802
803 /* VSYNC polarity */
804 if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
805 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5));
806 /* HSYNC polarity */
807 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
808 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0));
809
810 /* Start DSI Tx */
811 tc358768_write(priv, TC358768_DSI_START, 0x1);
812
813 /* Configure DSI_Control register */
814 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
815 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
816 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
817 tc358768_write(priv, TC358768_DSI_CONFW, val);
818
819 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
820 val |= (dsi_dev->lanes - 1) << 1;
821
822 if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM))
823 val |= TC358768_DSI_CONTROL_TXMD;
824
825 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
826 val |= TC358768_DSI_CONTROL_HSCKMD;
827
828 if (dsi_dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
829 val |= TC358768_DSI_CONTROL_EOTDIS;
830
831 tc358768_write(priv, TC358768_DSI_CONFW, val);
832
833 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
834 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
835 tc358768_write(priv, TC358768_DSI_CONFW, val);
836
837 ret = tc358768_clear_error(priv);
838 if (ret) {
839 dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret);
840 tc358768_bridge_disable(bridge);
841 tc358768_bridge_post_disable(bridge);
842 }
843 }
844
845 static void tc358768_bridge_enable(struct drm_bridge *bridge)
846 {
847 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
848 int ret;
849
850 if (!priv->enabled) {
851 dev_err(priv->dev, "Bridge is not enabled\n");
852 return;
853 }
854
855 /* clear FrmStop and RstPtr */
856 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
857
858 /* set PP_en */
859 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
860
861 ret = tc358768_clear_error(priv);
862 if (ret) {
863 dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
864 tc358768_bridge_disable(bridge);
865 tc358768_bridge_post_disable(bridge);
866 }
867 }
868
869 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
870 .attach = tc358768_bridge_attach,
871 .mode_valid = tc358768_bridge_mode_valid,
872 .pre_enable = tc358768_bridge_pre_enable,
873 .enable = tc358768_bridge_enable,
874 .disable = tc358768_bridge_disable,
875 .post_disable = tc358768_bridge_post_disable,
876 };
877
878 static const struct drm_bridge_timings default_tc358768_timings = {
879 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
880 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
881 | DRM_BUS_FLAG_DE_HIGH,
882 };
883
884 static bool tc358768_is_reserved_reg(unsigned int reg)
885 {
886 switch (reg) {
887 case 0x114 ... 0x13f:
888 case 0x200:
889 case 0x20c:
890 case 0x400 ... 0x408:
891 case 0x41c ... 0x42f:
892 return true;
893 default:
894 return false;
895 }
896 }
897
898 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
899 {
900 if (tc358768_is_reserved_reg(reg))
901 return false;
902
903 switch (reg) {
904 case TC358768_CHIPID:
905 case TC358768_FIFOSTATUS:
906 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
907 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
908 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
909 return false;
910 default:
911 return true;
912 }
913 }
914
915 static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
916 {
917 if (tc358768_is_reserved_reg(reg))
918 return false;
919
920 switch (reg) {
921 case TC358768_STARTCNTRL:
922 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
923 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
924 case TC358768_DSI_START ... (TC358768_DSI_START + 2):
925 case TC358768_DBG_DATA:
926 return false;
927 default:
928 return true;
929 }
930 }
931
932 static const struct regmap_config tc358768_regmap_config = {
933 .name = "tc358768",
934 .reg_bits = 16,
935 .val_bits = 16,
936 .max_register = TC358768_DSI_HACT,
937 .cache_type = REGCACHE_NONE,
938 .writeable_reg = tc358768_writeable_reg,
939 .readable_reg = tc358768_readable_reg,
940 .reg_format_endian = REGMAP_ENDIAN_BIG,
941 .val_format_endian = REGMAP_ENDIAN_BIG,
942 };
943
944 static const struct i2c_device_id tc358768_i2c_ids[] = {
945 { "tc358768", 0 },
946 { "tc358778", 0 },
947 { }
948 };
949 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
950
951 static const struct of_device_id tc358768_of_ids[] = {
952 { .compatible = "toshiba,tc358768", },
953 { .compatible = "toshiba,tc358778", },
954 { }
955 };
956 MODULE_DEVICE_TABLE(of, tc358768_of_ids);
957
958 static int tc358768_get_regulators(struct tc358768_priv *priv)
959 {
960 int i, ret;
961
962 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
963 priv->supplies[i].supply = tc358768_supplies[i];
964
965 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
966 priv->supplies);
967 if (ret < 0)
968 dev_err(priv->dev, "failed to get regulators: %d\n", ret);
969
970 return ret;
971 }
972
973 static int tc358768_i2c_probe(struct i2c_client *client,
974 const struct i2c_device_id *id)
975 {
976 struct tc358768_priv *priv;
977 struct device *dev = &client->dev;
978 struct device_node *np = dev->of_node;
979 int ret;
980
981 if (!np)
982 return -ENODEV;
983
984 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
985 if (!priv)
986 return -ENOMEM;
987
988 dev_set_drvdata(dev, priv);
989 priv->dev = dev;
990
991 ret = tc358768_get_regulators(priv);
992 if (ret)
993 return ret;
994
995 priv->refclk = devm_clk_get(dev, "refclk");
996 if (IS_ERR(priv->refclk))
997 return PTR_ERR(priv->refclk);
998
999 /*
1000 * RESX is low active, to disable tc358768 initially (keep in reset)
1001 * the gpio line must be LOW. This is the ASSERTED state of
1002 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1003 */
1004 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1005 GPIOD_OUT_HIGH);
1006 if (IS_ERR(priv->reset_gpio))
1007 return PTR_ERR(priv->reset_gpio);
1008
1009 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1010 if (IS_ERR(priv->regmap)) {
1011 dev_err(dev, "Failed to init regmap\n");
1012 return PTR_ERR(priv->regmap);
1013 }
1014
1015 priv->dsi_host.dev = dev;
1016 priv->dsi_host.ops = &tc358768_dsi_host_ops;
1017
1018 priv->bridge.funcs = &tc358768_bridge_funcs;
1019 priv->bridge.timings = &default_tc358768_timings;
1020 priv->bridge.of_node = np;
1021
1022 i2c_set_clientdata(client, priv);
1023
1024 return mipi_dsi_host_register(&priv->dsi_host);
1025 }
1026
1027 static int tc358768_i2c_remove(struct i2c_client *client)
1028 {
1029 struct tc358768_priv *priv = i2c_get_clientdata(client);
1030
1031 mipi_dsi_host_unregister(&priv->dsi_host);
1032
1033 return 0;
1034 }
1035
1036 static struct i2c_driver tc358768_driver = {
1037 .driver = {
1038 .name = "tc358768",
1039 .of_match_table = tc358768_of_ids,
1040 },
1041 .id_table = tc358768_i2c_ids,
1042 .probe = tc358768_i2c_probe,
1043 .remove = tc358768_i2c_remove,
1044 };
1045 module_i2c_driver(tc358768_driver);
1046
1047 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1048 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1049 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support