| blob | 8496f230c0f0f916495de27ca92f9b238629692d |
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 *
4 * Cloned from drivers/media/video/s5p-tv/regs-hdmi.h
5 *
6 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * http://www.samsung.com/
8 *
9 * HDMI register header file for Samsung TVOUT driver
10 */
12 #ifndef SAMSUNG_REGS_HDMI_H
13 #define SAMSUNG_REGS_HDMI_H
15 /*
16 * Register part
17 */
19 /* HDMI Version 1.3 & Common */
20 #define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
21 #define HDMI_CORE_BASE(x) ((x) + 0x00010000)
22 #define HDMI_I2S_BASE(x) ((x) + 0x00040000)
23 #define HDMI_TG_BASE(x) ((x) + 0x00050000)
25 /* Control registers */
26 #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
27 #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
28 #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
29 #define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
30 #define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018)
31 #define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C)
32 #define HDMI_V13_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)
34 /* Core registers */
35 #define HDMI_CON_0 HDMI_CORE_BASE(0x0000)
36 #define HDMI_CON_1 HDMI_CORE_BASE(0x0004)
37 #define HDMI_CON_2 HDMI_CORE_BASE(0x0008)
38 #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)
39 #define HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014)
40 #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)
41 #define HDMI_HPD HDMI_CORE_BASE(0x0030)
42 #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)
43 #define HDMI_ENC_EN HDMI_CORE_BASE(0x0044)
44 #define HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)
45 #define HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)
46 #define HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)
47 #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)
48 #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)
49 #define HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0)
50 #define HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4)
51 #define HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8)
52 #define HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)
53 #define HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)
54 #define HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)
55 #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)
56 #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)
57 #define HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)
58 #define HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)
59 #define HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)
60 #define HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)
61 #define HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)
62 #define HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)
63 #define HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)
64 #define HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)
65 #define HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)
66 #define HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)
67 #define HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)
68 #define HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)
69 #define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)
70 #define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)
71 #define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)
72 #define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300)
73 #define HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n))
74 #define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0)
75 #define HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)
76 #define HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8)
77 #define HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360)
78 #define HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400)
80 /* Timing generator registers */
81 #define HDMI_TG_CMD HDMI_TG_BASE(0x0000)
82 #define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)
83 #define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C)
84 #define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020)
85 #define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024)
86 #define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028)
87 #define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C)
88 #define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030)
89 #define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034)
90 #define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038)
91 #define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C)
92 #define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040)
93 #define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044)
94 #define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048)
95 #define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C)
96 #define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050)
97 #define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054)
98 #define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058)
99 #define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C)
100 #define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060)
101 #define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064)
102 #define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078)
103 #define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C)
104 #define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080)
105 #define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084)
106 #define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088)
107 #define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C)
108 #define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090)
109 #define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094)
111 /*
112 * Bit definition part
113 */
115 /* HDMI_INTC_CON */
116 #define HDMI_INTC_EN_GLOBAL (1 << 6)
117 #define HDMI_INTC_EN_HPD_PLUG (1 << 3)
118 #define HDMI_INTC_EN_HPD_UNPLUG (1 << 2)
120 /* HDMI_INTC_FLAG */
121 #define HDMI_INTC_FLAG_HPD_PLUG (1 << 3)
122 #define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2)
124 /* HDMI_PHY_RSTOUT */
125 #define HDMI_PHY_SW_RSTOUT (1 << 0)
127 /* HDMI_CORE_RSTOUT */
128 #define HDMI_CORE_SW_RSTOUT (1 << 0)
130 /* HDMI_CON_0 */
131 #define HDMI_BLUE_SCR_EN (1 << 5)
132 #define HDMI_ASP_EN (1 << 2)
133 #define HDMI_ASP_DIS (0 << 2)
134 #define HDMI_ASP_MASK (1 << 2)
135 #define HDMI_EN (1 << 0)
137 /* HDMI_CON_2 */
138 #define HDMI_VID_PREAMBLE_DIS (1 << 5)
139 #define HDMI_GUARD_BAND_DIS (1 << 1)
141 /* HDMI_PHY_STATUS */
142 #define HDMI_PHY_STATUS_READY (1 << 0)
144 /* HDMI_MODE_SEL */
145 #define HDMI_MODE_HDMI_EN (1 << 1)
146 #define HDMI_MODE_DVI_EN (1 << 0)
147 #define HDMI_MODE_MASK (3 << 0)
149 /* HDMI_TG_CMD */
150 #define HDMI_TG_EN (1 << 0)
151 #define HDMI_FIELD_EN (1 << 1)
154 /* HDMI Version 1.4 */
155 /* Control registers */
156 /* #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) */
157 /* #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) */
158 #define HDMI_HDCP_KEY_LOAD HDMI_CTRL_BASE(0x0008)
159 /* #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) */
160 #define HDMI_INTC_CON_1 HDMI_CTRL_BASE(0x0010)
161 #define HDMI_INTC_FLAG_1 HDMI_CTRL_BASE(0x0014)
162 #define HDMI_PHY_STATUS_0 HDMI_CTRL_BASE(0x0020)
163 #define HDMI_PHY_STATUS_CMU HDMI_CTRL_BASE(0x0024)
164 #define HDMI_PHY_STATUS_PLL HDMI_CTRL_BASE(0x0028)
165 #define HDMI_PHY_CON_0 HDMI_CTRL_BASE(0x0030)
166 #define HDMI_HPD_CTRL HDMI_CTRL_BASE(0x0040)
167 #define HDMI_HPD_ST HDMI_CTRL_BASE(0x0044)
168 #define HDMI_HPD_TH_X HDMI_CTRL_BASE(0x0050)
169 #define HDMI_AUDIO_CLKSEL HDMI_CTRL_BASE(0x0070)
170 #define HDMI_V14_PHY_RSTOUT HDMI_CTRL_BASE(0x0074)
171 #define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0078)
172 #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C)
173 #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080)
175 /* PHY Control bit definition */
177 /* HDMI_PHY_CON_0 */
178 #define HDMI_PHY_POWER_OFF_EN (1 << 0)
180 /* Video related registers */
181 #define HDMI_YMAX HDMI_CORE_BASE(0x0060)
182 #define HDMI_YMIN HDMI_CORE_BASE(0x0064)
183 #define HDMI_CMAX HDMI_CORE_BASE(0x0068)
184 #define HDMI_CMIN HDMI_CORE_BASE(0x006C)
186 #define HDMI_V2_BLANK_0 HDMI_CORE_BASE(0x00B0)
187 #define HDMI_V2_BLANK_1 HDMI_CORE_BASE(0x00B4)
188 #define HDMI_V1_BLANK_0 HDMI_CORE_BASE(0x00B8)
189 #define HDMI_V1_BLANK_1 HDMI_CORE_BASE(0x00BC)
191 #define HDMI_V_LINE_0 HDMI_CORE_BASE(0x00C0)
192 #define HDMI_V_LINE_1 HDMI_CORE_BASE(0x00C4)
193 #define HDMI_H_LINE_0 HDMI_CORE_BASE(0x00C8)
194 #define HDMI_H_LINE_1 HDMI_CORE_BASE(0x00CC)
196 #define HDMI_HSYNC_POL HDMI_CORE_BASE(0x00E0)
198 #define HDMI_V_BLANK_F0_0 HDMI_CORE_BASE(0x0110)
199 #define HDMI_V_BLANK_F0_1 HDMI_CORE_BASE(0x0114)
200 #define HDMI_V_BLANK_F1_0 HDMI_CORE_BASE(0x0118)
201 #define HDMI_V_BLANK_F1_1 HDMI_CORE_BASE(0x011C)
203 #define HDMI_H_SYNC_START_0 HDMI_CORE_BASE(0x0120)
204 #define HDMI_H_SYNC_START_1 HDMI_CORE_BASE(0x0124)
205 #define HDMI_H_SYNC_END_0 HDMI_CORE_BASE(0x0128)
206 #define HDMI_H_SYNC_END_1 HDMI_CORE_BASE(0x012C)
208 #define HDMI_V_SYNC_LINE_BEF_2_0 HDMI_CORE_BASE(0x0130)
209 #define HDMI_V_SYNC_LINE_BEF_2_1 HDMI_CORE_BASE(0x0134)
210 #define HDMI_V_SYNC_LINE_BEF_1_0 HDMI_CORE_BASE(0x0138)
211 #define HDMI_V_SYNC_LINE_BEF_1_1 HDMI_CORE_BASE(0x013C)
213 #define HDMI_V_SYNC_LINE_AFT_2_0 HDMI_CORE_BASE(0x0140)
214 #define HDMI_V_SYNC_LINE_AFT_2_1 HDMI_CORE_BASE(0x0144)
215 #define HDMI_V_SYNC_LINE_AFT_1_0 HDMI_CORE_BASE(0x0148)
216 #define HDMI_V_SYNC_LINE_AFT_1_1 HDMI_CORE_BASE(0x014C)
218 #define HDMI_V_SYNC_LINE_AFT_PXL_2_0 HDMI_CORE_BASE(0x0150)
219 #define HDMI_V_SYNC_LINE_AFT_PXL_2_1 HDMI_CORE_BASE(0x0154)
220 #define HDMI_V_SYNC_LINE_AFT_PXL_1_0 HDMI_CORE_BASE(0x0158)
221 #define HDMI_V_SYNC_LINE_AFT_PXL_1_1 HDMI_CORE_BASE(0x015C)
223 #define HDMI_V_BLANK_F2_0 HDMI_CORE_BASE(0x0160)
224 #define HDMI_V_BLANK_F2_1 HDMI_CORE_BASE(0x0164)
225 #define HDMI_V_BLANK_F3_0 HDMI_CORE_BASE(0x0168)
226 #define HDMI_V_BLANK_F3_1 HDMI_CORE_BASE(0x016C)
227 #define HDMI_V_BLANK_F4_0 HDMI_CORE_BASE(0x0170)
228 #define HDMI_V_BLANK_F4_1 HDMI_CORE_BASE(0x0174)
229 #define HDMI_V_BLANK_F5_0 HDMI_CORE_BASE(0x0178)
230 #define HDMI_V_BLANK_F5_1 HDMI_CORE_BASE(0x017C)
232 #define HDMI_V_SYNC_LINE_AFT_3_0 HDMI_CORE_BASE(0x0180)
233 #define HDMI_V_SYNC_LINE_AFT_3_1 HDMI_CORE_BASE(0x0184)
234 #define HDMI_V_SYNC_LINE_AFT_4_0 HDMI_CORE_BASE(0x0188)
235 #define HDMI_V_SYNC_LINE_AFT_4_1 HDMI_CORE_BASE(0x018C)
236 #define HDMI_V_SYNC_LINE_AFT_5_0 HDMI_CORE_BASE(0x0190)
237 #define HDMI_V_SYNC_LINE_AFT_5_1 HDMI_CORE_BASE(0x0194)
238 #define HDMI_V_SYNC_LINE_AFT_6_0 HDMI_CORE_BASE(0x0198)
239 #define HDMI_V_SYNC_LINE_AFT_6_1 HDMI_CORE_BASE(0x019C)
241 #define HDMI_V_SYNC_LINE_AFT_PXL_3_0 HDMI_CORE_BASE(0x01A0)
242 #define HDMI_V_SYNC_LINE_AFT_PXL_3_1 HDMI_CORE_BASE(0x01A4)
243 #define HDMI_V_SYNC_LINE_AFT_PXL_4_0 HDMI_CORE_BASE(0x01A8)
244 #define HDMI_V_SYNC_LINE_AFT_PXL_4_1 HDMI_CORE_BASE(0x01AC)
245 #define HDMI_V_SYNC_LINE_AFT_PXL_5_0 HDMI_CORE_BASE(0x01B0)
246 #define HDMI_V_SYNC_LINE_AFT_PXL_5_1 HDMI_CORE_BASE(0x01B4)
247 #define HDMI_V_SYNC_LINE_AFT_PXL_6_0 HDMI_CORE_BASE(0x01B8)
248 #define HDMI_V_SYNC_LINE_AFT_PXL_6_1 HDMI_CORE_BASE(0x01BC)
250 #define HDMI_VACT_SPACE_1_0 HDMI_CORE_BASE(0x01C0)
251 #define HDMI_VACT_SPACE_1_1 HDMI_CORE_BASE(0x01C4)
252 #define HDMI_VACT_SPACE_2_0 HDMI_CORE_BASE(0x01C8)
253 #define HDMI_VACT_SPACE_2_1 HDMI_CORE_BASE(0x01CC)
254 #define HDMI_VACT_SPACE_3_0 HDMI_CORE_BASE(0x01D0)
255 #define HDMI_VACT_SPACE_3_1 HDMI_CORE_BASE(0x01D4)
256 #define HDMI_VACT_SPACE_4_0 HDMI_CORE_BASE(0x01D8)
257 #define HDMI_VACT_SPACE_4_1 HDMI_CORE_BASE(0x01DC)
258 #define HDMI_VACT_SPACE_5_0 HDMI_CORE_BASE(0x01E0)
259 #define HDMI_VACT_SPACE_5_1 HDMI_CORE_BASE(0x01E4)
260 #define HDMI_VACT_SPACE_6_0 HDMI_CORE_BASE(0x01E8)
261 #define HDMI_VACT_SPACE_6_1 HDMI_CORE_BASE(0x01EC)
263 #define HDMI_GCP_CON HDMI_CORE_BASE(0x0200)
264 #define HDMI_GCP_BYTE1 HDMI_CORE_BASE(0x0210)
265 #define HDMI_GCP_BYTE2 HDMI_CORE_BASE(0x0214)
266 #define HDMI_GCP_BYTE3 HDMI_CORE_BASE(0x0218)
268 /* Audio related registers */
269 #define HDMI_ASP_CON HDMI_CORE_BASE(0x0300)
270 #define HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304)
271 #define HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310)
272 #define HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314)
273 #define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318)
274 #define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C)
276 #define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180)
277 #define HDMI_V13_ACR_MCTS0 HDMI_CORE_BASE(0x0184)
278 #define HDMI_V13_ACR_MCTS1 HDMI_CORE_BASE(0x0188)
279 #define HDMI_V13_ACR_MCTS2 HDMI_CORE_BASE(0x018C)
280 #define HDMI_V13_ACR_CTS0 HDMI_CORE_BASE(0x0190)
281 #define HDMI_V13_ACR_CTS1 HDMI_CORE_BASE(0x0194)
282 #define HDMI_V13_ACR_CTS2 HDMI_CORE_BASE(0x0198)
283 #define HDMI_V13_ACR_N0 HDMI_CORE_BASE(0x01A0)
284 #define HDMI_V13_ACR_N1 HDMI_CORE_BASE(0x01A4)
285 #define HDMI_V13_ACR_N2 HDMI_CORE_BASE(0x01A8)
286 #define HDMI_V14_ACR_CON HDMI_CORE_BASE(0x0400)
287 #define HDMI_V14_ACR_MCTS0 HDMI_CORE_BASE(0x0410)
288 #define HDMI_V14_ACR_MCTS1 HDMI_CORE_BASE(0x0414)
289 #define HDMI_V14_ACR_MCTS2 HDMI_CORE_BASE(0x0418)
290 #define HDMI_V14_ACR_CTS0 HDMI_CORE_BASE(0x0420)
291 #define HDMI_V14_ACR_CTS1 HDMI_CORE_BASE(0x0424)
292 #define HDMI_V14_ACR_CTS2 HDMI_CORE_BASE(0x0428)
293 #define HDMI_V14_ACR_N0 HDMI_CORE_BASE(0x0430)
294 #define HDMI_V14_ACR_N1 HDMI_CORE_BASE(0x0434)
295 #define HDMI_V14_ACR_N2 HDMI_CORE_BASE(0x0438)
297 /* Packet related registers */
298 #define HDMI_ACP_CON HDMI_CORE_BASE(0x0500)
299 #define HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514)
300 #define HDMI_ACP_DATA(n) HDMI_CORE_BASE(0x0520 + 4 * (n))
302 #define HDMI_ISRC_CON HDMI_CORE_BASE(0x0600)
303 #define HDMI_ISRC1_HEADER1 HDMI_CORE_BASE(0x0614)
304 #define HDMI_ISRC1_DATA(n) HDMI_CORE_BASE(0x0620 + 4 * (n))
305 #define HDMI_ISRC2_DATA(n) HDMI_CORE_BASE(0x06A0 + 4 * (n))
307 #define HDMI_AVI_CON HDMI_CORE_BASE(0x0700)
308 #define HDMI_AVI_HEADER0 HDMI_CORE_BASE(0x0710)
309 #define HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714)
310 #define HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718)
311 #define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C)
312 #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n-1))
314 #define HDMI_AUI_CON HDMI_CORE_BASE(0x0800)
315 #define HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810)
316 #define HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814)
317 #define HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818)
318 #define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C)
319 #define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n-1))
321 #define HDMI_MPG_CON HDMI_CORE_BASE(0x0900)
322 #define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C)
323 #define HDMI_MPG_DATA(n) HDMI_CORE_BASE(0x0920 + 4 * (n))
325 #define HDMI_SPD_CON HDMI_CORE_BASE(0x0A00)
326 #define HDMI_SPD_HEADER0 HDMI_CORE_BASE(0x0A10)
327 #define HDMI_SPD_HEADER1 HDMI_CORE_BASE(0x0A14)
328 #define HDMI_SPD_HEADER2 HDMI_CORE_BASE(0x0A18)
329 #define HDMI_SPD_DATA(n) HDMI_CORE_BASE(0x0A20 + 4 * (n))
331 #define HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00)
332 #define HDMI_GAMUT_HEADER0 HDMI_CORE_BASE(0x0B10)
333 #define HDMI_GAMUT_HEADER1 HDMI_CORE_BASE(0x0B14)
334 #define HDMI_GAMUT_HEADER2 HDMI_CORE_BASE(0x0B18)
335 #define HDMI_GAMUT_METADATA(n) HDMI_CORE_BASE(0x0B20 + 4 * (n))
337 #define HDMI_VSI_CON HDMI_CORE_BASE(0x0C00)
338 #define HDMI_VSI_HEADER0 HDMI_CORE_BASE(0x0C10)
339 #define HDMI_VSI_HEADER1 HDMI_CORE_BASE(0x0C14)
340 #define HDMI_VSI_HEADER2 HDMI_CORE_BASE(0x0C18)
341 #define HDMI_VSI_DATA(n) HDMI_CORE_BASE(0x0C20 + 4 * (n))
343 #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00)
344 #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04)
346 #define HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48)
347 #define HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58)
348 #define HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C)
349 #define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60)
350 #define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64)
352 /* AVI bit definition */
353 #define HDMI_AVI_CON_DO_NOT_TRANSMIT (0 << 1)
354 #define HDMI_AVI_CON_EVERY_VSYNC (1 << 1)
356 #define AVI_ACTIVE_FORMAT_VALID (1 << 4)
357 #define AVI_UNDERSCANNED_DISPLAY_VALID (1 << 1)
359 /* AUI bit definition */
360 #define HDMI_AUI_CON_NO_TRAN (0 << 0)
361 #define HDMI_AUI_CON_EVERY_VSYNC (1 << 1)
363 /* VSI bit definition */
364 #define HDMI_VSI_CON_DO_NOT_TRANSMIT (0 << 0)
365 #define HDMI_VSI_CON_EVERY_VSYNC (1 << 1)
367 /* HDCP related registers */
368 #define HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n))
369 #define HDMI_HDCP_KSV_LIST(n) HDMI_CORE_BASE(0x7050 + 4 * (n))
371 #define HDMI_HDCP_KSV_LIST_CON HDMI_CORE_BASE(0x7064)
372 #define HDMI_HDCP_SHA_RESULT HDMI_CORE_BASE(0x7070)
373 #define HDMI_HDCP_CTRL1 HDMI_CORE_BASE(0x7080)
374 #define HDMI_HDCP_CTRL2 HDMI_CORE_BASE(0x7084)
375 #define HDMI_HDCP_CHECK_RESULT HDMI_CORE_BASE(0x7090)
376 #define HDMI_HDCP_BKSV(n) HDMI_CORE_BASE(0x70A0 + 4 * (n))
377 #define HDMI_HDCP_AKSV(n) HDMI_CORE_BASE(0x70C0 + 4 * (n))
378 #define HDMI_HDCP_AN(n) HDMI_CORE_BASE(0x70E0 + 4 * (n))
380 #define HDMI_HDCP_BCAPS HDMI_CORE_BASE(0x7100)
381 #define HDMI_HDCP_BSTATUS_0 HDMI_CORE_BASE(0x7110)
382 #define HDMI_HDCP_BSTATUS_1 HDMI_CORE_BASE(0x7114)
383 #define HDMI_HDCP_RI_0 HDMI_CORE_BASE(0x7140)
384 #define HDMI_HDCP_RI_1 HDMI_CORE_BASE(0x7144)
385 #define HDMI_HDCP_I2C_INT HDMI_CORE_BASE(0x7180)
386 #define HDMI_HDCP_AN_INT HDMI_CORE_BASE(0x7190)
387 #define HDMI_HDCP_WDT_INT HDMI_CORE_BASE(0x71A0)
388 #define HDMI_HDCP_RI_INT HDMI_CORE_BASE(0x71B0)
389 #define HDMI_HDCP_RI_COMPARE_0 HDMI_CORE_BASE(0x71D0)
390 #define HDMI_HDCP_RI_COMPARE_1 HDMI_CORE_BASE(0x71D4)
391 #define HDMI_HDCP_FRAME_COUNT HDMI_CORE_BASE(0x71E0)
393 #define HDMI_RGB_ROUND_EN HDMI_CORE_BASE(0xD500)
394 #define HDMI_VACT_SPACE_R_0 HDMI_CORE_BASE(0xD504)
395 #define HDMI_VACT_SPACE_R_1 HDMI_CORE_BASE(0xD508)
396 #define HDMI_VACT_SPACE_G_0 HDMI_CORE_BASE(0xD50C)
397 #define HDMI_VACT_SPACE_G_1 HDMI_CORE_BASE(0xD510)
398 #define HDMI_VACT_SPACE_B_0 HDMI_CORE_BASE(0xD514)
399 #define HDMI_VACT_SPACE_B_1 HDMI_CORE_BASE(0xD518)
401 #define HDMI_BLUE_SCREEN_B_0 HDMI_CORE_BASE(0xD520)
402 #define HDMI_BLUE_SCREEN_B_1 HDMI_CORE_BASE(0xD524)
403 #define HDMI_BLUE_SCREEN_G_0 HDMI_CORE_BASE(0xD528)
404 #define HDMI_BLUE_SCREEN_G_1 HDMI_CORE_BASE(0xD52C)
405 #define HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530)
406 #define HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534)
408 /* HDMI I2S register */
409 #define HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000)
410 #define HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004)
411 #define HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008)
412 #define HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c)
413 #define HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010)
414 #define HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014)
415 #define HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018)
416 #define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c)
417 #define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020)
418 #define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024)
419 /* n must be within range 0...(HDMI_I2S_CH_ST_MAXNUM - 1) */
420 #define HDMI_I2S_CH_ST_MAXNUM 5
421 #define HDMI_I2S_CH_ST(n) HDMI_I2S_BASE(0x028 + 4 * (n))
422 #define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c)
423 #define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040)
424 #define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044)
425 #define HDMI_I2S_CH_ST_SH_3 HDMI_I2S_BASE(0x048)
426 #define HDMI_I2S_CH_ST_SH_4 HDMI_I2S_BASE(0x04c)
427 #define HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054)
428 #define HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058)
430 /* I2S bit definition */
432 /* I2S_CLK_CON */
433 #define HDMI_I2S_CLK_DIS (0)
434 #define HDMI_I2S_CLK_EN (1)
436 /* I2S_CON_1 */
437 #define HDMI_I2S_SCLK_FALLING_EDGE (0 << 1)
438 #define HDMI_I2S_SCLK_RISING_EDGE (1 << 1)
439 #define HDMI_I2S_L_CH_LOW_POL (0)
440 #define HDMI_I2S_L_CH_HIGH_POL (1)
442 /* I2S_CON_2 */
443 #define HDMI_I2S_MSB_FIRST_MODE (0 << 6)
444 #define HDMI_I2S_LSB_FIRST_MODE (1 << 6)
445 #define HDMI_I2S_BIT_CH_32FS (0 << 4)
446 #define HDMI_I2S_BIT_CH_48FS (1 << 4)
447 #define HDMI_I2S_BIT_CH_RESERVED (2 << 4)
448 #define HDMI_I2S_SDATA_16BIT (1 << 2)
449 #define HDMI_I2S_SDATA_20BIT (2 << 2)
450 #define HDMI_I2S_SDATA_24BIT (3 << 2)
451 #define HDMI_I2S_BASIC_FORMAT (0)
452 #define HDMI_I2S_L_JUST_FORMAT (2)
453 #define HDMI_I2S_R_JUST_FORMAT (3)
454 #define HDMI_I2S_CON_2_CLR (~(0xFF))
455 #define HDMI_I2S_SET_BIT_CH(x) (((x) & 0x7) << 4)
456 #define HDMI_I2S_SET_SDATA_BIT(x) (((x) & 0x7) << 2)
458 /* I2S_PIN_SEL_0 */
459 #define HDMI_I2S_SEL_SCLK(x) (((x) & 0x7) << 4)
460 #define HDMI_I2S_SEL_LRCK(x) ((x) & 0x7)
462 /* I2S_PIN_SEL_1 */
463 #define HDMI_I2S_SEL_SDATA1(x) (((x) & 0x7) << 4)
464 #define HDMI_I2S_SEL_SDATA0(x) ((x) & 0x7)
466 /* I2S_PIN_SEL_2 */
467 #define HDMI_I2S_SEL_SDATA3(x) (((x) & 0x7) << 4)
468 #define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7)
470 /* I2S_PIN_SEL_3 */
471 #define HDMI_I2S_SEL_DSD(x) ((x) & 0x7)
473 /* I2S_DSD_CON */
474 #define HDMI_I2S_DSD_CLK_RI_EDGE (1 << 1)
475 #define HDMI_I2S_DSD_CLK_FA_EDGE (0 << 1)
476 #define HDMI_I2S_DSD_ENABLE (1)
477 #define HDMI_I2S_DSD_DISABLE (0)
479 /* I2S_MUX_CON */
480 #define HDMI_I2S_NOISE_FILTER_ZERO (0 << 5)
481 #define HDMI_I2S_NOISE_FILTER_2_STAGE (1 << 5)
482 #define HDMI_I2S_NOISE_FILTER_3_STAGE (2 << 5)
483 #define HDMI_I2S_NOISE_FILTER_4_STAGE (3 << 5)
484 #define HDMI_I2S_NOISE_FILTER_5_STAGE (4 << 5)
485 #define HDMI_I2S_IN_DISABLE (1 << 4)
486 #define HDMI_I2S_IN_ENABLE (0 << 4)
487 #define HDMI_I2S_AUD_SPDIF (0 << 2)
488 #define HDMI_I2S_AUD_I2S (1 << 2)
489 #define HDMI_I2S_AUD_DSD (2 << 2)
490 #define HDMI_I2S_CUV_SPDIF_ENABLE (0 << 1)
491 #define HDMI_I2S_CUV_I2S_ENABLE (1 << 1)
492 #define HDMI_I2S_MUX_DISABLE (0)
493 #define HDMI_I2S_MUX_ENABLE (1)
494 #define HDMI_I2S_MUX_CON_CLR (~(0xFF))
496 /* I2S_CH_ST_CON */
497 #define HDMI_I2S_CH_STATUS_RELOAD (1)
498 #define HDMI_I2S_CH_ST_CON_CLR (~(1))
500 /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
501 #define HDMI_I2S_CH_STATUS_MODE_0 (0 << 6)
502 #define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3)
503 #define HDMI_I2S_2AUD_CH_WITH_PREEMPH (1 << 3)
504 #define HDMI_I2S_DEFAULT_EMPHASIS (0 << 3)
505 #define HDMI_I2S_COPYRIGHT (0 << 2)
506 #define HDMI_I2S_NO_COPYRIGHT (1 << 2)
507 #define HDMI_I2S_LINEAR_PCM (0 << 1)
508 #define HDMI_I2S_NO_LINEAR_PCM (1 << 1)
509 #define HDMI_I2S_CONSUMER_FORMAT (0)
510 #define HDMI_I2S_PROF_FORMAT (1)
511 #define HDMI_I2S_CH_ST_0_CLR (~(0xFF))
513 /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
514 #define HDMI_I2S_CD_PLAYER (0x00)
515 #define HDMI_I2S_DAT_PLAYER (0x03)
516 #define HDMI_I2S_DCC_PLAYER (0x43)
517 #define HDMI_I2S_MINI_DISC_PLAYER (0x49)
519 /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
520 #define HDMI_I2S_CHANNEL_NUM_MASK (0xF << 4)
521 #define HDMI_I2S_SOURCE_NUM_MASK (0xF)
522 #define HDMI_I2S_SET_CHANNEL_NUM(x) (((x) & (0xF)) << 4)
523 #define HDMI_I2S_SET_SOURCE_NUM(x) ((x) & (0xF))
525 /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
526 #define HDMI_I2S_CLK_ACCUR_LEVEL_1 (1 << 4)
527 #define HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4)
528 #define HDMI_I2S_CLK_ACCUR_LEVEL_3 (2 << 4)
529 #define HDMI_I2S_SMP_FREQ_44_1 (0x0)
530 #define HDMI_I2S_SMP_FREQ_48 (0x2)
531 #define HDMI_I2S_SMP_FREQ_32 (0x3)
532 #define HDMI_I2S_SMP_FREQ_96 (0xA)
533 #define HDMI_I2S_SET_SMP_FREQ(x) ((x) & (0xF))
535 /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
536 #define HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4)
537 #define HDMI_I2S_ORG_SMP_FREQ_88_2 (0x7 << 4)
538 #define HDMI_I2S_ORG_SMP_FREQ_22_05 (0xB << 4)
539 #define HDMI_I2S_ORG_SMP_FREQ_176_4 (0x3 << 4)
540 #define HDMI_I2S_WORD_LEN_NOT_DEFINE (0x0 << 1)
541 #define HDMI_I2S_WORD_LEN_MAX24_20BITS (0x1 << 1)
542 #define HDMI_I2S_WORD_LEN_MAX24_22BITS (0x2 << 1)
543 #define HDMI_I2S_WORD_LEN_MAX24_23BITS (0x4 << 1)
544 #define HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1)
545 #define HDMI_I2S_WORD_LEN_MAX24_21BITS (0x6 << 1)
546 #define HDMI_I2S_WORD_LEN_MAX20_16BITS (0x1 << 1)
547 #define HDMI_I2S_WORD_LEN_MAX20_18BITS (0x2 << 1)
548 #define HDMI_I2S_WORD_LEN_MAX20_19BITS (0x4 << 1)
549 #define HDMI_I2S_WORD_LEN_MAX20_20BITS (0x5 << 1)
550 #define HDMI_I2S_WORD_LEN_MAX20_17BITS (0x6 << 1)
551 #define HDMI_I2S_WORD_LEN_MAX_24BITS (1)
552 #define HDMI_I2S_WORD_LEN_MAX_20BITS (0)
554 /* I2S_MUX_CH */
555 #define HDMI_I2S_CH3_R_EN (1 << 7)
556 #define HDMI_I2S_CH3_L_EN (1 << 6)
557 #define HDMI_I2S_CH3_EN (3 << 6)
558 #define HDMI_I2S_CH2_R_EN (1 << 5)
559 #define HDMI_I2S_CH2_L_EN (1 << 4)
560 #define HDMI_I2S_CH2_EN (3 << 4)
561 #define HDMI_I2S_CH1_R_EN (1 << 3)
562 #define HDMI_I2S_CH1_L_EN (1 << 2)
563 #define HDMI_I2S_CH1_EN (3 << 2)
564 #define HDMI_I2S_CH0_R_EN (1 << 1)
565 #define HDMI_I2S_CH0_L_EN (1)
566 #define HDMI_I2S_CH0_EN (3)
567 #define HDMI_I2S_CH_ALL_EN (0xFF)
568 #define HDMI_I2S_MUX_CH_CLR (~HDMI_I2S_CH_ALL_EN)
570 /* I2S_MUX_CUV */
571 #define HDMI_I2S_CUV_R_EN (1 << 1)
572 #define HDMI_I2S_CUV_L_EN (1)
573 #define HDMI_I2S_CUV_RL_EN (0x03)
575 /* I2S_CUV_L_R */
576 #define HDMI_I2S_CUV_R_DATA_MASK (0x7 << 4)
577 #define HDMI_I2S_CUV_L_DATA_MASK (0x7)
579 /* Timing generator registers */
580 /* TG configure/status registers */
581 #define HDMI_TG_VACT_ST3_L HDMI_TG_BASE(0x0068)
582 #define HDMI_TG_VACT_ST3_H HDMI_TG_BASE(0x006c)
583 #define HDMI_TG_VACT_ST4_L HDMI_TG_BASE(0x0070)
584 #define HDMI_TG_VACT_ST4_H HDMI_TG_BASE(0x0074)
585 #define HDMI_TG_3D HDMI_TG_BASE(0x00F0)
586 #define HDMI_TG_DECON_EN HDMI_TG_BASE(0x01e0)
588 /* HDMI PHY Registers Offsets*/
589 #define HDMIPHY_POWER 0x74
590 #define HDMIPHY_MODE_SET_DONE 0x7c
591 #define HDMIPHY5433_MODE_SET_DONE 0x84
593 /* HDMI PHY Values */
594 #define HDMI_PHY_POWER_ON 0x80
595 #define HDMI_PHY_POWER_OFF 0xff
597 /* HDMI PHY Values */
598 #define HDMI_PHY_DISABLE_MODE_SET 0x80
599 #define HDMI_PHY_ENABLE_MODE_SET 0x00
601 /* PMU Registers for PHY */
602 #define PMU_HDMI_PHY_CONTROL 0x700
603 #define PMU_HDMI_PHY_ENABLE_BIT BIT(0)
605 #define EXYNOS5433_SYSREG_DISP_HDMI_PHY 0x1008
606 #define SYSREG_HDMI_REFCLK_INT_CLK 1