1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
6 * Eric Anholt <eric@anholt.net>
7 * Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
10 #include <linux/delay.h>
11 #include <linux/highmem.h>
13 #include <drm/drm_crtc.h>
14 #include <drm/drm_fourcc.h>
15 #include <drm/drm_vblank.h>
17 #include "framebuffer.h"
18 #include "gma_display.h"
20 #include "psb_intel_drv.h"
21 #include "psb_intel_reg.h"
24 * Returns whether any output on the specified pipe is of the specified type
26 bool gma_pipe_has_type(struct drm_crtc
*crtc
, int type
)
28 struct drm_device
*dev
= crtc
->dev
;
29 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
30 struct drm_connector
*l_entry
;
32 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
33 if (l_entry
->encoder
&& l_entry
->encoder
->crtc
== crtc
) {
34 struct gma_encoder
*gma_encoder
=
35 gma_attached_encoder(l_entry
);
36 if (gma_encoder
->type
== type
)
44 void gma_wait_for_vblank(struct drm_device
*dev
)
46 /* Wait for 20ms, i.e. one cycle at 50hz. */
50 int gma_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
51 struct drm_framebuffer
*old_fb
)
53 struct drm_device
*dev
= crtc
->dev
;
54 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
55 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
56 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
57 struct gtt_range
*gtt
;
58 int pipe
= gma_crtc
->pipe
;
59 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
60 unsigned long start
, offset
;
64 if (!gma_power_begin(dev
, true))
69 dev_err(dev
->dev
, "No FB bound\n");
70 goto gma_pipe_cleaner
;
73 gtt
= to_gtt_range(fb
->obj
[0]);
75 /* We are displaying this buffer, make sure it is actually loaded
77 ret
= psb_gtt_pin(gtt
);
79 goto gma_pipe_set_base_exit
;
81 offset
= y
* fb
->pitches
[0] + x
* fb
->format
->cpp
[0];
83 REG_WRITE(map
->stride
, fb
->pitches
[0]);
85 dspcntr
= REG_READ(map
->cntr
);
86 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
88 switch (fb
->format
->cpp
[0] * 8) {
90 dspcntr
|= DISPPLANE_8BPP
;
93 if (fb
->format
->depth
== 15)
94 dspcntr
|= DISPPLANE_15_16BPP
;
96 dspcntr
|= DISPPLANE_16BPP
;
100 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
103 dev_err(dev
->dev
, "Unknown color depth\n");
105 goto gma_pipe_set_base_exit
;
107 REG_WRITE(map
->cntr
, dspcntr
);
110 "Writing base %08lX %08lX %d %d\n", start
, offset
, x
, y
);
112 /* FIXME: Investigate whether this really is the base for psb and why
113 the linear offset is named base for the other chips. map->surf
114 should be the base and map->linoff the offset for all chips */
116 REG_WRITE(map
->base
, offset
+ start
);
119 REG_WRITE(map
->base
, offset
);
121 REG_WRITE(map
->surf
, start
);
126 /* If there was a previous display we can now unpin it */
128 psb_gtt_unpin(to_gtt_range(old_fb
->obj
[0]));
130 gma_pipe_set_base_exit
:
135 /* Loads the palette/gamma unit for the CRTC with the prepared values */
136 void gma_crtc_load_lut(struct drm_crtc
*crtc
)
138 struct drm_device
*dev
= crtc
->dev
;
139 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
140 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
141 const struct psb_offset
*map
= &dev_priv
->regmap
[gma_crtc
->pipe
];
142 int palreg
= map
->palette
;
146 /* The clocks have to be on to load the palette. */
150 r
= crtc
->gamma_store
;
151 g
= r
+ crtc
->gamma_size
;
152 b
= g
+ crtc
->gamma_size
;
154 if (gma_power_begin(dev
, false)) {
155 for (i
= 0; i
< 256; i
++) {
156 REG_WRITE(palreg
+ 4 * i
,
157 (((*r
++ >> 8) + gma_crtc
->lut_adj
[i
]) << 16) |
158 (((*g
++ >> 8) + gma_crtc
->lut_adj
[i
]) << 8) |
159 ((*b
++ >> 8) + gma_crtc
->lut_adj
[i
]));
163 for (i
= 0; i
< 256; i
++) {
164 /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */
165 dev_priv
->regs
.pipe
[0].palette
[i
] =
166 (((*r
++ >> 8) + gma_crtc
->lut_adj
[i
]) << 16) |
167 (((*g
++ >> 8) + gma_crtc
->lut_adj
[i
]) << 8) |
168 ((*b
++ >> 8) + gma_crtc
->lut_adj
[i
]);
174 int gma_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
, u16
*blue
,
176 struct drm_modeset_acquire_ctx
*ctx
)
178 gma_crtc_load_lut(crtc
);
184 * Sets the power management mode of the pipe and plane.
186 * This code should probably grow support for turning the cursor off and back
187 * on appropriately at the same time as we're turning the pipe off/on.
189 void gma_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
191 struct drm_device
*dev
= crtc
->dev
;
192 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
193 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
194 int pipe
= gma_crtc
->pipe
;
195 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
198 /* XXX: When our outputs are all unaware of DPMS modes other than off
199 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
203 dev_priv
->ops
->disable_sr(dev
);
206 case DRM_MODE_DPMS_ON
:
207 case DRM_MODE_DPMS_STANDBY
:
208 case DRM_MODE_DPMS_SUSPEND
:
209 if (gma_crtc
->active
)
212 gma_crtc
->active
= true;
214 /* Enable the DPLL */
215 temp
= REG_READ(map
->dpll
);
216 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
217 REG_WRITE(map
->dpll
, temp
);
219 /* Wait for the clocks to stabilize. */
221 REG_WRITE(map
->dpll
, temp
| DPLL_VCO_ENABLE
);
223 /* Wait for the clocks to stabilize. */
225 REG_WRITE(map
->dpll
, temp
| DPLL_VCO_ENABLE
);
227 /* Wait for the clocks to stabilize. */
231 /* Enable the plane */
232 temp
= REG_READ(map
->cntr
);
233 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
235 temp
| DISPLAY_PLANE_ENABLE
);
236 /* Flush the plane changes */
237 REG_WRITE(map
->base
, REG_READ(map
->base
));
242 /* Enable the pipe */
243 temp
= REG_READ(map
->conf
);
244 if ((temp
& PIPEACONF_ENABLE
) == 0)
245 REG_WRITE(map
->conf
, temp
| PIPEACONF_ENABLE
);
247 temp
= REG_READ(map
->status
);
249 temp
|= PIPE_FIFO_UNDERRUN
;
250 REG_WRITE(map
->status
, temp
);
251 REG_READ(map
->status
);
253 gma_crtc_load_lut(crtc
);
255 /* Give the overlay scaler a chance to enable
256 * if it's on this pipe */
257 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
259 drm_crtc_vblank_on(crtc
);
261 case DRM_MODE_DPMS_OFF
:
262 if (!gma_crtc
->active
)
265 gma_crtc
->active
= false;
267 /* Give the overlay scaler a chance to disable
268 * if it's on this pipe */
269 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
271 /* Disable the VGA plane that we never use */
272 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
274 /* Turn off vblank interrupts */
275 drm_crtc_vblank_off(crtc
);
277 /* Wait for vblank for the disable to take effect */
278 gma_wait_for_vblank(dev
);
281 temp
= REG_READ(map
->cntr
);
282 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
284 temp
& ~DISPLAY_PLANE_ENABLE
);
285 /* Flush the plane changes */
286 REG_WRITE(map
->base
, REG_READ(map
->base
));
291 temp
= REG_READ(map
->conf
);
292 if ((temp
& PIPEACONF_ENABLE
) != 0) {
293 REG_WRITE(map
->conf
, temp
& ~PIPEACONF_ENABLE
);
297 /* Wait for vblank for the disable to take effect. */
298 gma_wait_for_vblank(dev
);
303 temp
= REG_READ(map
->dpll
);
304 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
305 REG_WRITE(map
->dpll
, temp
& ~DPLL_VCO_ENABLE
);
309 /* Wait for the clocks to turn off. */
315 dev_priv
->ops
->update_wm(dev
, crtc
);
317 /* Set FIFO watermarks */
318 REG_WRITE(DSPARB
, 0x3F3E);
321 int gma_crtc_cursor_set(struct drm_crtc
*crtc
,
322 struct drm_file
*file_priv
,
324 uint32_t width
, uint32_t height
)
326 struct drm_device
*dev
= crtc
->dev
;
327 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
328 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
329 int pipe
= gma_crtc
->pipe
;
330 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
331 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
334 struct gtt_range
*gt
;
335 struct gtt_range
*cursor_gt
= gma_crtc
->cursor_gt
;
336 struct drm_gem_object
*obj
;
337 void *tmp_dst
, *tmp_src
;
338 int ret
= 0, i
, cursor_pages
;
340 /* If we didn't get a handle then turn the cursor off */
342 temp
= CURSOR_MODE_DISABLE
;
343 if (gma_power_begin(dev
, false)) {
344 REG_WRITE(control
, temp
);
349 /* Unpin the old GEM object */
350 if (gma_crtc
->cursor_obj
) {
351 gt
= container_of(gma_crtc
->cursor_obj
,
352 struct gtt_range
, gem
);
354 drm_gem_object_put(gma_crtc
->cursor_obj
);
355 gma_crtc
->cursor_obj
= NULL
;
360 /* Currently we only support 64x64 cursors */
361 if (width
!= 64 || height
!= 64) {
362 dev_dbg(dev
->dev
, "We currently only support 64x64 cursors\n");
366 obj
= drm_gem_object_lookup(file_priv
, handle
);
372 if (obj
->size
< width
* height
* 4) {
373 dev_dbg(dev
->dev
, "Buffer is too small\n");
378 gt
= container_of(obj
, struct gtt_range
, gem
);
380 /* Pin the memory into the GTT */
381 ret
= psb_gtt_pin(gt
);
383 dev_err(dev
->dev
, "Can not pin down handle 0x%x\n", handle
);
387 if (dev_priv
->ops
->cursor_needs_phys
) {
388 if (cursor_gt
== NULL
) {
389 dev_err(dev
->dev
, "No hardware cursor mem available");
394 /* Prevent overflow */
398 cursor_pages
= gt
->npage
;
400 /* Copy the cursor to cursor mem */
401 tmp_dst
= dev_priv
->vram_addr
+ cursor_gt
->offset
;
402 for (i
= 0; i
< cursor_pages
; i
++) {
403 tmp_src
= kmap(gt
->pages
[i
]);
404 memcpy(tmp_dst
, tmp_src
, PAGE_SIZE
);
405 kunmap(gt
->pages
[i
]);
406 tmp_dst
+= PAGE_SIZE
;
409 addr
= gma_crtc
->cursor_addr
;
412 gma_crtc
->cursor_addr
= addr
;
416 /* set the pipe for the cursor */
417 temp
|= (pipe
<< 28);
418 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
420 if (gma_power_begin(dev
, false)) {
421 REG_WRITE(control
, temp
);
422 REG_WRITE(base
, addr
);
426 /* unpin the old bo */
427 if (gma_crtc
->cursor_obj
) {
428 gt
= container_of(gma_crtc
->cursor_obj
, struct gtt_range
, gem
);
430 drm_gem_object_put(gma_crtc
->cursor_obj
);
433 gma_crtc
->cursor_obj
= obj
;
438 drm_gem_object_put(obj
);
442 int gma_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
444 struct drm_device
*dev
= crtc
->dev
;
445 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
446 int pipe
= gma_crtc
->pipe
;
451 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
455 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
459 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
460 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
462 addr
= gma_crtc
->cursor_addr
;
464 if (gma_power_begin(dev
, false)) {
465 REG_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
466 REG_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, addr
);
472 void gma_crtc_prepare(struct drm_crtc
*crtc
)
474 const struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
475 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
478 void gma_crtc_commit(struct drm_crtc
*crtc
)
480 const struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
481 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
484 void gma_crtc_disable(struct drm_crtc
*crtc
)
486 struct gtt_range
*gt
;
487 const struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
489 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
491 if (crtc
->primary
->fb
) {
492 gt
= to_gtt_range(crtc
->primary
->fb
->obj
[0]);
497 void gma_crtc_destroy(struct drm_crtc
*crtc
)
499 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
501 kfree(gma_crtc
->crtc_state
);
502 drm_crtc_cleanup(crtc
);
506 int gma_crtc_page_flip(struct drm_crtc
*crtc
,
507 struct drm_framebuffer
*fb
,
508 struct drm_pending_vblank_event
*event
,
509 uint32_t page_flip_flags
,
510 struct drm_modeset_acquire_ctx
*ctx
)
512 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
513 struct drm_framebuffer
*current_fb
= crtc
->primary
->fb
;
514 struct drm_framebuffer
*old_fb
= crtc
->primary
->old_fb
;
515 const struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
516 struct drm_device
*dev
= crtc
->dev
;
520 if (!crtc_funcs
->mode_set_base
)
523 /* Using mode_set_base requires the new fb to be set already. */
524 crtc
->primary
->fb
= fb
;
527 spin_lock_irqsave(&dev
->event_lock
, flags
);
529 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
531 gma_crtc
->page_flip_event
= event
;
533 /* Call this locked if we want an event at vblank interrupt. */
534 ret
= crtc_funcs
->mode_set_base(crtc
, crtc
->x
, crtc
->y
, old_fb
);
536 gma_crtc
->page_flip_event
= NULL
;
537 drm_crtc_vblank_put(crtc
);
540 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
542 ret
= crtc_funcs
->mode_set_base(crtc
, crtc
->x
, crtc
->y
, old_fb
);
545 /* Restore previous fb in case of failure. */
547 crtc
->primary
->fb
= current_fb
;
552 int gma_crtc_set_config(struct drm_mode_set
*set
,
553 struct drm_modeset_acquire_ctx
*ctx
)
555 struct drm_device
*dev
= set
->crtc
->dev
;
556 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
559 if (!dev_priv
->rpm_enabled
)
560 return drm_crtc_helper_set_config(set
, ctx
);
562 pm_runtime_forbid(&dev
->pdev
->dev
);
563 ret
= drm_crtc_helper_set_config(set
, ctx
);
564 pm_runtime_allow(&dev
->pdev
->dev
);
570 * Save HW states of given crtc
572 void gma_crtc_save(struct drm_crtc
*crtc
)
574 struct drm_device
*dev
= crtc
->dev
;
575 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
576 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
577 struct psb_intel_crtc_state
*crtc_state
= gma_crtc
->crtc_state
;
578 const struct psb_offset
*map
= &dev_priv
->regmap
[gma_crtc
->pipe
];
579 uint32_t palette_reg
;
583 dev_err(dev
->dev
, "No CRTC state found\n");
587 crtc_state
->saveDSPCNTR
= REG_READ(map
->cntr
);
588 crtc_state
->savePIPECONF
= REG_READ(map
->conf
);
589 crtc_state
->savePIPESRC
= REG_READ(map
->src
);
590 crtc_state
->saveFP0
= REG_READ(map
->fp0
);
591 crtc_state
->saveFP1
= REG_READ(map
->fp1
);
592 crtc_state
->saveDPLL
= REG_READ(map
->dpll
);
593 crtc_state
->saveHTOTAL
= REG_READ(map
->htotal
);
594 crtc_state
->saveHBLANK
= REG_READ(map
->hblank
);
595 crtc_state
->saveHSYNC
= REG_READ(map
->hsync
);
596 crtc_state
->saveVTOTAL
= REG_READ(map
->vtotal
);
597 crtc_state
->saveVBLANK
= REG_READ(map
->vblank
);
598 crtc_state
->saveVSYNC
= REG_READ(map
->vsync
);
599 crtc_state
->saveDSPSTRIDE
= REG_READ(map
->stride
);
601 /* NOTE: DSPSIZE DSPPOS only for psb */
602 crtc_state
->saveDSPSIZE
= REG_READ(map
->size
);
603 crtc_state
->saveDSPPOS
= REG_READ(map
->pos
);
605 crtc_state
->saveDSPBASE
= REG_READ(map
->base
);
607 palette_reg
= map
->palette
;
608 for (i
= 0; i
< 256; ++i
)
609 crtc_state
->savePalette
[i
] = REG_READ(palette_reg
+ (i
<< 2));
613 * Restore HW states of given crtc
615 void gma_crtc_restore(struct drm_crtc
*crtc
)
617 struct drm_device
*dev
= crtc
->dev
;
618 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
619 struct gma_crtc
*gma_crtc
= to_gma_crtc(crtc
);
620 struct psb_intel_crtc_state
*crtc_state
= gma_crtc
->crtc_state
;
621 const struct psb_offset
*map
= &dev_priv
->regmap
[gma_crtc
->pipe
];
622 uint32_t palette_reg
;
626 dev_err(dev
->dev
, "No crtc state\n");
630 if (crtc_state
->saveDPLL
& DPLL_VCO_ENABLE
) {
632 crtc_state
->saveDPLL
& ~DPLL_VCO_ENABLE
);
637 REG_WRITE(map
->fp0
, crtc_state
->saveFP0
);
640 REG_WRITE(map
->fp1
, crtc_state
->saveFP1
);
643 REG_WRITE(map
->dpll
, crtc_state
->saveDPLL
);
647 REG_WRITE(map
->htotal
, crtc_state
->saveHTOTAL
);
648 REG_WRITE(map
->hblank
, crtc_state
->saveHBLANK
);
649 REG_WRITE(map
->hsync
, crtc_state
->saveHSYNC
);
650 REG_WRITE(map
->vtotal
, crtc_state
->saveVTOTAL
);
651 REG_WRITE(map
->vblank
, crtc_state
->saveVBLANK
);
652 REG_WRITE(map
->vsync
, crtc_state
->saveVSYNC
);
653 REG_WRITE(map
->stride
, crtc_state
->saveDSPSTRIDE
);
655 REG_WRITE(map
->size
, crtc_state
->saveDSPSIZE
);
656 REG_WRITE(map
->pos
, crtc_state
->saveDSPPOS
);
658 REG_WRITE(map
->src
, crtc_state
->savePIPESRC
);
659 REG_WRITE(map
->base
, crtc_state
->saveDSPBASE
);
660 REG_WRITE(map
->conf
, crtc_state
->savePIPECONF
);
662 gma_wait_for_vblank(dev
);
664 REG_WRITE(map
->cntr
, crtc_state
->saveDSPCNTR
);
665 REG_WRITE(map
->base
, crtc_state
->saveDSPBASE
);
667 gma_wait_for_vblank(dev
);
669 palette_reg
= map
->palette
;
670 for (i
= 0; i
< 256; ++i
)
671 REG_WRITE(palette_reg
+ (i
<< 2), crtc_state
->savePalette
[i
]);
674 void gma_encoder_prepare(struct drm_encoder
*encoder
)
676 const struct drm_encoder_helper_funcs
*encoder_funcs
=
677 encoder
->helper_private
;
678 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
679 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
682 void gma_encoder_commit(struct drm_encoder
*encoder
)
684 const struct drm_encoder_helper_funcs
*encoder_funcs
=
685 encoder
->helper_private
;
686 /* lvds has its own version of commit see psb_intel_lvds_commit */
687 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
690 void gma_encoder_destroy(struct drm_encoder
*encoder
)
692 struct gma_encoder
*intel_encoder
= to_gma_encoder(encoder
);
694 drm_encoder_cleanup(encoder
);
695 kfree(intel_encoder
);
698 /* Currently there is only a 1:1 mapping of encoders and connectors */
699 struct drm_encoder
*gma_best_encoder(struct drm_connector
*connector
)
701 struct gma_encoder
*gma_encoder
= gma_attached_encoder(connector
);
703 return &gma_encoder
->base
;
706 void gma_connector_attach_encoder(struct gma_connector
*connector
,
707 struct gma_encoder
*encoder
)
709 connector
->encoder
= encoder
;
710 drm_connector_attach_encoder(&connector
->base
,
714 #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
716 bool gma_pll_is_valid(struct drm_crtc
*crtc
,
717 const struct gma_limit_t
*limit
,
718 struct gma_clock_t
*clock
)
720 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
721 GMA_PLL_INVALID("p1 out of range");
722 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
723 GMA_PLL_INVALID("p out of range");
724 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
725 GMA_PLL_INVALID("m2 out of range");
726 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
727 GMA_PLL_INVALID("m1 out of range");
728 /* On CDV m1 is always 0 */
729 if (clock
->m1
<= clock
->m2
&& clock
->m1
!= 0)
730 GMA_PLL_INVALID("m1 <= m2 && m1 != 0");
731 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
732 GMA_PLL_INVALID("m out of range");
733 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
734 GMA_PLL_INVALID("n out of range");
735 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
736 GMA_PLL_INVALID("vco out of range");
737 /* XXX: We may need to be checking "Dot clock"
738 * depending on the multiplier, connector, etc.,
739 * rather than just a single range.
741 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
742 GMA_PLL_INVALID("dot out of range");
747 bool gma_find_best_pll(const struct gma_limit_t
*limit
,
748 struct drm_crtc
*crtc
, int target
, int refclk
,
749 struct gma_clock_t
*best_clock
)
751 struct drm_device
*dev
= crtc
->dev
;
752 const struct gma_clock_funcs
*clock_funcs
=
753 to_gma_crtc(crtc
)->clock_funcs
;
754 struct gma_clock_t clock
;
757 if (gma_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
758 (REG_READ(LVDS
) & LVDS_PORT_EN
) != 0) {
760 * For LVDS, if the panel is on, just rely on its current
761 * settings for dual-channel. We haven't figured out how to
762 * reliably set up different single/dual channel state, if we
765 if ((REG_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
767 clock
.p2
= limit
->p2
.p2_fast
;
769 clock
.p2
= limit
->p2
.p2_slow
;
771 if (target
< limit
->p2
.dot_limit
)
772 clock
.p2
= limit
->p2
.p2_slow
;
774 clock
.p2
= limit
->p2
.p2_fast
;
777 memset(best_clock
, 0, sizeof(*best_clock
));
779 /* m1 is always 0 on CDV so the outmost loop will run just once */
780 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
781 for (clock
.m2
= limit
->m2
.min
;
782 (clock
.m2
< clock
.m1
|| clock
.m1
== 0) &&
783 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
784 for (clock
.n
= limit
->n
.min
;
785 clock
.n
<= limit
->n
.max
; clock
.n
++) {
786 for (clock
.p1
= limit
->p1
.min
;
787 clock
.p1
<= limit
->p1
.max
;
791 clock_funcs
->clock(refclk
, &clock
);
793 if (!clock_funcs
->pll_is_valid(crtc
,
797 this_err
= abs(clock
.dot
- target
);
798 if (this_err
< err
) {
807 return err
!= target
;