drivers/gpu/drm/gma500/mdfld_tmd_vid.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  * Jim Liu <jim.liu@intel.com>
  25  * Jackie Li<yaodong.li@intel.com>
  26  * Gideon Eaton <eaton.
  27  * Scott Rowe <scott.m.rowe@intel.com>
  28  */
  29
  30 #include <linux/delay.h>
  31
  32 #include "mdfld_dsi_dpi.h"
  33 #include "mdfld_dsi_pkg_sender.h"
  34
  35 static struct drm_display_mode *tmd_vid_get_config_mode(struct drm_device *dev)
  36 {
  37         struct drm_display_mode *mode;
  38         struct drm_psb_private *dev_priv = dev->dev_private;
  39         struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
  40         bool use_gct = false; /*Disable GCT for now*/
  41
  42         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  43         if (!mode)
  44                 return NULL;
  45
  46         if (use_gct) {
  47                 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
  48                 mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
  49                 mode->hsync_start = mode->hdisplay + \
  50                                 ((ti->hsync_offset_hi << 8) | \
  51                                 ti->hsync_offset_lo);
  52                 mode->hsync_end = mode->hsync_start + \
  53                                 ((ti->hsync_pulse_width_hi << 8) | \
  54                                 ti->hsync_pulse_width_lo);
  55                 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
  56                                                                 ti->hblank_lo);
  57                 mode->vsync_start = \
  58                         mode->vdisplay + ((ti->vsync_offset_hi << 8) | \
  59                                                 ti->vsync_offset_lo);
  60                 mode->vsync_end = \
  61                         mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) | \
  62                                                 ti->vsync_pulse_width_lo);
  63                 mode->vtotal = mode->vdisplay + \
  64                                 ((ti->vblank_hi << 8) | ti->vblank_lo);
  65                 mode->clock = ti->pixel_clock * 10;
  66
  67                 dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay);
  68                 dev_dbg(dev->dev, "vdisplay is %d\n", mode->vdisplay);
  69                 dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start);
  70                 dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
  71                 dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
  72                 dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
  73                 dev_dbg(dev->dev, "VSE is %d\n", mode->vsync_end);
  74                 dev_dbg(dev->dev, "vtotal is %d\n", mode->vtotal);
  75                 dev_dbg(dev->dev, "clock is %d\n", mode->clock);
  76         } else {
  77                 mode->hdisplay = 480;
  78                 mode->vdisplay = 854;
  79                 mode->hsync_start = 487;
  80                 mode->hsync_end = 490;
  81                 mode->htotal = 499;
  82                 mode->vsync_start = 861;
  83                 mode->vsync_end = 865;
  84                 mode->vtotal = 873;
  85                 mode->clock = 33264;
  86         }
  87
  88         drm_mode_set_name(mode);
  89         drm_mode_set_crtcinfo(mode, 0);
  90
  91         mode->type |= DRM_MODE_TYPE_PREFERRED;
  92
  93         return mode;
  94 }
  95
  96 static int tmd_vid_get_panel_info(struct drm_device *dev,
  97                                 int pipe,
  98                                 struct panel_info *pi)
  99 {
 100         if (!dev || !pi)
 101                 return -EINVAL;
 102
 103         pi->width_mm = TMD_PANEL_WIDTH;
 104         pi->height_mm = TMD_PANEL_HEIGHT;
 105
 106         return 0;
 107 }
 108
 109 /* ************************************************************************* *\
 110  * FUNCTION: mdfld_init_TMD_MIPI
 111  *
 112  * DESCRIPTION:  This function is called only by mrst_dsi_mode_set and
 113  *               restore_display_registers.  since this function does not
 114  *               acquire the mutex, it is important that the calling function
 115  *               does!
 116 \* ************************************************************************* */
 117
 118 /* FIXME: make the below data u8 instead of u32; note byte order! */
 119 static u32 tmd_cmd_mcap_off[] = {0x000000b2};
 120 static u32 tmd_cmd_enable_lane_switch[] = {0x000101ef};
 121 static u32 tmd_cmd_set_lane_num[] = {0x006360ef};
 122 static u32 tmd_cmd_pushing_clock0[] = {0x00cc2fef};
 123 static u32 tmd_cmd_pushing_clock1[] = {0x00dd6eef};
 124 static u32 tmd_cmd_set_mode[] = {0x000000b3};
 125 static u32 tmd_cmd_set_sync_pulse_mode[] = {0x000961ef};
 126 static u32 tmd_cmd_set_column[] = {0x0100002a, 0x000000df};
 127 static u32 tmd_cmd_set_page[] = {0x0300002b, 0x00000055};
 128 static u32 tmd_cmd_set_video_mode[] = {0x00000153};
 129 /*no auto_bl,need add in furture*/
 130 static u32 tmd_cmd_enable_backlight[] = {0x00005ab4};
 131 static u32 tmd_cmd_set_backlight_dimming[] = {0x00000ebd};
 132
 133 static void mdfld_dsi_tmd_drv_ic_init(struct mdfld_dsi_config *dsi_config,
 134                                       int pipe)
 135 {
 136         struct mdfld_dsi_pkg_sender *sender
 137                         = mdfld_dsi_get_pkg_sender(dsi_config);
 138
 139         DRM_INFO("Enter mdfld init TMD MIPI display.\n");
 140
 141         if (!sender) {
 142                 DRM_ERROR("Cannot get sender\n");
 143                 return;
 144         }
 145
 146         if (dsi_config->dvr_ic_inited)
 147                 return;
 148
 149         msleep(3);
 150
 151         /* FIXME: make the below data u8 instead of u32; note byte order! */
 152
 153         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_mcap_off,
 154                                 sizeof(tmd_cmd_mcap_off), false);
 155         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_enable_lane_switch,
 156                                 sizeof(tmd_cmd_enable_lane_switch), false);
 157         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_lane_num,
 158                                 sizeof(tmd_cmd_set_lane_num), false);
 159         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_pushing_clock0,
 160                                 sizeof(tmd_cmd_pushing_clock0), false);
 161         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_pushing_clock1,
 162                                 sizeof(tmd_cmd_pushing_clock1), false);
 163         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_mode,
 164                                 sizeof(tmd_cmd_set_mode), false);
 165         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_sync_pulse_mode,
 166                                 sizeof(tmd_cmd_set_sync_pulse_mode), false);
 167         mdfld_dsi_send_mcs_long(sender, (u8 *) tmd_cmd_set_column,
 168                                 sizeof(tmd_cmd_set_column), false);
 169         mdfld_dsi_send_mcs_long(sender, (u8 *) tmd_cmd_set_page,
 170                                 sizeof(tmd_cmd_set_page), false);
 171         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_video_mode,
 172                                 sizeof(tmd_cmd_set_video_mode), false);
 173         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_enable_backlight,
 174                                 sizeof(tmd_cmd_enable_backlight), false);
 175         mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_backlight_dimming,
 176                                 sizeof(tmd_cmd_set_backlight_dimming), false);
 177
 178         dsi_config->dvr_ic_inited = 1;
 179 }
 180
 181 /*TPO DPI encoder helper funcs*/
 182 static const struct drm_encoder_helper_funcs
 183                                 mdfld_tpo_dpi_encoder_helper_funcs = {
 184         .dpms = mdfld_dsi_dpi_dpms,
 185         .mode_fixup = mdfld_dsi_dpi_mode_fixup,
 186         .prepare = mdfld_dsi_dpi_prepare,
 187         .mode_set = mdfld_dsi_dpi_mode_set,
 188         .commit = mdfld_dsi_dpi_commit,
 189 };
 190
 191 const struct panel_funcs mdfld_tmd_vid_funcs = {
 192         .encoder_helper_funcs = &mdfld_tpo_dpi_encoder_helper_funcs,
 193         .get_config_mode = &tmd_vid_get_config_mode,
 194         .get_panel_info = tmd_vid_get_panel_info,
 195         .reset = mdfld_dsi_panel_reset,
 196         .drv_ic_init = mdfld_dsi_tmd_drv_ic_init,
 197 };