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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / display / intel_vdsc.c
blobe2716a67b2816d94f3b32ec2c02456ec5c6f9402
1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8
9 #include "i915_drv.h"
10 #include "intel_display_types.h"
11 #include "intel_dsi.h"
12 #include "intel_vdsc.h"
13
14 enum ROW_INDEX_BPP {
15 ROW_INDEX_6BPP = 0,
16 ROW_INDEX_8BPP,
17 ROW_INDEX_10BPP,
18 ROW_INDEX_12BPP,
19 ROW_INDEX_15BPP,
20 MAX_ROW_INDEX
21 };
22
23 enum COLUMN_INDEX_BPC {
24 COLUMN_INDEX_8BPC = 0,
25 COLUMN_INDEX_10BPC,
26 COLUMN_INDEX_12BPC,
27 COLUMN_INDEX_14BPC,
28 COLUMN_INDEX_16BPC,
29 MAX_COLUMN_INDEX
30 };
31
32 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
33 static const u16 rc_buf_thresh[] = {
34 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
35 7744, 7872, 8000, 8064
36 };
37
38 struct rc_parameters {
39 u16 initial_xmit_delay;
40 u8 first_line_bpg_offset;
41 u16 initial_offset;
42 u8 flatness_min_qp;
43 u8 flatness_max_qp;
44 u8 rc_quant_incr_limit0;
45 u8 rc_quant_incr_limit1;
46 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
47 };
48
49 /*
50 * Selected Rate Control Related Parameter Recommended Values
51 * from DSC_v1.11 spec & C Model release: DSC_model_20161212
52 */
53 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
54 {
55 /* 6BPP/8BPC */
56 { 768, 15, 6144, 3, 13, 11, 11, {
57 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
58 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
59 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
60 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
61 }
62 },
63 /* 6BPP/10BPC */
64 { 768, 15, 6144, 7, 17, 15, 15, {
65 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
66 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
67 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
68 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
69 { 17, 18, -12 }
70 }
71 },
72 /* 6BPP/12BPC */
73 { 768, 15, 6144, 11, 21, 19, 19, {
74 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
75 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
76 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
77 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
78 { 21, 22, -12 }
79 }
80 },
81 /* 6BPP/14BPC */
82 { 768, 15, 6144, 15, 25, 23, 27, {
83 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
84 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
85 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
86 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
87 { 25, 26, -12 }
88 }
89 },
90 /* 6BPP/16BPC */
91 { 768, 15, 6144, 19, 29, 27, 27, {
92 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
93 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
94 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
95 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
96 { 29, 30, -12 }
97 }
98 },
99 },
100 {
101 /* 8BPP/8BPC */
102 { 512, 12, 6144, 3, 12, 11, 11, {
103 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
104 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
105 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
106 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
107 }
108 },
109 /* 8BPP/10BPC */
110 { 512, 12, 6144, 7, 16, 15, 15, {
111 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
112 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
113 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
114 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
115 }
116 },
117 /* 8BPP/12BPC */
118 { 512, 12, 6144, 11, 20, 19, 19, {
119 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
120 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
121 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
122 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
123 { 21, 23, -12 }
124 }
125 },
126 /* 8BPP/14BPC */
127 { 512, 12, 6144, 15, 24, 23, 23, {
128 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
129 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
130 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
131 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
132 { 24, 25, -12 }
133 }
134 },
135 /* 8BPP/16BPC */
136 { 512, 12, 6144, 19, 28, 27, 27, {
137 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
138 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
139 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
140 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
141 { 28, 29, -12 }
142 }
143 },
144 },
145 {
146 /* 10BPP/8BPC */
147 { 410, 15, 5632, 3, 12, 11, 11, {
148 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
149 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
150 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
151 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
152 }
153 },
154 /* 10BPP/10BPC */
155 { 410, 15, 5632, 7, 16, 15, 15, {
156 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
157 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
158 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
159 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
160 }
161 },
162 /* 10BPP/12BPC */
163 { 410, 15, 5632, 11, 20, 19, 19, {
164 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
165 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
166 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
167 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
168 { 19, 20, -12 }
169 }
170 },
171 /* 10BPP/14BPC */
172 { 410, 15, 5632, 15, 24, 23, 23, {
173 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
174 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
175 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
176 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
177 { 23, 24, -12 }
178 }
179 },
180 /* 10BPP/16BPC */
181 { 410, 15, 5632, 19, 28, 27, 27, {
182 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
183 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
184 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
185 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
186 { 27, 28, -12 }
187 }
188 },
189 },
190 {
191 /* 12BPP/8BPC */
192 { 341, 15, 2048, 3, 12, 11, 11, {
193 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
194 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
195 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
196 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
197 }
198 },
199 /* 12BPP/10BPC */
200 { 341, 15, 2048, 7, 16, 15, 15, {
201 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
202 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
203 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
204 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
205 }
206 },
207 /* 12BPP/12BPC */
208 { 341, 15, 2048, 11, 20, 19, 19, {
209 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
210 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
211 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
212 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
213 { 21, 23, -12 }
214 }
215 },
216 /* 12BPP/14BPC */
217 { 341, 15, 2048, 15, 24, 23, 23, {
218 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
219 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
220 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
221 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
222 { 22, 23, -12 }
223 }
224 },
225 /* 12BPP/16BPC */
226 { 341, 15, 2048, 19, 28, 27, 27, {
227 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
228 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
229 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
230 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
231 { 26, 27, -12 }
232 }
233 },
234 },
235 {
236 /* 15BPP/8BPC */
237 { 273, 15, 2048, 3, 12, 11, 11, {
238 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
239 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
240 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
241 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
242 }
243 },
244 /* 15BPP/10BPC */
245 { 273, 15, 2048, 7, 16, 15, 15, {
246 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
247 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
248 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
249 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
250 }
251 },
252 /* 15BPP/12BPC */
253 { 273, 15, 2048, 11, 20, 19, 19, {
254 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
255 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
256 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
257 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
258 { 16, 17, -12 }
259 }
260 },
261 /* 15BPP/14BPC */
262 { 273, 15, 2048, 15, 24, 23, 23, {
263 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
264 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
265 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
266 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
267 { 20, 21, -12 }
268 }
269 },
270 /* 15BPP/16BPC */
271 { 273, 15, 2048, 19, 28, 27, 27, {
272 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
273 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
274 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
275 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
276 { 24, 25, -12 }
277 }
278 }
279 }
280
281 };
282
283 static int get_row_index_for_rc_params(u16 compressed_bpp)
284 {
285 switch (compressed_bpp) {
286 case 6:
287 return ROW_INDEX_6BPP;
288 case 8:
289 return ROW_INDEX_8BPP;
290 case 10:
291 return ROW_INDEX_10BPP;
292 case 12:
293 return ROW_INDEX_12BPP;
294 case 15:
295 return ROW_INDEX_15BPP;
296 default:
297 return -EINVAL;
298 }
299 }
300
301 static int get_column_index_for_rc_params(u8 bits_per_component)
302 {
303 switch (bits_per_component) {
304 case 8:
305 return COLUMN_INDEX_8BPC;
306 case 10:
307 return COLUMN_INDEX_10BPC;
308 case 12:
309 return COLUMN_INDEX_12BPC;
310 case 14:
311 return COLUMN_INDEX_14BPC;
312 case 16:
313 return COLUMN_INDEX_16BPC;
314 default:
315 return -EINVAL;
316 }
317 }
318
319 static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
320 u8 bits_per_component)
321 {
322 int row_index, column_index;
323
324 row_index = get_row_index_for_rc_params(compressed_bpp);
325 if (row_index < 0)
326 return NULL;
327
328 column_index = get_column_index_for_rc_params(bits_per_component);
329 if (column_index < 0)
330 return NULL;
331
332 return &rc_parameters[row_index][column_index];
333 }
334
335 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
336 {
337 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
338 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
339 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
340 enum pipe pipe = crtc->pipe;
341
342 if (!INTEL_INFO(i915)->display.has_dsc)
343 return false;
344
345 /* On TGL, DSC is supported on all Pipes */
346 if (INTEL_GEN(i915) >= 12)
347 return true;
348
349 if (INTEL_GEN(i915) >= 10 &&
350 (pipe != PIPE_A ||
351 (cpu_transcoder == TRANSCODER_EDP ||
352 cpu_transcoder == TRANSCODER_DSI_0 ||
353 cpu_transcoder == TRANSCODER_DSI_1)))
354 return true;
355
356 return false;
357 }
358
359 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
360 {
361 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
362 const struct drm_i915_private *i915 = to_i915(crtc->base.dev);
363 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
364
365 if (INTEL_GEN(i915) >= 12)
366 return true;
367
368 if (cpu_transcoder == TRANSCODER_EDP ||
369 cpu_transcoder == TRANSCODER_DSI_0 ||
370 cpu_transcoder == TRANSCODER_DSI_1)
371 return false;
372
373 /* There's no pipe A DSC engine on ICL */
374 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
375
376 return true;
377 }
378
379 int intel_dsc_compute_params(struct intel_encoder *encoder,
380 struct intel_crtc_state *pipe_config)
381 {
382 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
383 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
384 const struct rc_parameters *rc_params;
385 u8 i = 0;
386
387 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
388 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
389 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
390 pipe_config->dsc.slice_count);
391
392 /* Gen 11 does not support YCbCr */
393 vdsc_cfg->simple_422 = false;
394 /* Gen 11 does not support VBR */
395 vdsc_cfg->vbr_enable = false;
396
397 /* Gen 11 only supports integral values of bpp */
398 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
399 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
400
401 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
402 /*
403 * six 0s are appended to the lsb of each threshold value
404 * internally in h/w.
405 * Only 8 bits are allowed for programming RcBufThreshold
406 */
407 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
408 }
409
410 /*
411 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
412 * as per C Model
413 */
414 if (compressed_bpp == 6) {
415 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
416 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
417 }
418
419 rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component);
420 if (!rc_params)
421 return -EINVAL;
422
423 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
424 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
425 vdsc_cfg->initial_offset = rc_params->initial_offset;
426 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
427 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
428 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
429 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
430
431 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
432 vdsc_cfg->rc_range_params[i].range_min_qp =
433 rc_params->rc_range_params[i].range_min_qp;
434 vdsc_cfg->rc_range_params[i].range_max_qp =
435 rc_params->rc_range_params[i].range_max_qp;
436 /*
437 * Range BPG Offset uses 2's complement and is only a 6 bits. So
438 * mask it to get only 6 bits.
439 */
440 vdsc_cfg->rc_range_params[i].range_bpg_offset =
441 rc_params->rc_range_params[i].range_bpg_offset &
442 DSC_RANGE_BPG_OFFSET_MASK;
443 }
444
445 /*
446 * BitsPerComponent value determines mux_word_size:
447 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
448 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
449 * 48 bits
450 */
451 if (vdsc_cfg->bits_per_component == 8 ||
452 vdsc_cfg->bits_per_component == 10)
453 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
454 else if (vdsc_cfg->bits_per_component == 12)
455 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
456
457 /* RC_MODEL_SIZE is a constant across all configurations */
458 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
459 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
460 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
461 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
462
463 return 0;
464 }
465
466 enum intel_display_power_domain
467 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
468 {
469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
470 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
471 enum pipe pipe = crtc->pipe;
472
473 /*
474 * VDSC/joining uses a separate power well, PW2, and requires
475 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
476 *
477 * - ICL eDP/DSI transcoder
478 * - Gen12+ (except RKL) pipe A
479 *
480 * For any other pipe, VDSC/joining uses the power well associated with
481 * the pipe in use. Hence another reference on the pipe power domain
482 * will suffice. (Except no VDSC/joining on ICL pipe A.)
483 */
484 if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
485 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
486 else if (is_pipe_dsc(crtc_state))
487 return POWER_DOMAIN_PIPE(pipe);
488 else
489 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
490 }
491
492 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
493 {
494 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
495 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
496 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
497 enum pipe pipe = crtc->pipe;
498 u32 pps_val = 0;
499 u32 rc_buf_thresh_dword[4];
500 u32 rc_range_params_dword[8];
501 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
502 int i = 0;
503
504 if (crtc_state->bigjoiner)
505 num_vdsc_instances *= 2;
506
507 /* Populate PICTURE_PARAMETER_SET_0 registers */
508 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
509 DSC_VER_MIN_SHIFT |
510 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
511 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
512 if (vdsc_cfg->block_pred_enable)
513 pps_val |= DSC_BLOCK_PREDICTION;
514 if (vdsc_cfg->convert_rgb)
515 pps_val |= DSC_COLOR_SPACE_CONVERSION;
516 if (vdsc_cfg->simple_422)
517 pps_val |= DSC_422_ENABLE;
518 if (vdsc_cfg->vbr_enable)
519 pps_val |= DSC_VBR_ENABLE;
520 drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
521 if (!is_pipe_dsc(crtc_state)) {
522 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
523 pps_val);
524 /*
525 * If 2 VDSC instances are needed, configure PPS for second
526 * VDSC
527 */
528 if (crtc_state->dsc.dsc_split)
529 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
530 pps_val);
531 } else {
532 intel_de_write(dev_priv,
533 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
534 pps_val);
535 if (crtc_state->dsc.dsc_split)
536 intel_de_write(dev_priv,
537 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
538 pps_val);
539 }
540
541 /* Populate PICTURE_PARAMETER_SET_1 registers */
542 pps_val = 0;
543 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
544 drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
545 if (!is_pipe_dsc(crtc_state)) {
546 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
547 pps_val);
548 /*
549 * If 2 VDSC instances are needed, configure PPS for second
550 * VDSC
551 */
552 if (crtc_state->dsc.dsc_split)
553 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
554 pps_val);
555 } else {
556 intel_de_write(dev_priv,
557 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
558 pps_val);
559 if (crtc_state->dsc.dsc_split)
560 intel_de_write(dev_priv,
561 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
562 pps_val);
563 }
564
565 /* Populate PICTURE_PARAMETER_SET_2 registers */
566 pps_val = 0;
567 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
568 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
569 drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
570 if (!is_pipe_dsc(crtc_state)) {
571 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
572 pps_val);
573 /*
574 * If 2 VDSC instances are needed, configure PPS for second
575 * VDSC
576 */
577 if (crtc_state->dsc.dsc_split)
578 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
579 pps_val);
580 } else {
581 intel_de_write(dev_priv,
582 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
583 pps_val);
584 if (crtc_state->dsc.dsc_split)
585 intel_de_write(dev_priv,
586 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
587 pps_val);
588 }
589
590 /* Populate PICTURE_PARAMETER_SET_3 registers */
591 pps_val = 0;
592 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
593 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
594 drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
595 if (!is_pipe_dsc(crtc_state)) {
596 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
597 pps_val);
598 /*
599 * If 2 VDSC instances are needed, configure PPS for second
600 * VDSC
601 */
602 if (crtc_state->dsc.dsc_split)
603 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
604 pps_val);
605 } else {
606 intel_de_write(dev_priv,
607 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
608 pps_val);
609 if (crtc_state->dsc.dsc_split)
610 intel_de_write(dev_priv,
611 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
612 pps_val);
613 }
614
615 /* Populate PICTURE_PARAMETER_SET_4 registers */
616 pps_val = 0;
617 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
618 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
619 drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
620 if (!is_pipe_dsc(crtc_state)) {
621 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
622 pps_val);
623 /*
624 * If 2 VDSC instances are needed, configure PPS for second
625 * VDSC
626 */
627 if (crtc_state->dsc.dsc_split)
628 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
629 pps_val);
630 } else {
631 intel_de_write(dev_priv,
632 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
633 pps_val);
634 if (crtc_state->dsc.dsc_split)
635 intel_de_write(dev_priv,
636 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
637 pps_val);
638 }
639
640 /* Populate PICTURE_PARAMETER_SET_5 registers */
641 pps_val = 0;
642 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
643 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
644 drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
645 if (!is_pipe_dsc(crtc_state)) {
646 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
647 pps_val);
648 /*
649 * If 2 VDSC instances are needed, configure PPS for second
650 * VDSC
651 */
652 if (crtc_state->dsc.dsc_split)
653 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
654 pps_val);
655 } else {
656 intel_de_write(dev_priv,
657 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
658 pps_val);
659 if (crtc_state->dsc.dsc_split)
660 intel_de_write(dev_priv,
661 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
662 pps_val);
663 }
664
665 /* Populate PICTURE_PARAMETER_SET_6 registers */
666 pps_val = 0;
667 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
668 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
669 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
670 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
671 drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
672 if (!is_pipe_dsc(crtc_state)) {
673 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
674 pps_val);
675 /*
676 * If 2 VDSC instances are needed, configure PPS for second
677 * VDSC
678 */
679 if (crtc_state->dsc.dsc_split)
680 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
681 pps_val);
682 } else {
683 intel_de_write(dev_priv,
684 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
685 pps_val);
686 if (crtc_state->dsc.dsc_split)
687 intel_de_write(dev_priv,
688 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
689 pps_val);
690 }
691
692 /* Populate PICTURE_PARAMETER_SET_7 registers */
693 pps_val = 0;
694 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
695 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
696 drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
697 if (!is_pipe_dsc(crtc_state)) {
698 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
699 pps_val);
700 /*
701 * If 2 VDSC instances are needed, configure PPS for second
702 * VDSC
703 */
704 if (crtc_state->dsc.dsc_split)
705 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
706 pps_val);
707 } else {
708 intel_de_write(dev_priv,
709 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
710 pps_val);
711 if (crtc_state->dsc.dsc_split)
712 intel_de_write(dev_priv,
713 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
714 pps_val);
715 }
716
717 /* Populate PICTURE_PARAMETER_SET_8 registers */
718 pps_val = 0;
719 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
720 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
721 drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
722 if (!is_pipe_dsc(crtc_state)) {
723 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
724 pps_val);
725 /*
726 * If 2 VDSC instances are needed, configure PPS for second
727 * VDSC
728 */
729 if (crtc_state->dsc.dsc_split)
730 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
731 pps_val);
732 } else {
733 intel_de_write(dev_priv,
734 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
735 pps_val);
736 if (crtc_state->dsc.dsc_split)
737 intel_de_write(dev_priv,
738 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
739 pps_val);
740 }
741
742 /* Populate PICTURE_PARAMETER_SET_9 registers */
743 pps_val = 0;
744 pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
745 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
746 drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
747 if (!is_pipe_dsc(crtc_state)) {
748 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
749 pps_val);
750 /*
751 * If 2 VDSC instances are needed, configure PPS for second
752 * VDSC
753 */
754 if (crtc_state->dsc.dsc_split)
755 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
756 pps_val);
757 } else {
758 intel_de_write(dev_priv,
759 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
760 pps_val);
761 if (crtc_state->dsc.dsc_split)
762 intel_de_write(dev_priv,
763 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
764 pps_val);
765 }
766
767 /* Populate PICTURE_PARAMETER_SET_10 registers */
768 pps_val = 0;
769 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
770 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
771 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
772 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
773 drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
774 if (!is_pipe_dsc(crtc_state)) {
775 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
776 pps_val);
777 /*
778 * If 2 VDSC instances are needed, configure PPS for second
779 * VDSC
780 */
781 if (crtc_state->dsc.dsc_split)
782 intel_de_write(dev_priv,
783 DSCC_PICTURE_PARAMETER_SET_10, pps_val);
784 } else {
785 intel_de_write(dev_priv,
786 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
787 pps_val);
788 if (crtc_state->dsc.dsc_split)
789 intel_de_write(dev_priv,
790 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
791 pps_val);
792 }
793
794 /* Populate Picture parameter set 16 */
795 pps_val = 0;
796 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
797 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
798 vdsc_cfg->slice_width) |
799 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
800 vdsc_cfg->slice_height);
801 drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
802 if (!is_pipe_dsc(crtc_state)) {
803 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
804 pps_val);
805 /*
806 * If 2 VDSC instances are needed, configure PPS for second
807 * VDSC
808 */
809 if (crtc_state->dsc.dsc_split)
810 intel_de_write(dev_priv,
811 DSCC_PICTURE_PARAMETER_SET_16, pps_val);
812 } else {
813 intel_de_write(dev_priv,
814 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
815 pps_val);
816 if (crtc_state->dsc.dsc_split)
817 intel_de_write(dev_priv,
818 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
819 pps_val);
820 }
821
822 /* Populate the RC_BUF_THRESH registers */
823 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
824 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
825 rc_buf_thresh_dword[i / 4] |=
826 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
827 BITS_PER_BYTE * (i % 4));
828 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i,
829 rc_buf_thresh_dword[i / 4]);
830 }
831 if (!is_pipe_dsc(crtc_state)) {
832 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
833 rc_buf_thresh_dword[0]);
834 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
835 rc_buf_thresh_dword[1]);
836 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
837 rc_buf_thresh_dword[2]);
838 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
839 rc_buf_thresh_dword[3]);
840 if (crtc_state->dsc.dsc_split) {
841 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
842 rc_buf_thresh_dword[0]);
843 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
844 rc_buf_thresh_dword[1]);
845 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
846 rc_buf_thresh_dword[2]);
847 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
848 rc_buf_thresh_dword[3]);
849 }
850 } else {
851 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
852 rc_buf_thresh_dword[0]);
853 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
854 rc_buf_thresh_dword[1]);
855 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
856 rc_buf_thresh_dword[2]);
857 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
858 rc_buf_thresh_dword[3]);
859 if (crtc_state->dsc.dsc_split) {
860 intel_de_write(dev_priv,
861 ICL_DSC1_RC_BUF_THRESH_0(pipe),
862 rc_buf_thresh_dword[0]);
863 intel_de_write(dev_priv,
864 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
865 rc_buf_thresh_dword[1]);
866 intel_de_write(dev_priv,
867 ICL_DSC1_RC_BUF_THRESH_1(pipe),
868 rc_buf_thresh_dword[2]);
869 intel_de_write(dev_priv,
870 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
871 rc_buf_thresh_dword[3]);
872 }
873 }
874
875 /* Populate the RC_RANGE_PARAMETERS registers */
876 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
877 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
878 rc_range_params_dword[i / 2] |=
879 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
880 RC_BPG_OFFSET_SHIFT) |
881 (vdsc_cfg->rc_range_params[i].range_max_qp <<
882 RC_MAX_QP_SHIFT) |
883 (vdsc_cfg->rc_range_params[i].range_min_qp <<
884 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
885 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i,
886 rc_range_params_dword[i / 2]);
887 }
888 if (!is_pipe_dsc(crtc_state)) {
889 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
890 rc_range_params_dword[0]);
891 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
892 rc_range_params_dword[1]);
893 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
894 rc_range_params_dword[2]);
895 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
896 rc_range_params_dword[3]);
897 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
898 rc_range_params_dword[4]);
899 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
900 rc_range_params_dword[5]);
901 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
902 rc_range_params_dword[6]);
903 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
904 rc_range_params_dword[7]);
905 if (crtc_state->dsc.dsc_split) {
906 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
907 rc_range_params_dword[0]);
908 intel_de_write(dev_priv,
909 DSCC_RC_RANGE_PARAMETERS_0_UDW,
910 rc_range_params_dword[1]);
911 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
912 rc_range_params_dword[2]);
913 intel_de_write(dev_priv,
914 DSCC_RC_RANGE_PARAMETERS_1_UDW,
915 rc_range_params_dword[3]);
916 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
917 rc_range_params_dword[4]);
918 intel_de_write(dev_priv,
919 DSCC_RC_RANGE_PARAMETERS_2_UDW,
920 rc_range_params_dword[5]);
921 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
922 rc_range_params_dword[6]);
923 intel_de_write(dev_priv,
924 DSCC_RC_RANGE_PARAMETERS_3_UDW,
925 rc_range_params_dword[7]);
926 }
927 } else {
928 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
929 rc_range_params_dword[0]);
930 intel_de_write(dev_priv,
931 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
932 rc_range_params_dword[1]);
933 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
934 rc_range_params_dword[2]);
935 intel_de_write(dev_priv,
936 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
937 rc_range_params_dword[3]);
938 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
939 rc_range_params_dword[4]);
940 intel_de_write(dev_priv,
941 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
942 rc_range_params_dword[5]);
943 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
944 rc_range_params_dword[6]);
945 intel_de_write(dev_priv,
946 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
947 rc_range_params_dword[7]);
948 if (crtc_state->dsc.dsc_split) {
949 intel_de_write(dev_priv,
950 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
951 rc_range_params_dword[0]);
952 intel_de_write(dev_priv,
953 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
954 rc_range_params_dword[1]);
955 intel_de_write(dev_priv,
956 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
957 rc_range_params_dword[2]);
958 intel_de_write(dev_priv,
959 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
960 rc_range_params_dword[3]);
961 intel_de_write(dev_priv,
962 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
963 rc_range_params_dword[4]);
964 intel_de_write(dev_priv,
965 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
966 rc_range_params_dword[5]);
967 intel_de_write(dev_priv,
968 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
969 rc_range_params_dword[6]);
970 intel_de_write(dev_priv,
971 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
972 rc_range_params_dword[7]);
973 }
974 }
975 }
976
977 static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
978 const struct intel_crtc_state *crtc_state)
979 {
980 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
981 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
982 struct mipi_dsi_device *dsi;
983 struct drm_dsc_picture_parameter_set pps;
984 enum port port;
985
986 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
987
988 for_each_dsi_port(port, intel_dsi->ports) {
989 dsi = intel_dsi->dsi_hosts[port]->device;
990
991 mipi_dsi_picture_parameter_set(dsi, &pps);
992 mipi_dsi_compression_mode(dsi, true);
993 }
994 }
995
996 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
997 const struct intel_crtc_state *crtc_state)
998 {
999 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1000 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1001 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1002 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1003
1004 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
1005 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
1006
1007 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
1008 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
1009
1010 dig_port->write_infoframe(encoder, crtc_state,
1011 DP_SDP_PPS, &dp_dsc_pps_sdp,
1012 sizeof(dp_dsc_pps_sdp));
1013 }
1014
1015 static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state)
1016 {
1017 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1018
1019 if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
1020 return DSS_CTL1;
1021
1022 return ICL_PIPE_DSS_CTL1(pipe);
1023 }
1024
1025 static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
1026 {
1027 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1028
1029 if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
1030 return DSS_CTL2;
1031
1032 return ICL_PIPE_DSS_CTL2(pipe);
1033 }
1034
1035 void intel_dsc_enable(struct intel_encoder *encoder,
1036 const struct intel_crtc_state *crtc_state)
1037 {
1038 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040 u32 dss_ctl1_val = 0;
1041 u32 dss_ctl2_val = 0;
1042
1043 if (!crtc_state->dsc.compression_enable)
1044 return;
1045
1046 intel_dsc_pps_configure(crtc_state);
1047
1048 if (!crtc_state->bigjoiner_slave) {
1049 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1050 intel_dsc_dsi_pps_write(encoder, crtc_state);
1051 else
1052 intel_dsc_dp_pps_write(encoder, crtc_state);
1053 }
1054
1055 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1056 if (crtc_state->dsc.dsc_split) {
1057 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1058 dss_ctl1_val |= JOINER_ENABLE;
1059 }
1060 if (crtc_state->bigjoiner) {
1061 dss_ctl1_val |= BIG_JOINER_ENABLE;
1062 if (!crtc_state->bigjoiner_slave)
1063 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
1064 }
1065 intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
1066 intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val);
1067 }
1068
1069 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1070 {
1071 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1072 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1073
1074 if (!old_crtc_state->dsc.compression_enable)
1075 return;
1076
1077 intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
1078 intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
1079 }
1080
1081 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
1082 {
1083 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1084 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1085 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1086 enum pipe pipe = crtc->pipe;
1087 enum intel_display_power_domain power_domain;
1088 intel_wakeref_t wakeref;
1089 u32 dss_ctl1, dss_ctl2, val;
1090
1091 if (!intel_dsc_source_support(crtc_state))
1092 return;
1093
1094 power_domain = intel_dsc_power_domain(crtc_state);
1095
1096 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1097 if (!wakeref)
1098 return;
1099
1100 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
1101 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state));
1102
1103 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
1104 if (!crtc_state->dsc.compression_enable)
1105 goto out;
1106
1107 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1108 (dss_ctl1 & JOINER_ENABLE);
1109
1110 if (dss_ctl1 & BIG_JOINER_ENABLE) {
1111 crtc_state->bigjoiner = true;
1112
1113 if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {
1114 crtc_state->bigjoiner_slave = true;
1115 if (!WARN_ON(crtc->pipe == PIPE_A))
1116 crtc_state->bigjoiner_linked_crtc =
1117 intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
1118 } else {
1119 if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
1120 crtc_state->bigjoiner_linked_crtc =
1121 intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
1122 }
1123 }
1124
1125 /* FIXME: add more state readout as needed */
1126
1127 /* PPS1 */
1128 if (!is_pipe_dsc(crtc_state))
1129 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1130 else
1131 val = intel_de_read(dev_priv,
1132 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1133 vdsc_cfg->bits_per_pixel = val;
1134 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
1135 out:
1136 intel_display_power_put(dev_priv, power_domain, wakeref);
1137 }
Linux with added FPC-III support