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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / gvt / handlers.c
blobaa7e75cb3e6afb881af95610c8d9f19297ce750c
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include "i915_drv.h"
40 #include "gvt.h"
41 #include "i915_pvinfo.h"
42
43 /* XXX FIXME i915 has changed PP_XXX definition */
44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
49
50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51 {
52 struct drm_i915_private *i915 = gvt->gt->i915;
53
54 if (IS_BROADWELL(i915))
55 return D_BDW;
56 else if (IS_SKYLAKE(i915))
57 return D_SKL;
58 else if (IS_KABYLAKE(i915))
59 return D_KBL;
60 else if (IS_BROXTON(i915))
61 return D_BXT;
62 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
63 return D_CFL;
64
65 return 0;
66 }
67
68 bool intel_gvt_match_device(struct intel_gvt *gvt,
69 unsigned long device)
70 {
71 return intel_gvt_get_device_type(gvt) & device;
72 }
73
74 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
75 void *p_data, unsigned int bytes)
76 {
77 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
78 }
79
80 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
81 void *p_data, unsigned int bytes)
82 {
83 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
84 }
85
86 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
87 unsigned int offset)
88 {
89 struct intel_gvt_mmio_info *e;
90
91 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
92 if (e->offset == offset)
93 return e;
94 }
95 return NULL;
96 }
97
98 static int new_mmio_info(struct intel_gvt *gvt,
99 u32 offset, u8 flags, u32 size,
100 u32 addr_mask, u32 ro_mask, u32 device,
101 gvt_mmio_func read, gvt_mmio_func write)
102 {
103 struct intel_gvt_mmio_info *info, *p;
104 u32 start, end, i;
105
106 if (!intel_gvt_match_device(gvt, device))
107 return 0;
108
109 if (WARN_ON(!IS_ALIGNED(offset, 4)))
110 return -EINVAL;
111
112 start = offset;
113 end = offset + size;
114
115 for (i = start; i < end; i += 4) {
116 info = kzalloc(sizeof(*info), GFP_KERNEL);
117 if (!info)
118 return -ENOMEM;
119
120 info->offset = i;
121 p = find_mmio_info(gvt, info->offset);
122 if (p) {
123 WARN(1, "dup mmio definition offset %x\n",
124 info->offset);
125 kfree(info);
126
127 /* We return -EEXIST here to make GVT-g load fail.
128 * So duplicated MMIO can be found as soon as
129 * possible.
130 */
131 return -EEXIST;
132 }
133
134 info->ro_mask = ro_mask;
135 info->device = device;
136 info->read = read ? read : intel_vgpu_default_mmio_read;
137 info->write = write ? write : intel_vgpu_default_mmio_write;
138 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
139 INIT_HLIST_NODE(&info->node);
140 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
141 gvt->mmio.num_tracked_mmio++;
142 }
143 return 0;
144 }
145
146 /**
147 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine
148 * @gvt: a GVT device
149 * @offset: register offset
150 *
151 * Returns:
152 * The engine containing the offset within its mmio page.
153 */
154 const struct intel_engine_cs *
155 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset)
156 {
157 struct intel_engine_cs *engine;
158 enum intel_engine_id id;
159
160 offset &= ~GENMASK(11, 0);
161 for_each_engine(engine, gvt->gt, id)
162 if (engine->mmio_base == offset)
163 return engine;
164
165 return NULL;
166 }
167
168 #define offset_to_fence_num(offset) \
169 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
170
171 #define fence_num_to_offset(num) \
172 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
173
174
175 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
176 {
177 switch (reason) {
178 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
179 pr_err("Detected your guest driver doesn't support GVT-g.\n");
180 break;
181 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
182 pr_err("Graphics resource is not enough for the guest\n");
183 break;
184 case GVT_FAILSAFE_GUEST_ERR:
185 pr_err("GVT Internal error for the guest\n");
186 break;
187 default:
188 break;
189 }
190 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
191 vgpu->failsafe = true;
192 }
193
194 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
195 unsigned int fence_num, void *p_data, unsigned int bytes)
196 {
197 unsigned int max_fence = vgpu_fence_sz(vgpu);
198
199 if (fence_num >= max_fence) {
200 gvt_vgpu_err("access oob fence reg %d/%d\n",
201 fence_num, max_fence);
202
203 /* When guest access oob fence regs without access
204 * pv_info first, we treat guest not supporting GVT,
205 * and we will let vgpu enter failsafe mode.
206 */
207 if (!vgpu->pv_notified)
208 enter_failsafe_mode(vgpu,
209 GVT_FAILSAFE_UNSUPPORTED_GUEST);
210
211 memset(p_data, 0, bytes);
212 return -EINVAL;
213 }
214 return 0;
215 }
216
217 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
218 unsigned int offset, void *p_data, unsigned int bytes)
219 {
220 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
221
222 if (INTEL_GEN(vgpu->gvt->gt->i915) <= 10) {
223 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
224 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
225 else if (!ips)
226 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
227 else {
228 /* All engines must be enabled together for vGPU,
229 * since we don't know which engine the ppgtt will
230 * bind to when shadowing.
231 */
232 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
233 ips);
234 return -EINVAL;
235 }
236 }
237
238 write_vreg(vgpu, offset, p_data, bytes);
239 return 0;
240 }
241
242 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
243 void *p_data, unsigned int bytes)
244 {
245 int ret;
246
247 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
248 p_data, bytes);
249 if (ret)
250 return ret;
251 read_vreg(vgpu, off, p_data, bytes);
252 return 0;
253 }
254
255 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
256 void *p_data, unsigned int bytes)
257 {
258 struct intel_gvt *gvt = vgpu->gvt;
259 unsigned int fence_num = offset_to_fence_num(off);
260 int ret;
261
262 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
263 if (ret)
264 return ret;
265 write_vreg(vgpu, off, p_data, bytes);
266
267 mmio_hw_access_pre(gvt->gt);
268 intel_vgpu_write_fence(vgpu, fence_num,
269 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
270 mmio_hw_access_post(gvt->gt);
271 return 0;
272 }
273
274 #define CALC_MODE_MASK_REG(old, new) \
275 (((new) & GENMASK(31, 16)) \
276 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
277 | ((new) & ((new) >> 16))))
278
279 static int mul_force_wake_write(struct intel_vgpu *vgpu,
280 unsigned int offset, void *p_data, unsigned int bytes)
281 {
282 u32 old, new;
283 u32 ack_reg_offset;
284
285 old = vgpu_vreg(vgpu, offset);
286 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
287
288 if (INTEL_GEN(vgpu->gvt->gt->i915) >= 9) {
289 switch (offset) {
290 case FORCEWAKE_RENDER_GEN9_REG:
291 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
292 break;
293 case FORCEWAKE_GT_GEN9_REG:
294 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG;
295 break;
296 case FORCEWAKE_MEDIA_GEN9_REG:
297 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
298 break;
299 default:
300 /*should not hit here*/
301 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
302 return -EINVAL;
303 }
304 } else {
305 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
306 }
307
308 vgpu_vreg(vgpu, offset) = new;
309 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
310 return 0;
311 }
312
313 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
314 void *p_data, unsigned int bytes)
315 {
316 intel_engine_mask_t engine_mask = 0;
317 u32 data;
318
319 write_vreg(vgpu, offset, p_data, bytes);
320 data = vgpu_vreg(vgpu, offset);
321
322 if (data & GEN6_GRDOM_FULL) {
323 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
324 engine_mask = ALL_ENGINES;
325 } else {
326 if (data & GEN6_GRDOM_RENDER) {
327 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
328 engine_mask |= BIT(RCS0);
329 }
330 if (data & GEN6_GRDOM_MEDIA) {
331 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
332 engine_mask |= BIT(VCS0);
333 }
334 if (data & GEN6_GRDOM_BLT) {
335 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
336 engine_mask |= BIT(BCS0);
337 }
338 if (data & GEN6_GRDOM_VECS) {
339 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
340 engine_mask |= BIT(VECS0);
341 }
342 if (data & GEN8_GRDOM_MEDIA2) {
343 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
344 engine_mask |= BIT(VCS1);
345 }
346 if (data & GEN9_GRDOM_GUC) {
347 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
348 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
349 }
350 engine_mask &= vgpu->gvt->gt->info.engine_mask;
351 }
352
353 /* vgpu_lock already hold by emulate mmio r/w */
354 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
355
356 /* sw will wait for the device to ack the reset request */
357 vgpu_vreg(vgpu, offset) = 0;
358
359 return 0;
360 }
361
362 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
363 void *p_data, unsigned int bytes)
364 {
365 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
366 }
367
368 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
369 void *p_data, unsigned int bytes)
370 {
371 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
372 }
373
374 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
375 unsigned int offset, void *p_data, unsigned int bytes)
376 {
377 write_vreg(vgpu, offset, p_data, bytes);
378
379 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
382 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
383 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
384
385 } else
386 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
387 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
388 | PP_CYCLE_DELAY_ACTIVE);
389 return 0;
390 }
391
392 static int transconf_mmio_write(struct intel_vgpu *vgpu,
393 unsigned int offset, void *p_data, unsigned int bytes)
394 {
395 write_vreg(vgpu, offset, p_data, bytes);
396
397 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
398 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
399 else
400 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
401 return 0;
402 }
403
404 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
405 void *p_data, unsigned int bytes)
406 {
407 write_vreg(vgpu, offset, p_data, bytes);
408
409 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
410 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
411 else
412 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
413
414 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
415 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
416 else
417 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
418
419 return 0;
420 }
421
422 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
423 void *p_data, unsigned int bytes)
424 {
425 switch (offset) {
426 case 0xe651c:
427 case 0xe661c:
428 case 0xe671c:
429 case 0xe681c:
430 vgpu_vreg(vgpu, offset) = 1 << 17;
431 break;
432 case 0xe6c04:
433 vgpu_vreg(vgpu, offset) = 0x3;
434 break;
435 case 0xe6e1c:
436 vgpu_vreg(vgpu, offset) = 0x2f << 16;
437 break;
438 default:
439 return -EINVAL;
440 }
441
442 read_vreg(vgpu, offset, p_data, bytes);
443 return 0;
444 }
445
446 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
447 void *p_data, unsigned int bytes)
448 {
449 u32 data;
450
451 write_vreg(vgpu, offset, p_data, bytes);
452 data = vgpu_vreg(vgpu, offset);
453
454 if (data & PIPECONF_ENABLE)
455 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
456 else
457 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
458 /* vgpu_lock already hold by emulate mmio r/w */
459 mutex_unlock(&vgpu->vgpu_lock);
460 intel_gvt_check_vblank_emulation(vgpu->gvt);
461 mutex_lock(&vgpu->vgpu_lock);
462 return 0;
463 }
464
465 /* sorted in ascending order */
466 static i915_reg_t force_nonpriv_white_list[] = {
467 _MMIO(0xd80),
468 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
469 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
470 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
471 PS_INVOCATION_COUNT, //_MMIO(0x2348)
472 PS_DEPTH_COUNT, //_MMIO(0x2350)
473 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
474 _MMIO(0x2690),
475 _MMIO(0x2694),
476 _MMIO(0x2698),
477 _MMIO(0x2754),
478 _MMIO(0x28a0),
479 _MMIO(0x4de0),
480 _MMIO(0x4de4),
481 _MMIO(0x4dfc),
482 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
483 _MMIO(0x7014),
484 HDC_CHICKEN0,//_MMIO(0x7300)
485 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
486 _MMIO(0x7700),
487 _MMIO(0x7704),
488 _MMIO(0x7708),
489 _MMIO(0x770c),
490 _MMIO(0x83a8),
491 _MMIO(0xb110),
492 GEN8_L3SQCREG4,//_MMIO(0xb118)
493 _MMIO(0xe100),
494 _MMIO(0xe18c),
495 _MMIO(0xe48c),
496 _MMIO(0xe5f4),
497 _MMIO(0x64844),
498 };
499
500 /* a simple bsearch */
501 static inline bool in_whitelist(u32 reg)
502 {
503 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
504 i915_reg_t *array = force_nonpriv_white_list;
505
506 while (left < right) {
507 int mid = (left + right)/2;
508
509 if (reg > array[mid].reg)
510 left = mid + 1;
511 else if (reg < array[mid].reg)
512 right = mid;
513 else
514 return true;
515 }
516 return false;
517 }
518
519 static int force_nonpriv_write(struct intel_vgpu *vgpu,
520 unsigned int offset, void *p_data, unsigned int bytes)
521 {
522 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
523 const struct intel_engine_cs *engine =
524 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
525
526 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) {
527 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
528 vgpu->id, offset, bytes);
529 return -EINVAL;
530 }
531
532 if (!in_whitelist(reg_nonpriv) &&
533 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {
534 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
535 vgpu->id, reg_nonpriv, offset);
536 } else
537 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
538
539 return 0;
540 }
541
542 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
543 void *p_data, unsigned int bytes)
544 {
545 write_vreg(vgpu, offset, p_data, bytes);
546
547 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
548 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
549 } else {
550 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
551 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
552 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
553 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
554 }
555 return 0;
556 }
557
558 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
559 unsigned int offset, void *p_data, unsigned int bytes)
560 {
561 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
562 return 0;
563 }
564
565 #define FDI_LINK_TRAIN_PATTERN1 0
566 #define FDI_LINK_TRAIN_PATTERN2 1
567
568 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
569 {
570 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
571 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
572 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
573
574 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
575 (rx_ctl & FDI_RX_ENABLE) &&
576 (rx_ctl & FDI_AUTO_TRAINING) &&
577 (tx_ctl & DP_TP_CTL_ENABLE) &&
578 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
579 return 1;
580 else
581 return 0;
582 }
583
584 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
585 enum pipe pipe, unsigned int train_pattern)
586 {
587 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
588 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
589 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
590 unsigned int fdi_iir_check_bits;
591
592 fdi_rx_imr = FDI_RX_IMR(pipe);
593 fdi_tx_ctl = FDI_TX_CTL(pipe);
594 fdi_rx_ctl = FDI_RX_CTL(pipe);
595
596 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
597 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
598 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
599 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
600 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
601 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
602 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
603 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
604 } else {
605 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
606 return -EINVAL;
607 }
608
609 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
610 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
611
612 /* If imr bit has been masked */
613 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
614 return 0;
615
616 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
617 == fdi_tx_check_bits)
618 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
619 == fdi_rx_check_bits))
620 return 1;
621 else
622 return 0;
623 }
624
625 #define INVALID_INDEX (~0U)
626
627 static unsigned int calc_index(unsigned int offset, unsigned int start,
628 unsigned int next, unsigned int end, i915_reg_t i915_end)
629 {
630 unsigned int range = next - start;
631
632 if (!end)
633 end = i915_mmio_reg_offset(i915_end);
634 if (offset < start || offset > end)
635 return INVALID_INDEX;
636 offset -= start;
637 return offset / range;
638 }
639
640 #define FDI_RX_CTL_TO_PIPE(offset) \
641 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
642
643 #define FDI_TX_CTL_TO_PIPE(offset) \
644 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
645
646 #define FDI_RX_IMR_TO_PIPE(offset) \
647 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
648
649 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
650 unsigned int offset, void *p_data, unsigned int bytes)
651 {
652 i915_reg_t fdi_rx_iir;
653 unsigned int index;
654 int ret;
655
656 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
657 index = FDI_RX_CTL_TO_PIPE(offset);
658 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
659 index = FDI_TX_CTL_TO_PIPE(offset);
660 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
661 index = FDI_RX_IMR_TO_PIPE(offset);
662 else {
663 gvt_vgpu_err("Unsupport registers %x\n", offset);
664 return -EINVAL;
665 }
666
667 write_vreg(vgpu, offset, p_data, bytes);
668
669 fdi_rx_iir = FDI_RX_IIR(index);
670
671 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
672 if (ret < 0)
673 return ret;
674 if (ret)
675 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
676
677 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
678 if (ret < 0)
679 return ret;
680 if (ret)
681 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
682
683 if (offset == _FDI_RXA_CTL)
684 if (fdi_auto_training_started(vgpu))
685 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
686 DP_TP_STATUS_AUTOTRAIN_DONE;
687 return 0;
688 }
689
690 #define DP_TP_CTL_TO_PORT(offset) \
691 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
692
693 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
694 void *p_data, unsigned int bytes)
695 {
696 i915_reg_t status_reg;
697 unsigned int index;
698 u32 data;
699
700 write_vreg(vgpu, offset, p_data, bytes);
701
702 index = DP_TP_CTL_TO_PORT(offset);
703 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
704 if (data == 0x2) {
705 status_reg = DP_TP_STATUS(index);
706 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
707 }
708 return 0;
709 }
710
711 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
712 unsigned int offset, void *p_data, unsigned int bytes)
713 {
714 u32 reg_val;
715 u32 sticky_mask;
716
717 reg_val = *((u32 *)p_data);
718 sticky_mask = GENMASK(27, 26) | (1 << 24);
719
720 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
721 (vgpu_vreg(vgpu, offset) & sticky_mask);
722 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
723 return 0;
724 }
725
726 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
727 unsigned int offset, void *p_data, unsigned int bytes)
728 {
729 u32 data;
730
731 write_vreg(vgpu, offset, p_data, bytes);
732 data = vgpu_vreg(vgpu, offset);
733
734 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
735 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
736 return 0;
737 }
738
739 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
740 unsigned int offset, void *p_data, unsigned int bytes)
741 {
742 u32 data;
743
744 write_vreg(vgpu, offset, p_data, bytes);
745 data = vgpu_vreg(vgpu, offset);
746
747 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
748 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
749 else
750 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
751 return 0;
752 }
753
754 #define DSPSURF_TO_PIPE(offset) \
755 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
756
757 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
758 void *p_data, unsigned int bytes)
759 {
760 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
761 u32 pipe = DSPSURF_TO_PIPE(offset);
762 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
763
764 write_vreg(vgpu, offset, p_data, bytes);
765 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
766
767 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
768
769 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
770 intel_vgpu_trigger_virtual_event(vgpu, event);
771 else
772 set_bit(event, vgpu->irq.flip_done_event[pipe]);
773
774 return 0;
775 }
776
777 #define SPRSURF_TO_PIPE(offset) \
778 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
779
780 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
781 void *p_data, unsigned int bytes)
782 {
783 u32 pipe = SPRSURF_TO_PIPE(offset);
784 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
785
786 write_vreg(vgpu, offset, p_data, bytes);
787 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
788
789 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
790 intel_vgpu_trigger_virtual_event(vgpu, event);
791 else
792 set_bit(event, vgpu->irq.flip_done_event[pipe]);
793
794 return 0;
795 }
796
797 static int reg50080_mmio_write(struct intel_vgpu *vgpu,
798 unsigned int offset, void *p_data,
799 unsigned int bytes)
800 {
801 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
802 enum pipe pipe = REG_50080_TO_PIPE(offset);
803 enum plane_id plane = REG_50080_TO_PLANE(offset);
804 int event = SKL_FLIP_EVENT(pipe, plane);
805
806 write_vreg(vgpu, offset, p_data, bytes);
807 if (plane == PLANE_PRIMARY) {
808 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
809 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
810 } else {
811 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
812 }
813
814 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
815 intel_vgpu_trigger_virtual_event(vgpu, event);
816 else
817 set_bit(event, vgpu->irq.flip_done_event[pipe]);
818
819 return 0;
820 }
821
822 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
823 unsigned int reg)
824 {
825 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
826 enum intel_gvt_event_type event;
827
828 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
829 event = AUX_CHANNEL_A;
830 else if (reg == _PCH_DPB_AUX_CH_CTL ||
831 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
832 event = AUX_CHANNEL_B;
833 else if (reg == _PCH_DPC_AUX_CH_CTL ||
834 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
835 event = AUX_CHANNEL_C;
836 else if (reg == _PCH_DPD_AUX_CH_CTL ||
837 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
838 event = AUX_CHANNEL_D;
839 else {
840 drm_WARN_ON(&dev_priv->drm, true);
841 return -EINVAL;
842 }
843
844 intel_vgpu_trigger_virtual_event(vgpu, event);
845 return 0;
846 }
847
848 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
849 unsigned int reg, int len, bool data_valid)
850 {
851 /* mark transaction done */
852 value |= DP_AUX_CH_CTL_DONE;
853 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
854 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
855
856 if (data_valid)
857 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
858 else
859 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
860
861 /* message size */
862 value &= ~(0xf << 20);
863 value |= (len << 20);
864 vgpu_vreg(vgpu, reg) = value;
865
866 if (value & DP_AUX_CH_CTL_INTERRUPT)
867 return trigger_aux_channel_interrupt(vgpu, reg);
868 return 0;
869 }
870
871 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
872 u8 t)
873 {
874 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
875 /* training pattern 1 for CR */
876 /* set LANE0_CR_DONE, LANE1_CR_DONE */
877 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
878 /* set LANE2_CR_DONE, LANE3_CR_DONE */
879 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
880 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
881 DPCD_TRAINING_PATTERN_2) {
882 /* training pattern 2 for EQ */
883 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
884 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
885 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
886 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
887 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
888 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
889 /* set INTERLANE_ALIGN_DONE */
890 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
891 DPCD_INTERLANE_ALIGN_DONE;
892 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
893 DPCD_LINK_TRAINING_DISABLED) {
894 /* finish link training */
895 /* set sink status as synchronized */
896 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
897 }
898 }
899
900 #define _REG_HSW_DP_AUX_CH_CTL(dp) \
901 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
902
903 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
904
905 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
906
907 #define dpy_is_valid_port(port) \
908 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
909
910 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
911 unsigned int offset, void *p_data, unsigned int bytes)
912 {
913 struct intel_vgpu_display *display = &vgpu->display;
914 int msg, addr, ctrl, op, len;
915 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
916 struct intel_vgpu_dpcd_data *dpcd = NULL;
917 struct intel_vgpu_port *port = NULL;
918 u32 data;
919
920 if (!dpy_is_valid_port(port_index)) {
921 gvt_vgpu_err("Unsupported DP port access!\n");
922 return 0;
923 }
924
925 write_vreg(vgpu, offset, p_data, bytes);
926 data = vgpu_vreg(vgpu, offset);
927
928 if ((INTEL_GEN(vgpu->gvt->gt->i915) >= 9)
929 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
930 /* SKL DPB/C/D aux ctl register changed */
931 return 0;
932 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) &&
933 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
934 /* write to the data registers */
935 return 0;
936 }
937
938 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
939 /* just want to clear the sticky bits */
940 vgpu_vreg(vgpu, offset) = 0;
941 return 0;
942 }
943
944 port = &display->ports[port_index];
945 dpcd = port->dpcd;
946
947 /* read out message from DATA1 register */
948 msg = vgpu_vreg(vgpu, offset + 4);
949 addr = (msg >> 8) & 0xffff;
950 ctrl = (msg >> 24) & 0xff;
951 len = msg & 0xff;
952 op = ctrl >> 4;
953
954 if (op == GVT_AUX_NATIVE_WRITE) {
955 int t;
956 u8 buf[16];
957
958 if ((addr + len + 1) >= DPCD_SIZE) {
959 /*
960 * Write request exceeds what we supported,
961 * DCPD spec: When a Source Device is writing a DPCD
962 * address not supported by the Sink Device, the Sink
963 * Device shall reply with AUX NACK and “M” equal to
964 * zero.
965 */
966
967 /* NAK the write */
968 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
969 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
970 return 0;
971 }
972
973 /*
974 * Write request format: Headr (command + address + size) occupies
975 * 4 bytes, followed by (len + 1) bytes of data. See details at
976 * intel_dp_aux_transfer().
977 */
978 if ((len + 1 + 4) > AUX_BURST_SIZE) {
979 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
980 return -EINVAL;
981 }
982
983 /* unpack data from vreg to buf */
984 for (t = 0; t < 4; t++) {
985 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
986
987 buf[t * 4] = (r >> 24) & 0xff;
988 buf[t * 4 + 1] = (r >> 16) & 0xff;
989 buf[t * 4 + 2] = (r >> 8) & 0xff;
990 buf[t * 4 + 3] = r & 0xff;
991 }
992
993 /* write to virtual DPCD */
994 if (dpcd && dpcd->data_valid) {
995 for (t = 0; t <= len; t++) {
996 int p = addr + t;
997
998 dpcd->data[p] = buf[t];
999 /* check for link training */
1000 if (p == DPCD_TRAINING_PATTERN_SET)
1001 dp_aux_ch_ctl_link_training(dpcd,
1002 buf[t]);
1003 }
1004 }
1005
1006 /* ACK the write */
1007 vgpu_vreg(vgpu, offset + 4) = 0;
1008 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1009 dpcd && dpcd->data_valid);
1010 return 0;
1011 }
1012
1013 if (op == GVT_AUX_NATIVE_READ) {
1014 int idx, i, ret = 0;
1015
1016 if ((addr + len + 1) >= DPCD_SIZE) {
1017 /*
1018 * read request exceeds what we supported
1019 * DPCD spec: A Sink Device receiving a Native AUX CH
1020 * read request for an unsupported DPCD address must
1021 * reply with an AUX ACK and read data set equal to
1022 * zero instead of replying with AUX NACK.
1023 */
1024
1025 /* ACK the READ*/
1026 vgpu_vreg(vgpu, offset + 4) = 0;
1027 vgpu_vreg(vgpu, offset + 8) = 0;
1028 vgpu_vreg(vgpu, offset + 12) = 0;
1029 vgpu_vreg(vgpu, offset + 16) = 0;
1030 vgpu_vreg(vgpu, offset + 20) = 0;
1031
1032 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1033 true);
1034 return 0;
1035 }
1036
1037 for (idx = 1; idx <= 5; idx++) {
1038 /* clear the data registers */
1039 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1040 }
1041
1042 /*
1043 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1044 */
1045 if ((len + 2) > AUX_BURST_SIZE) {
1046 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1047 return -EINVAL;
1048 }
1049
1050 /* read from virtual DPCD to vreg */
1051 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1052 if (dpcd && dpcd->data_valid) {
1053 for (i = 1; i <= (len + 1); i++) {
1054 int t;
1055
1056 t = dpcd->data[addr + i - 1];
1057 t <<= (24 - 8 * (i % 4));
1058 ret |= t;
1059
1060 if ((i % 4 == 3) || (i == (len + 1))) {
1061 vgpu_vreg(vgpu, offset +
1062 (i / 4 + 1) * 4) = ret;
1063 ret = 0;
1064 }
1065 }
1066 }
1067 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1068 dpcd && dpcd->data_valid);
1069 return 0;
1070 }
1071
1072 /* i2c transaction starts */
1073 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1074
1075 if (data & DP_AUX_CH_CTL_INTERRUPT)
1076 trigger_aux_channel_interrupt(vgpu, offset);
1077 return 0;
1078 }
1079
1080 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1081 void *p_data, unsigned int bytes)
1082 {
1083 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1084 write_vreg(vgpu, offset, p_data, bytes);
1085 return 0;
1086 }
1087
1088 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1089 void *p_data, unsigned int bytes)
1090 {
1091 bool vga_disable;
1092
1093 write_vreg(vgpu, offset, p_data, bytes);
1094 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1095
1096 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1097 vga_disable ? "Disable" : "Enable");
1098 return 0;
1099 }
1100
1101 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1102 unsigned int sbi_offset)
1103 {
1104 struct intel_vgpu_display *display = &vgpu->display;
1105 int num = display->sbi.number;
1106 int i;
1107
1108 for (i = 0; i < num; ++i)
1109 if (display->sbi.registers[i].offset == sbi_offset)
1110 break;
1111
1112 if (i == num)
1113 return 0;
1114
1115 return display->sbi.registers[i].value;
1116 }
1117
1118 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1119 unsigned int offset, u32 value)
1120 {
1121 struct intel_vgpu_display *display = &vgpu->display;
1122 int num = display->sbi.number;
1123 int i;
1124
1125 for (i = 0; i < num; ++i) {
1126 if (display->sbi.registers[i].offset == offset)
1127 break;
1128 }
1129
1130 if (i == num) {
1131 if (num == SBI_REG_MAX) {
1132 gvt_vgpu_err("SBI caching meets maximum limits\n");
1133 return;
1134 }
1135 display->sbi.number++;
1136 }
1137
1138 display->sbi.registers[i].offset = offset;
1139 display->sbi.registers[i].value = value;
1140 }
1141
1142 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1143 void *p_data, unsigned int bytes)
1144 {
1145 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1146 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1147 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1148 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1149 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1150 sbi_offset);
1151 }
1152 read_vreg(vgpu, offset, p_data, bytes);
1153 return 0;
1154 }
1155
1156 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1157 void *p_data, unsigned int bytes)
1158 {
1159 u32 data;
1160
1161 write_vreg(vgpu, offset, p_data, bytes);
1162 data = vgpu_vreg(vgpu, offset);
1163
1164 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1165 data |= SBI_READY;
1166
1167 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1168 data |= SBI_RESPONSE_SUCCESS;
1169
1170 vgpu_vreg(vgpu, offset) = data;
1171
1172 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1173 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1174 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1175 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1176
1177 write_virtual_sbi_register(vgpu, sbi_offset,
1178 vgpu_vreg_t(vgpu, SBI_DATA));
1179 }
1180 return 0;
1181 }
1182
1183 #define _vgtif_reg(x) \
1184 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1185
1186 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1187 void *p_data, unsigned int bytes)
1188 {
1189 bool invalid_read = false;
1190
1191 read_vreg(vgpu, offset, p_data, bytes);
1192
1193 switch (offset) {
1194 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1195 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1196 invalid_read = true;
1197 break;
1198 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1199 _vgtif_reg(avail_rs.fence_num):
1200 if (offset + bytes >
1201 _vgtif_reg(avail_rs.fence_num) + 4)
1202 invalid_read = true;
1203 break;
1204 case 0x78010: /* vgt_caps */
1205 case 0x7881c:
1206 break;
1207 default:
1208 invalid_read = true;
1209 break;
1210 }
1211 if (invalid_read)
1212 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1213 offset, bytes, *(u32 *)p_data);
1214 vgpu->pv_notified = true;
1215 return 0;
1216 }
1217
1218 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1219 {
1220 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1221 struct intel_vgpu_mm *mm;
1222 u64 *pdps;
1223
1224 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1225
1226 switch (notification) {
1227 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1228 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1229 fallthrough;
1230 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1231 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1232 return PTR_ERR_OR_ZERO(mm);
1233 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1234 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1235 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1236 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1237 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1238 case 1: /* Remove this in guest driver. */
1239 break;
1240 default:
1241 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1242 }
1243 return 0;
1244 }
1245
1246 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1247 {
1248 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj;
1249 char *env[3] = {NULL, NULL, NULL};
1250 char vmid_str[20];
1251 char display_ready_str[20];
1252
1253 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1254 env[0] = display_ready_str;
1255
1256 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1257 env[1] = vmid_str;
1258
1259 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1260 }
1261
1262 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1263 void *p_data, unsigned int bytes)
1264 {
1265 u32 data = *(u32 *)p_data;
1266 bool invalid_write = false;
1267
1268 switch (offset) {
1269 case _vgtif_reg(display_ready):
1270 send_display_ready_uevent(vgpu, data ? 1 : 0);
1271 break;
1272 case _vgtif_reg(g2v_notify):
1273 handle_g2v_notification(vgpu, data);
1274 break;
1275 /* add xhot and yhot to handled list to avoid error log */
1276 case _vgtif_reg(cursor_x_hot):
1277 case _vgtif_reg(cursor_y_hot):
1278 case _vgtif_reg(pdp[0].lo):
1279 case _vgtif_reg(pdp[0].hi):
1280 case _vgtif_reg(pdp[1].lo):
1281 case _vgtif_reg(pdp[1].hi):
1282 case _vgtif_reg(pdp[2].lo):
1283 case _vgtif_reg(pdp[2].hi):
1284 case _vgtif_reg(pdp[3].lo):
1285 case _vgtif_reg(pdp[3].hi):
1286 case _vgtif_reg(execlist_context_descriptor_lo):
1287 case _vgtif_reg(execlist_context_descriptor_hi):
1288 break;
1289 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1290 invalid_write = true;
1291 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1292 break;
1293 default:
1294 invalid_write = true;
1295 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1296 offset, bytes, data);
1297 break;
1298 }
1299
1300 if (!invalid_write)
1301 write_vreg(vgpu, offset, p_data, bytes);
1302
1303 return 0;
1304 }
1305
1306 static int pf_write(struct intel_vgpu *vgpu,
1307 unsigned int offset, void *p_data, unsigned int bytes)
1308 {
1309 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1310 u32 val = *(u32 *)p_data;
1311
1312 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1313 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1314 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1315 drm_WARN_ONCE(&i915->drm, true,
1316 "VM(%d): guest is trying to scaling a plane\n",
1317 vgpu->id);
1318 return 0;
1319 }
1320
1321 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1322 }
1323
1324 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1325 unsigned int offset, void *p_data, unsigned int bytes)
1326 {
1327 write_vreg(vgpu, offset, p_data, bytes);
1328
1329 if (vgpu_vreg(vgpu, offset) &
1330 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1331 vgpu_vreg(vgpu, offset) |=
1332 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1333 else
1334 vgpu_vreg(vgpu, offset) &=
1335 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1336 return 0;
1337 }
1338
1339 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1340 unsigned int offset, void *p_data, unsigned int bytes)
1341 {
1342 write_vreg(vgpu, offset, p_data, bytes);
1343
1344 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1345 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1346 else
1347 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1348
1349 return 0;
1350 }
1351
1352 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1353 unsigned int offset, void *p_data, unsigned int bytes)
1354 {
1355 write_vreg(vgpu, offset, p_data, bytes);
1356
1357 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1358 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1359 return 0;
1360 }
1361
1362 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1363 void *p_data, unsigned int bytes)
1364 {
1365 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1366 u32 mode;
1367
1368 write_vreg(vgpu, offset, p_data, bytes);
1369 mode = vgpu_vreg(vgpu, offset);
1370
1371 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1372 drm_WARN_ONCE(&i915->drm, 1,
1373 "VM(%d): iGVT-g doesn't support GuC\n",
1374 vgpu->id);
1375 return 0;
1376 }
1377
1378 return 0;
1379 }
1380
1381 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1382 void *p_data, unsigned int bytes)
1383 {
1384 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1385 u32 trtte = *(u32 *)p_data;
1386
1387 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1388 drm_WARN(&i915->drm, 1,
1389 "VM(%d): Use physical address for TRTT!\n",
1390 vgpu->id);
1391 return -EINVAL;
1392 }
1393 write_vreg(vgpu, offset, p_data, bytes);
1394
1395 return 0;
1396 }
1397
1398 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1399 void *p_data, unsigned int bytes)
1400 {
1401 write_vreg(vgpu, offset, p_data, bytes);
1402 return 0;
1403 }
1404
1405 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1406 void *p_data, unsigned int bytes)
1407 {
1408 u32 v = 0;
1409
1410 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1411 v |= (1 << 0);
1412
1413 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1414 v |= (1 << 8);
1415
1416 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1417 v |= (1 << 16);
1418
1419 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1420 v |= (1 << 24);
1421
1422 vgpu_vreg(vgpu, offset) = v;
1423
1424 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1425 }
1426
1427 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1428 void *p_data, unsigned int bytes)
1429 {
1430 u32 value = *(u32 *)p_data;
1431 u32 cmd = value & 0xff;
1432 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1433
1434 switch (cmd) {
1435 case GEN9_PCODE_READ_MEM_LATENCY:
1436 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1437 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1438 IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1439 IS_COMETLAKE(vgpu->gvt->gt->i915)) {
1440 /**
1441 * "Read memory latency" command on gen9.
1442 * Below memory latency values are read
1443 * from skylake platform.
1444 */
1445 if (!*data0)
1446 *data0 = 0x1e1a1100;
1447 else
1448 *data0 = 0x61514b3d;
1449 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) {
1450 /**
1451 * "Read memory latency" command on gen9.
1452 * Below memory latency values are read
1453 * from Broxton MRB.
1454 */
1455 if (!*data0)
1456 *data0 = 0x16080707;
1457 else
1458 *data0 = 0x16161616;
1459 }
1460 break;
1461 case SKL_PCODE_CDCLK_CONTROL:
1462 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1463 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1464 IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1465 IS_COMETLAKE(vgpu->gvt->gt->i915))
1466 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1467 break;
1468 case GEN6_PCODE_READ_RC6VIDS:
1469 *data0 |= 0x1;
1470 break;
1471 }
1472
1473 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1474 vgpu->id, value, *data0);
1475 /**
1476 * PCODE_READY clear means ready for pcode read/write,
1477 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1478 * always emulate as pcode read/write success and ready for access
1479 * anytime, since we don't touch real physical registers here.
1480 */
1481 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1482 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1483 }
1484
1485 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1486 void *p_data, unsigned int bytes)
1487 {
1488 u32 value = *(u32 *)p_data;
1489 const struct intel_engine_cs *engine =
1490 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1491
1492 if (value != 0 &&
1493 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1494 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1495 offset, value);
1496 return -EINVAL;
1497 }
1498
1499 /*
1500 * Need to emulate all the HWSP register write to ensure host can
1501 * update the VM CSB status correctly. Here listed registers can
1502 * support BDW, SKL or other platforms with same HWSP registers.
1503 */
1504 if (unlikely(!engine)) {
1505 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1506 offset);
1507 return -EINVAL;
1508 }
1509 vgpu->hws_pga[engine->id] = value;
1510 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1511 vgpu->id, value, offset);
1512
1513 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1514 }
1515
1516 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1517 unsigned int offset, void *p_data, unsigned int bytes)
1518 {
1519 u32 v = *(u32 *)p_data;
1520
1521 if (IS_BROXTON(vgpu->gvt->gt->i915))
1522 v &= (1 << 31) | (1 << 29);
1523 else
1524 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1525 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1526 v |= (v >> 1);
1527
1528 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1529 }
1530
1531 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1532 void *p_data, unsigned int bytes)
1533 {
1534 u32 v = *(u32 *)p_data;
1535
1536 /* other bits are MBZ. */
1537 v &= (1 << 31) | (1 << 30);
1538 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1539
1540 vgpu_vreg(vgpu, offset) = v;
1541
1542 return 0;
1543 }
1544
1545 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1546 unsigned int offset, void *p_data, unsigned int bytes)
1547 {
1548 u32 v = *(u32 *)p_data;
1549
1550 if (v & BXT_DE_PLL_PLL_ENABLE)
1551 v |= BXT_DE_PLL_LOCK;
1552
1553 vgpu_vreg(vgpu, offset) = v;
1554
1555 return 0;
1556 }
1557
1558 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1559 unsigned int offset, void *p_data, unsigned int bytes)
1560 {
1561 u32 v = *(u32 *)p_data;
1562
1563 if (v & PORT_PLL_ENABLE)
1564 v |= PORT_PLL_LOCK;
1565
1566 vgpu_vreg(vgpu, offset) = v;
1567
1568 return 0;
1569 }
1570
1571 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1572 unsigned int offset, void *p_data, unsigned int bytes)
1573 {
1574 u32 v = *(u32 *)p_data;
1575 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1576
1577 switch (offset) {
1578 case _PHY_CTL_FAMILY_EDP:
1579 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1580 break;
1581 case _PHY_CTL_FAMILY_DDI:
1582 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1583 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1584 break;
1585 }
1586
1587 vgpu_vreg(vgpu, offset) = v;
1588
1589 return 0;
1590 }
1591
1592 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1593 unsigned int offset, void *p_data, unsigned int bytes)
1594 {
1595 u32 v = vgpu_vreg(vgpu, offset);
1596
1597 v &= ~UNIQUE_TRANGE_EN_METHOD;
1598
1599 vgpu_vreg(vgpu, offset) = v;
1600
1601 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1602 }
1603
1604 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1605 unsigned int offset, void *p_data, unsigned int bytes)
1606 {
1607 u32 v = *(u32 *)p_data;
1608
1609 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1610 vgpu_vreg(vgpu, offset - 0x600) = v;
1611 vgpu_vreg(vgpu, offset - 0x800) = v;
1612 } else {
1613 vgpu_vreg(vgpu, offset - 0x400) = v;
1614 vgpu_vreg(vgpu, offset - 0x600) = v;
1615 }
1616
1617 vgpu_vreg(vgpu, offset) = v;
1618
1619 return 0;
1620 }
1621
1622 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1623 unsigned int offset, void *p_data, unsigned int bytes)
1624 {
1625 u32 v = *(u32 *)p_data;
1626
1627 if (v & BIT(0)) {
1628 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1629 ~PHY_RESERVED;
1630 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1631 PHY_POWER_GOOD;
1632 }
1633
1634 if (v & BIT(1)) {
1635 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1636 ~PHY_RESERVED;
1637 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1638 PHY_POWER_GOOD;
1639 }
1640
1641
1642 vgpu_vreg(vgpu, offset) = v;
1643
1644 return 0;
1645 }
1646
1647 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1648 unsigned int offset, void *p_data, unsigned int bytes)
1649 {
1650 vgpu_vreg(vgpu, offset) = 0;
1651 return 0;
1652 }
1653
1654 /**
1655 * FixMe:
1656 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
1657 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
1658 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
1659 * these MI_BATCH_BUFFER.
1660 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
1661 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1662 * The performance is still expected to be low, will need further improvement.
1663 */
1664 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
1665 void *p_data, unsigned int bytes)
1666 {
1667 u64 pat =
1668 GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1669 GEN8_PPAT(1, 0) |
1670 GEN8_PPAT(2, 0) |
1671 GEN8_PPAT(3, CHV_PPAT_SNOOP) |
1672 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1673 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1674 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1675 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1676
1677 vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
1678
1679 return 0;
1680 }
1681
1682 static int guc_status_read(struct intel_vgpu *vgpu,
1683 unsigned int offset, void *p_data,
1684 unsigned int bytes)
1685 {
1686 /* keep MIA_IN_RESET before clearing */
1687 read_vreg(vgpu, offset, p_data, bytes);
1688 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1689 return 0;
1690 }
1691
1692 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1693 unsigned int offset, void *p_data, unsigned int bytes)
1694 {
1695 struct intel_gvt *gvt = vgpu->gvt;
1696 const struct intel_engine_cs *engine =
1697 intel_gvt_render_mmio_to_engine(gvt, offset);
1698
1699 /**
1700 * Read HW reg in following case
1701 * a. the offset isn't a ring mmio
1702 * b. the offset's ring is running on hw.
1703 * c. the offset is ring time stamp mmio
1704 */
1705
1706 if (!engine ||
1707 vgpu == gvt->scheduler.engine_owner[engine->id] ||
1708 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||
1709 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {
1710 mmio_hw_access_pre(gvt->gt);
1711 vgpu_vreg(vgpu, offset) =
1712 intel_uncore_read(gvt->gt->uncore, _MMIO(offset));
1713 mmio_hw_access_post(gvt->gt);
1714 }
1715
1716 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1717 }
1718
1719 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1720 void *p_data, unsigned int bytes)
1721 {
1722 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1723 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1724 struct intel_vgpu_execlist *execlist;
1725 u32 data = *(u32 *)p_data;
1726 int ret = 0;
1727
1728 if (drm_WARN_ON(&i915->drm, !engine))
1729 return -EINVAL;
1730
1731 execlist = &vgpu->submission.execlist[engine->id];
1732
1733 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
1734 if (execlist->elsp_dwords.index == 3) {
1735 ret = intel_vgpu_submit_execlist(vgpu, engine);
1736 if(ret)
1737 gvt_vgpu_err("fail submit workload on ring %s\n",
1738 engine->name);
1739 }
1740
1741 ++execlist->elsp_dwords.index;
1742 execlist->elsp_dwords.index &= 0x3;
1743 return ret;
1744 }
1745
1746 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1747 void *p_data, unsigned int bytes)
1748 {
1749 u32 data = *(u32 *)p_data;
1750 const struct intel_engine_cs *engine =
1751 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1752 bool enable_execlist;
1753 int ret;
1754
1755 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
1756 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1757 IS_COMETLAKE(vgpu->gvt->gt->i915))
1758 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
1759 write_vreg(vgpu, offset, p_data, bytes);
1760
1761 if (IS_MASKED_BITS_ENABLED(data, 1)) {
1762 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1763 return 0;
1764 }
1765
1766 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1767 IS_COMETLAKE(vgpu->gvt->gt->i915)) &&
1768 IS_MASKED_BITS_ENABLED(data, 2)) {
1769 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1770 return 0;
1771 }
1772
1773 /* when PPGTT mode enabled, we will check if guest has called
1774 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1775 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1776 */
1777 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
1778 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
1779 !vgpu->pv_notified) {
1780 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1781 return 0;
1782 }
1783 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
1784 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
1785 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1786
1787 gvt_dbg_core("EXECLIST %s on ring %s\n",
1788 (enable_execlist ? "enabling" : "disabling"),
1789 engine->name);
1790
1791 if (!enable_execlist)
1792 return 0;
1793
1794 ret = intel_vgpu_select_submission_ops(vgpu,
1795 engine->mask,
1796 INTEL_VGPU_EXECLIST_SUBMISSION);
1797 if (ret)
1798 return ret;
1799
1800 intel_vgpu_start_schedule(vgpu);
1801 }
1802 return 0;
1803 }
1804
1805 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1806 unsigned int offset, void *p_data, unsigned int bytes)
1807 {
1808 unsigned int id = 0;
1809
1810 write_vreg(vgpu, offset, p_data, bytes);
1811 vgpu_vreg(vgpu, offset) = 0;
1812
1813 switch (offset) {
1814 case 0x4260:
1815 id = RCS0;
1816 break;
1817 case 0x4264:
1818 id = VCS0;
1819 break;
1820 case 0x4268:
1821 id = VCS1;
1822 break;
1823 case 0x426c:
1824 id = BCS0;
1825 break;
1826 case 0x4270:
1827 id = VECS0;
1828 break;
1829 default:
1830 return -EINVAL;
1831 }
1832 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
1833
1834 return 0;
1835 }
1836
1837 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1838 unsigned int offset, void *p_data, unsigned int bytes)
1839 {
1840 u32 data;
1841
1842 write_vreg(vgpu, offset, p_data, bytes);
1843 data = vgpu_vreg(vgpu, offset);
1844
1845 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
1846 data |= RESET_CTL_READY_TO_RESET;
1847 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1848 data &= ~RESET_CTL_READY_TO_RESET;
1849
1850 vgpu_vreg(vgpu, offset) = data;
1851 return 0;
1852 }
1853
1854 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
1855 unsigned int offset, void *p_data,
1856 unsigned int bytes)
1857 {
1858 u32 data = *(u32 *)p_data;
1859
1860 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
1861 write_vreg(vgpu, offset, p_data, bytes);
1862
1863 if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
1864 IS_MASKED_BITS_ENABLED(data, 0x8))
1865 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1866
1867 return 0;
1868 }
1869
1870 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1871 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
1872 f, s, am, rm, d, r, w); \
1873 if (ret) \
1874 return ret; \
1875 } while (0)
1876
1877 #define MMIO_D(reg, d) \
1878 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1879
1880 #define MMIO_DH(reg, d, r, w) \
1881 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1882
1883 #define MMIO_DFH(reg, d, f, r, w) \
1884 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1885
1886 #define MMIO_GM(reg, d, r, w) \
1887 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1888
1889 #define MMIO_GM_RDR(reg, d, r, w) \
1890 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1891
1892 #define MMIO_RO(reg, d, f, rm, r, w) \
1893 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1894
1895 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1896 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1897 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1898 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1899 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1900 if (HAS_ENGINE(gvt->gt, VCS1)) \
1901 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1902 } while (0)
1903
1904 #define MMIO_RING_D(prefix, d) \
1905 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1906
1907 #define MMIO_RING_DFH(prefix, d, f, r, w) \
1908 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1909
1910 #define MMIO_RING_GM(prefix, d, r, w) \
1911 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1912
1913 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
1914 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1915
1916 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1917 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1918
1919 static int init_generic_mmio_info(struct intel_gvt *gvt)
1920 {
1921 struct drm_i915_private *dev_priv = gvt->gt->i915;
1922 int ret;
1923
1924 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
1925 intel_vgpu_reg_imr_handler);
1926
1927 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1928 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1929 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1930 MMIO_D(SDEISR, D_ALL);
1931
1932 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
1933
1934
1935 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
1936 gamw_echo_dev_rw_ia_write);
1937
1938 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1939 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1940 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1941
1942 #define RING_REG(base) _MMIO((base) + 0x28)
1943 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1944 #undef RING_REG
1945
1946 #define RING_REG(base) _MMIO((base) + 0x134)
1947 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1948 #undef RING_REG
1949
1950 #define RING_REG(base) _MMIO((base) + 0x6c)
1951 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1952 #undef RING_REG
1953 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1954
1955 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
1956 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
1957 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
1958 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1959
1960 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
1961 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
1962 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
1963 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
1964 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
1965
1966 /* RING MODE */
1967 #define RING_REG(base) _MMIO((base) + 0x29c)
1968 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1969 ring_mode_mmio_write);
1970 #undef RING_REG
1971
1972 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1973 NULL, NULL);
1974 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1975 NULL, NULL);
1976 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1977 mmio_read_from_hw, NULL);
1978 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1979 mmio_read_from_hw, NULL);
1980
1981 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1982 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1983 NULL, NULL);
1984 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1985 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1986 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1987
1988 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1989 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1990 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1991 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
1992 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1993 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1994 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1995 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1996 NULL, NULL);
1997 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1998 NULL, NULL);
1999 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
2000 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
2001 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
2002 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
2003 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
2004 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
2005 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2006 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2007 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2008 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2009
2010 /* display */
2011 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
2012 MMIO_D(_MMIO(0x602a0), D_ALL);
2013
2014 MMIO_D(_MMIO(0x65050), D_ALL);
2015 MMIO_D(_MMIO(0x650b4), D_ALL);
2016
2017 MMIO_D(_MMIO(0xc4040), D_ALL);
2018 MMIO_D(DERRMR, D_ALL);
2019
2020 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
2021 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
2022 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
2023 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
2024
2025 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
2026 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
2027 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
2028 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
2029
2030 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
2031 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
2032 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
2033 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
2034
2035 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
2036 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
2037 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
2038 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
2039
2040 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
2041 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
2042 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
2043 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
2044
2045 MMIO_D(CURCNTR(PIPE_A), D_ALL);
2046 MMIO_D(CURCNTR(PIPE_B), D_ALL);
2047 MMIO_D(CURCNTR(PIPE_C), D_ALL);
2048
2049 MMIO_D(CURPOS(PIPE_A), D_ALL);
2050 MMIO_D(CURPOS(PIPE_B), D_ALL);
2051 MMIO_D(CURPOS(PIPE_C), D_ALL);
2052
2053 MMIO_D(CURBASE(PIPE_A), D_ALL);
2054 MMIO_D(CURBASE(PIPE_B), D_ALL);
2055 MMIO_D(CURBASE(PIPE_C), D_ALL);
2056
2057 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
2058 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
2059 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
2060
2061 MMIO_D(_MMIO(0x700ac), D_ALL);
2062 MMIO_D(_MMIO(0x710ac), D_ALL);
2063 MMIO_D(_MMIO(0x720ac), D_ALL);
2064
2065 MMIO_D(_MMIO(0x70090), D_ALL);
2066 MMIO_D(_MMIO(0x70094), D_ALL);
2067 MMIO_D(_MMIO(0x70098), D_ALL);
2068 MMIO_D(_MMIO(0x7009c), D_ALL);
2069
2070 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
2071 MMIO_D(DSPADDR(PIPE_A), D_ALL);
2072 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
2073 MMIO_D(DSPPOS(PIPE_A), D_ALL);
2074 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
2075 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2076 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
2077 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
2078 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2079 reg50080_mmio_write);
2080
2081 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
2082 MMIO_D(DSPADDR(PIPE_B), D_ALL);
2083 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
2084 MMIO_D(DSPPOS(PIPE_B), D_ALL);
2085 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
2086 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2087 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
2088 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
2089 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2090 reg50080_mmio_write);
2091
2092 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
2093 MMIO_D(DSPADDR(PIPE_C), D_ALL);
2094 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
2095 MMIO_D(DSPPOS(PIPE_C), D_ALL);
2096 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
2097 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2098 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
2099 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
2100 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2101 reg50080_mmio_write);
2102
2103 MMIO_D(SPRCTL(PIPE_A), D_ALL);
2104 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
2105 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
2106 MMIO_D(SPRPOS(PIPE_A), D_ALL);
2107 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
2108 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
2109 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
2110 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
2111 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
2112 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
2113 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
2114 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
2115 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2116 reg50080_mmio_write);
2117
2118 MMIO_D(SPRCTL(PIPE_B), D_ALL);
2119 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
2120 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
2121 MMIO_D(SPRPOS(PIPE_B), D_ALL);
2122 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
2123 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
2124 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
2125 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2126 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
2127 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
2128 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
2129 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
2130 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2131 reg50080_mmio_write);
2132
2133 MMIO_D(SPRCTL(PIPE_C), D_ALL);
2134 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
2135 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
2136 MMIO_D(SPRPOS(PIPE_C), D_ALL);
2137 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
2138 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
2139 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
2140 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2141 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
2142 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
2143 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
2144 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
2145 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2146 reg50080_mmio_write);
2147
2148 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
2149 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
2150 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
2151 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
2152 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
2153 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
2154 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
2155 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
2156 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
2157
2158 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
2159 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
2160 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
2161 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
2162 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
2163 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
2164 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
2165 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
2166 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
2167
2168 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
2169 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
2170 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
2171 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
2172 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
2173 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
2174 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
2175 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
2176 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
2177
2178 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
2179 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
2180 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
2181 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
2182 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
2183 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
2184 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
2185 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
2186
2187 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
2188 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
2189 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
2190 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
2191 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
2192 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
2193 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
2194 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
2195
2196 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
2197 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
2198 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
2199 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
2200 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
2201 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
2202 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
2203 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
2204
2205 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
2206 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
2207 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
2208 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
2209 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
2210 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
2211 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
2212 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
2213
2214 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
2215 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
2216 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
2217 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
2218 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
2219 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
2220 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
2221 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
2222
2223 MMIO_D(PF_CTL(PIPE_A), D_ALL);
2224 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
2225 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
2226 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
2227 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
2228
2229 MMIO_D(PF_CTL(PIPE_B), D_ALL);
2230 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
2231 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
2232 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
2233 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
2234
2235 MMIO_D(PF_CTL(PIPE_C), D_ALL);
2236 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
2237 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
2238 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
2239 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
2240
2241 MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
2242 MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
2243 MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
2244 MMIO_D(WM1_LP_ILK, D_ALL);
2245 MMIO_D(WM2_LP_ILK, D_ALL);
2246 MMIO_D(WM3_LP_ILK, D_ALL);
2247 MMIO_D(WM1S_LP_ILK, D_ALL);
2248 MMIO_D(WM2S_LP_IVB, D_ALL);
2249 MMIO_D(WM3S_LP_IVB, D_ALL);
2250
2251 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
2252 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
2253 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
2254 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
2255
2256 MMIO_D(_MMIO(0x48268), D_ALL);
2257
2258 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2259 gmbus_mmio_write);
2260 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2261 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
2262
2263 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2264 dp_aux_ch_ctl_mmio_write);
2265 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2266 dp_aux_ch_ctl_mmio_write);
2267 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2268 dp_aux_ch_ctl_mmio_write);
2269
2270 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2271
2272 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2273 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2274
2275 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2276 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2277 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2278 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2279 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2280 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2281 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2282 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2283 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2284
2285 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
2286 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
2287 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
2288 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
2289 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
2290 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
2291 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
2292
2293 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
2294 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
2295 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
2296 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
2297 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
2298 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
2299 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
2300
2301 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2302 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2303 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2304 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2305 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2306 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2307 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2308 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
2309
2310 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2311 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2312 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2313
2314 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2315 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2316 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2317
2318 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2319 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2320 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2321
2322 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2323 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2324 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2325
2326 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2327 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2328 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2329 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2330 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2331 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
2332
2333 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2334 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2335 MMIO_D(PCH_PP_STATUS, D_ALL);
2336 MMIO_D(PCH_LVDS, D_ALL);
2337 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2338 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2339 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2340 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2341 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2342 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
2343 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2344 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2345 MMIO_D(PCH_DPLL_SEL, D_ALL);
2346
2347 MMIO_D(_MMIO(0x61208), D_ALL);
2348 MMIO_D(_MMIO(0x6120c), D_ALL);
2349 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2350 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2351
2352 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2353 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2354 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2355 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2356 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2357 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2358
2359 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2360 PORTA_HOTPLUG_STATUS_MASK
2361 | PORTB_HOTPLUG_STATUS_MASK
2362 | PORTC_HOTPLUG_STATUS_MASK
2363 | PORTD_HOTPLUG_STATUS_MASK,
2364 NULL, NULL);
2365
2366 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2367 MMIO_D(FUSE_STRAP, D_ALL);
2368 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2369
2370 MMIO_D(DISP_ARB_CTL, D_ALL);
2371 MMIO_D(DISP_ARB_CTL2, D_ALL);
2372
2373 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2374 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2375 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2376
2377 MMIO_D(SOUTH_CHICKEN1, D_ALL);
2378 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2379 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2380 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
2381 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2382 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2383 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
2384
2385 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2386 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2387 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2388 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2389 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2390 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2391 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2392
2393 MMIO_D(IPS_CTL, D_ALL);
2394
2395 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2396 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2397 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2398 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2399 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2400 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2401 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2402 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2403 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2404 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2405 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2406 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2407 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2408
2409 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2410 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2411 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2412 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2413 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2414 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2415 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2416 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2417 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2418 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2419 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2420 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2421 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2422
2423 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2424 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2425 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2426 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2427 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2428 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2429 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2430 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2431 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2432 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2433 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2434 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2435 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2436
2437 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2438 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2439 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2440
2441 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2442 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2443 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2444
2445 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2446 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2447 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2448
2449 MMIO_D(_MMIO(0x60110), D_ALL);
2450 MMIO_D(_MMIO(0x61110), D_ALL);
2451 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2452 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2453 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2454 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2455 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2456 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2457 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2458 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2459 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2460
2461 MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
2462 MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
2463 MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
2464 MMIO_D(SPLL_CTL, D_ALL);
2465 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2466 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
2467 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2468 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2469 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2470 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2471 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2472 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2473 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2474 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2475
2476 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2477 MMIO_D(_MMIO(0x46508), D_ALL);
2478
2479 MMIO_D(_MMIO(0x49080), D_ALL);
2480 MMIO_D(_MMIO(0x49180), D_ALL);
2481 MMIO_D(_MMIO(0x49280), D_ALL);
2482
2483 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2484 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2485 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2486
2487 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2488 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2489 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2490
2491 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2492 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2493 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2494
2495 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2496 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2497 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2498
2499 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2500 MMIO_D(SBI_ADDR, D_ALL);
2501 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2502 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2503 MMIO_D(PIXCLK_GATE, D_ALL);
2504
2505 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
2506 dp_aux_ch_ctl_mmio_write);
2507
2508 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2509 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2510 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2511 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2512 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2513
2514 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2515 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2516 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2517 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2518 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2519
2520 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2521 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2522 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2523 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2524 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2525
2526 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2527 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2528 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2529 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2530 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2531
2532 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2533 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2534 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
2535
2536 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2537 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2538 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2539 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2540
2541 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2542 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2543 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2544 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
2545
2546 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2547 MMIO_D(FORCEWAKE_ACK, D_ALL);
2548 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2549 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2550 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2551 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2552 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2553 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2554 MMIO_D(ECOBUS, D_ALL);
2555 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2556 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2557 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2558 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2559 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2560 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2561 MMIO_D(GEN6_RPSTAT1, D_ALL);
2562 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2563 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2564 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2565 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2566 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2567 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2568 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2569 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2570 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2571 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2572 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2573 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2574 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2575 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2576 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2577 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2578 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2579 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2580 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2581 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2582 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2583 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2584 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2585 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2586 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2587 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2588 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2589 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2590 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2591
2592 MMIO_D(RSTDBYCTL, D_ALL);
2593
2594 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2595 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2596 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2597
2598 MMIO_D(TILECTL, D_ALL);
2599
2600 MMIO_D(GEN6_UCGCTL1, D_ALL);
2601 MMIO_D(GEN6_UCGCTL2, D_ALL);
2602
2603 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2604
2605 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2606 MMIO_D(_MMIO(0x13812c), D_ALL);
2607 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2608 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2609 MMIO_D(HSW_IDICR, D_ALL);
2610 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2611
2612 MMIO_D(_MMIO(0x3c), D_ALL);
2613 MMIO_D(_MMIO(0x860), D_ALL);
2614 MMIO_D(ECOSKPD, D_ALL);
2615 MMIO_D(_MMIO(0x121d0), D_ALL);
2616 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2617 MMIO_D(_MMIO(0x41d0), D_ALL);
2618 MMIO_D(GAC_ECO_BITS, D_ALL);
2619 MMIO_D(_MMIO(0x6200), D_ALL);
2620 MMIO_D(_MMIO(0x6204), D_ALL);
2621 MMIO_D(_MMIO(0x6208), D_ALL);
2622 MMIO_D(_MMIO(0x7118), D_ALL);
2623 MMIO_D(_MMIO(0x7180), D_ALL);
2624 MMIO_D(_MMIO(0x7408), D_ALL);
2625 MMIO_D(_MMIO(0x7c00), D_ALL);
2626 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2627 MMIO_D(_MMIO(0x911c), D_ALL);
2628 MMIO_D(_MMIO(0x9120), D_ALL);
2629 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2630
2631 MMIO_D(GAB_CTL, D_ALL);
2632 MMIO_D(_MMIO(0x48800), D_ALL);
2633 MMIO_D(_MMIO(0xce044), D_ALL);
2634 MMIO_D(_MMIO(0xe6500), D_ALL);
2635 MMIO_D(_MMIO(0xe6504), D_ALL);
2636 MMIO_D(_MMIO(0xe6600), D_ALL);
2637 MMIO_D(_MMIO(0xe6604), D_ALL);
2638 MMIO_D(_MMIO(0xe6700), D_ALL);
2639 MMIO_D(_MMIO(0xe6704), D_ALL);
2640 MMIO_D(_MMIO(0xe6800), D_ALL);
2641 MMIO_D(_MMIO(0xe6804), D_ALL);
2642 MMIO_D(PCH_GMBUS4, D_ALL);
2643 MMIO_D(PCH_GMBUS5, D_ALL);
2644
2645 MMIO_D(_MMIO(0x902c), D_ALL);
2646 MMIO_D(_MMIO(0xec008), D_ALL);
2647 MMIO_D(_MMIO(0xec00c), D_ALL);
2648 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2649 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2650 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2651 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2652 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2653 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2654 MMIO_D(_MMIO(0xec408), D_ALL);
2655 MMIO_D(_MMIO(0xec40c), D_ALL);
2656 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2657 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2658 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2659 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2660 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2661 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2662 MMIO_D(_MMIO(0xfc810), D_ALL);
2663 MMIO_D(_MMIO(0xfc81c), D_ALL);
2664 MMIO_D(_MMIO(0xfc828), D_ALL);
2665 MMIO_D(_MMIO(0xfc834), D_ALL);
2666 MMIO_D(_MMIO(0xfcc00), D_ALL);
2667 MMIO_D(_MMIO(0xfcc0c), D_ALL);
2668 MMIO_D(_MMIO(0xfcc18), D_ALL);
2669 MMIO_D(_MMIO(0xfcc24), D_ALL);
2670 MMIO_D(_MMIO(0xfd000), D_ALL);
2671 MMIO_D(_MMIO(0xfd00c), D_ALL);
2672 MMIO_D(_MMIO(0xfd018), D_ALL);
2673 MMIO_D(_MMIO(0xfd024), D_ALL);
2674 MMIO_D(_MMIO(0xfd034), D_ALL);
2675
2676 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2677 MMIO_D(_MMIO(0x2054), D_ALL);
2678 MMIO_D(_MMIO(0x12054), D_ALL);
2679 MMIO_D(_MMIO(0x22054), D_ALL);
2680 MMIO_D(_MMIO(0x1a054), D_ALL);
2681
2682 MMIO_D(_MMIO(0x44070), D_ALL);
2683 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2684 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2685 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2686 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2687 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2688
2689 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2690 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2691 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2692 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2693 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2694 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2695
2696 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2697 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2698 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2699
2700 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2701 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2702 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2703 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2704 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2705 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2706 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2707 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2708 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2709 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2710 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2711 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2712 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2713 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2714 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2715 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2716 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2717
2718 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2719 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
2720 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2721 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2722 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2723 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2724 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2725 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2726 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2727 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2728 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2729
2730 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2731 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2732 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2733
2734 return 0;
2735 }
2736
2737 static int init_bdw_mmio_info(struct intel_gvt *gvt)
2738 {
2739 struct drm_i915_private *dev_priv = gvt->gt->i915;
2740 int ret;
2741
2742 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2743 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2744 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2745 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2746
2747 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2748 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2749 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2750 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2751
2752 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2753 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2754 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2755 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2756
2757 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2758 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2759 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2760 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2761
2762 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2763 intel_vgpu_reg_imr_handler);
2764 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2765 intel_vgpu_reg_ier_handler);
2766 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2767 intel_vgpu_reg_iir_handler);
2768 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2769
2770 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2771 intel_vgpu_reg_imr_handler);
2772 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2773 intel_vgpu_reg_ier_handler);
2774 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2775 intel_vgpu_reg_iir_handler);
2776 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2777
2778 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2779 intel_vgpu_reg_imr_handler);
2780 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2781 intel_vgpu_reg_ier_handler);
2782 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2783 intel_vgpu_reg_iir_handler);
2784 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2785
2786 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2787 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2788 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2789 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2790
2791 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2792 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2793 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2794 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2795
2796 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2797 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2798 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2799 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2800
2801 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2802 intel_vgpu_reg_master_irq_handler);
2803
2804 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
2805 mmio_read_from_hw, NULL);
2806
2807 #define RING_REG(base) _MMIO((base) + 0xd0)
2808 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2809 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2810 ring_reset_ctl_write);
2811 #undef RING_REG
2812
2813 #define RING_REG(base) _MMIO((base) + 0x230)
2814 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2815 #undef RING_REG
2816
2817 #define RING_REG(base) _MMIO((base) + 0x234)
2818 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
2819 NULL, NULL);
2820 #undef RING_REG
2821
2822 #define RING_REG(base) _MMIO((base) + 0x244)
2823 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2824 #undef RING_REG
2825
2826 #define RING_REG(base) _MMIO((base) + 0x370)
2827 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2828 #undef RING_REG
2829
2830 #define RING_REG(base) _MMIO((base) + 0x3a0)
2831 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2832 #undef RING_REG
2833
2834 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2835 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2836 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2837 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
2838 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2839 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2840 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
2841
2842 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2843
2844 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
2845 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2846
2847 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2848
2849 #define RING_REG(base) _MMIO((base) + 0x270)
2850 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2851 #undef RING_REG
2852
2853 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2854
2855 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2856
2857 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2858 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2859 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2860
2861 MMIO_D(WM_MISC, D_BDW);
2862 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
2863
2864 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
2865 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2866 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
2867
2868 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2869
2870 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2871 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2872 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2873
2874 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
2875 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2876 NULL, NULL);
2877 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2878 NULL, NULL);
2879 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2880
2881 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2882 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2883 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2884 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2885 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2886 MMIO_D(_MMIO(0xb110), D_BDW);
2887
2888 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2889 NULL, force_nonpriv_write);
2890
2891 MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2892 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
2893
2894 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2895 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2896
2897 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2898
2899 MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
2900
2901 MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
2902
2903 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2904 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
2905
2906 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2907 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2908 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2909 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2910
2911 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2912
2913 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2914 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2915 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2916 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2917 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2918 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2919 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2920 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2921 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2922 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2923 return 0;
2924 }
2925
2926 static int init_skl_mmio_info(struct intel_gvt *gvt)
2927 {
2928 struct drm_i915_private *dev_priv = gvt->gt->i915;
2929 int ret;
2930
2931 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2932 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2933 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2934 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
2935 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2936 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2937
2938 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2939 dp_aux_ch_ctl_mmio_write);
2940 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2941 dp_aux_ch_ctl_mmio_write);
2942 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2943 dp_aux_ch_ctl_mmio_write);
2944
2945 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2946 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2947
2948 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2949
2950 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
2951 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2952 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2953 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2954 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2955 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2956 MMIO_D(DC_STATE_EN, D_SKL_PLUS);
2957 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
2958 MMIO_D(CDCLK_CTL, D_SKL_PLUS);
2959 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2960 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2961 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
2962 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
2963 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
2964 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
2965 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
2966 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
2967 MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
2968 MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
2969 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
2970
2971 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2972 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2973 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2974 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2975 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2976 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2977
2978 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2979 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2980 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2981 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2982 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2983 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2984
2985 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2986 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2987 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2988 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2989 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2990 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2991
2992 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2993 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2994 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2995 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2996
2997 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2998 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2999 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
3000 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
3001
3002 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3003 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3004 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3005 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
3006
3007 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
3008 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
3009 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
3010
3011 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3012 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3013 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3014
3015 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3016 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3017 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3018
3019 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3020 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3021 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3022
3023 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3024 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3025 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
3026
3027 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
3028 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
3029 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
3030
3031 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
3032 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
3033 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
3034
3035 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3036 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3037 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3038
3039 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
3040 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
3041 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
3042
3043 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
3044 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
3045 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
3046 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
3047
3048 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
3049 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
3050 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
3051 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
3052
3053 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3054 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3055 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3056 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
3057
3058 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3059 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3060 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3061 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
3062
3063 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3064 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3065 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3066 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
3067
3068 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3069 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3070 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3071 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
3072
3073 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3074 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3075 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3076 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
3077
3078 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3079 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3080 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3081 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
3082
3083 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3084 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3085 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3086 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
3087
3088 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
3089 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
3090 MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
3091 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
3092 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
3093 MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
3094
3095 MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
3096 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
3097 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
3098
3099 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3100
3101 MMIO_D(SKL_DFSM, D_SKL_PLUS);
3102 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
3103
3104 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
3105 NULL, NULL);
3106 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
3107 NULL, NULL);
3108
3109 MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
3110 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
3111 MMIO_D(RC6_LOCATION, D_SKL_PLUS);
3112 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
3113 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
3114 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3115 NULL, NULL);
3116
3117 /* TRTT */
3118 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3119 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3120 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3121 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3122 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3123 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
3124 NULL, gen9_trtte_write);
3125 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
3126 NULL, gen9_trtt_chicken_write);
3127
3128 MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
3129
3130 MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
3131
3132 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
3133 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3134 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
3135
3136 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
3137 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
3138 MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
3139 MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
3140 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
3141 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
3142 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
3143 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
3144 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
3145 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
3146
3147 MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
3148 MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
3149 MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
3150
3151 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
3152 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
3153 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
3154 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
3155 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
3156 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
3157 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
3158 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
3159 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
3160
3161 MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
3162 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
3163 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3164 NULL, csfe_chicken1_mmio_write);
3165 #undef CSFE_CHICKEN1_REG
3166 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3167 NULL, NULL);
3168 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3169 NULL, NULL);
3170
3171 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
3172 MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
3173
3174 return 0;
3175 }
3176
3177 static int init_bxt_mmio_info(struct intel_gvt *gvt)
3178 {
3179 struct drm_i915_private *dev_priv = gvt->gt->i915;
3180 int ret;
3181
3182 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
3183
3184 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
3185 MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
3186 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
3187 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
3188 MMIO_D(ERROR_GEN6, D_BXT);
3189 MMIO_D(DONE_REG, D_BXT);
3190 MMIO_D(EIR, D_BXT);
3191 MMIO_D(PGTBL_ER, D_BXT);
3192 MMIO_D(_MMIO(0x4194), D_BXT);
3193 MMIO_D(_MMIO(0x4294), D_BXT);
3194 MMIO_D(_MMIO(0x4494), D_BXT);
3195
3196 MMIO_RING_D(RING_PSMI_CTL, D_BXT);
3197 MMIO_RING_D(RING_DMA_FADD, D_BXT);
3198 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
3199 MMIO_RING_D(RING_IPEHR, D_BXT);
3200 MMIO_RING_D(RING_INSTPS, D_BXT);
3201 MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
3202 MMIO_RING_D(RING_BBSTATE, D_BXT);
3203 MMIO_RING_D(RING_IPEIR, D_BXT);
3204
3205 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
3206
3207 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
3208 MMIO_D(BXT_RP_STATE_CAP, D_BXT);
3209 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
3210 NULL, bxt_phy_ctl_family_write);
3211 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
3212 NULL, bxt_phy_ctl_family_write);
3213 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
3214 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
3215 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
3216 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
3217 NULL, bxt_port_pll_enable_write);
3218 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
3219 NULL, bxt_port_pll_enable_write);
3220 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
3221 bxt_port_pll_enable_write);
3222
3223 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
3224 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
3225 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
3226 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
3227 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
3228 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
3229 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
3230 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
3231 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
3232
3233 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
3234 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
3235 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
3236 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
3237 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
3238 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
3239 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
3240 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
3241 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
3242
3243 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
3244 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
3245 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3246 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3247 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3248 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
3249 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
3250 NULL, bxt_pcs_dw12_grp_write);
3251 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3252 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3253 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
3254 bxt_port_tx_dw3_read, NULL);
3255 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3256 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3257 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3258 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3259 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3260 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3261 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3262 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3263 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3264 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3265 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3266 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
3267 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
3268 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
3269 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
3270
3271 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
3272 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
3273 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3274 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3275 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3276 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
3277 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
3278 NULL, bxt_pcs_dw12_grp_write);
3279 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3280 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3281 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
3282 bxt_port_tx_dw3_read, NULL);
3283 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3284 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3285 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3286 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3287 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3288 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3289 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3290 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3291 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3292 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3293 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3294 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
3295 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
3296 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
3297 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
3298
3299 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
3300 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
3301 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3302 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3303 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3304 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
3305 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
3306 NULL, bxt_pcs_dw12_grp_write);
3307 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3308 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3309 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
3310 bxt_port_tx_dw3_read, NULL);
3311 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3312 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3313 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3314 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3315 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3316 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3317 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3318 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3319 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3320 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3321 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3322 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
3323 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
3324 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
3325 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
3326
3327 MMIO_D(BXT_DE_PLL_CTL, D_BXT);
3328 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
3329 MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
3330 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
3331
3332 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
3333 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
3334
3335 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3336 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3337 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3338
3339 MMIO_D(RC6_CTX_BASE, D_BXT);
3340
3341 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
3342 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
3343 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3344 MMIO_D(GEN6_GFXPAUSE, D_BXT);
3345 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
3346 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3347 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
3348 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
3349 0, 0, D_BXT, NULL, NULL);
3350 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
3351 0, 0, D_BXT, NULL, NULL);
3352 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
3353 0, 0, D_BXT, NULL, NULL);
3354 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
3355 0, 0, D_BXT, NULL, NULL);
3356
3357 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3358
3359 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
3360
3361 return 0;
3362 }
3363
3364 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3365 unsigned int offset)
3366 {
3367 unsigned long device = intel_gvt_get_device_type(gvt);
3368 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3369 int num = gvt->mmio.num_mmio_block;
3370 int i;
3371
3372 for (i = 0; i < num; i++, block++) {
3373 if (!(device & block->device))
3374 continue;
3375 if (offset >= i915_mmio_reg_offset(block->offset) &&
3376 offset < i915_mmio_reg_offset(block->offset) + block->size)
3377 return block;
3378 }
3379 return NULL;
3380 }
3381
3382 /**
3383 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
3384 * @gvt: GVT device
3385 *
3386 * This function is called at the driver unloading stage, to clean up the MMIO
3387 * information table of GVT device
3388 *
3389 */
3390 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
3391 {
3392 struct hlist_node *tmp;
3393 struct intel_gvt_mmio_info *e;
3394 int i;
3395
3396 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
3397 kfree(e);
3398
3399 vfree(gvt->mmio.mmio_attribute);
3400 gvt->mmio.mmio_attribute = NULL;
3401 }
3402
3403 /* Special MMIO blocks. registers in MMIO block ranges should not be command
3404 * accessible (should have no F_CMD_ACCESS flag).
3405 * otherwise, need to update cmd_reg_handler in cmd_parser.c
3406 */
3407 static struct gvt_mmio_block mmio_blocks[] = {
3408 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
3409 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
3410 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
3411 pvinfo_mmio_read, pvinfo_mmio_write},
3412 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
3413 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
3414 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
3415 };
3416
3417 /**
3418 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
3419 * @gvt: GVT device
3420 *
3421 * This function is called at the initialization stage, to setup the MMIO
3422 * information table for GVT device
3423 *
3424 * Returns:
3425 * zero on success, negative if failed.
3426 */
3427 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
3428 {
3429 struct intel_gvt_device_info *info = &gvt->device_info;
3430 struct drm_i915_private *i915 = gvt->gt->i915;
3431 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
3432 int ret;
3433
3434 gvt->mmio.mmio_attribute = vzalloc(size);
3435 if (!gvt->mmio.mmio_attribute)
3436 return -ENOMEM;
3437
3438 ret = init_generic_mmio_info(gvt);
3439 if (ret)
3440 goto err;
3441
3442 if (IS_BROADWELL(i915)) {
3443 ret = init_bdw_mmio_info(gvt);
3444 if (ret)
3445 goto err;
3446 } else if (IS_SKYLAKE(i915) ||
3447 IS_KABYLAKE(i915) ||
3448 IS_COFFEELAKE(i915) ||
3449 IS_COMETLAKE(i915)) {
3450 ret = init_bdw_mmio_info(gvt);
3451 if (ret)
3452 goto err;
3453 ret = init_skl_mmio_info(gvt);
3454 if (ret)
3455 goto err;
3456 } else if (IS_BROXTON(i915)) {
3457 ret = init_bdw_mmio_info(gvt);
3458 if (ret)
3459 goto err;
3460 ret = init_skl_mmio_info(gvt);
3461 if (ret)
3462 goto err;
3463 ret = init_bxt_mmio_info(gvt);
3464 if (ret)
3465 goto err;
3466 }
3467
3468 gvt->mmio.mmio_block = mmio_blocks;
3469 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
3470
3471 return 0;
3472 err:
3473 intel_gvt_clean_mmio_info(gvt);
3474 return ret;
3475 }
3476
3477 /**
3478 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3479 * @gvt: a GVT device
3480 * @handler: the handler
3481 * @data: private data given to handler
3482 *
3483 * Returns:
3484 * Zero on success, negative error code if failed.
3485 */
3486 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3487 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3488 void *data)
3489 {
3490 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3491 struct intel_gvt_mmio_info *e;
3492 int i, j, ret;
3493
3494 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3495 ret = handler(gvt, e->offset, data);
3496 if (ret)
3497 return ret;
3498 }
3499
3500 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3501 /* pvinfo data doesn't come from hw mmio */
3502 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3503 continue;
3504
3505 for (j = 0; j < block->size; j += 4) {
3506 ret = handler(gvt,
3507 i915_mmio_reg_offset(block->offset) + j,
3508 data);
3509 if (ret)
3510 return ret;
3511 }
3512 }
3513 return 0;
3514 }
3515
3516 /**
3517 * intel_vgpu_default_mmio_read - default MMIO read handler
3518 * @vgpu: a vGPU
3519 * @offset: access offset
3520 * @p_data: data return buffer
3521 * @bytes: access data length
3522 *
3523 * Returns:
3524 * Zero on success, negative error code if failed.
3525 */
3526 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3527 void *p_data, unsigned int bytes)
3528 {
3529 read_vreg(vgpu, offset, p_data, bytes);
3530 return 0;
3531 }
3532
3533 /**
3534 * intel_t_default_mmio_write - default MMIO write handler
3535 * @vgpu: a vGPU
3536 * @offset: access offset
3537 * @p_data: write data buffer
3538 * @bytes: access data length
3539 *
3540 * Returns:
3541 * Zero on success, negative error code if failed.
3542 */
3543 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3544 void *p_data, unsigned int bytes)
3545 {
3546 write_vreg(vgpu, offset, p_data, bytes);
3547 return 0;
3548 }
3549
3550 /**
3551 * intel_vgpu_mask_mmio_write - write mask register
3552 * @vgpu: a vGPU
3553 * @offset: access offset
3554 * @p_data: write data buffer
3555 * @bytes: access data length
3556 *
3557 * Returns:
3558 * Zero on success, negative error code if failed.
3559 */
3560 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3561 void *p_data, unsigned int bytes)
3562 {
3563 u32 mask, old_vreg;
3564
3565 old_vreg = vgpu_vreg(vgpu, offset);
3566 write_vreg(vgpu, offset, p_data, bytes);
3567 mask = vgpu_vreg(vgpu, offset) >> 16;
3568 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3569 (vgpu_vreg(vgpu, offset) & mask);
3570
3571 return 0;
3572 }
3573
3574 /**
3575 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3576 * force-nopriv register
3577 *
3578 * @gvt: a GVT device
3579 * @offset: register offset
3580 *
3581 * Returns:
3582 * True if the register is in force-nonpriv whitelist;
3583 * False if outside;
3584 */
3585 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3586 unsigned int offset)
3587 {
3588 return in_whitelist(offset);
3589 }
3590
3591 /**
3592 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3593 * @vgpu: a vGPU
3594 * @offset: register offset
3595 * @pdata: data buffer
3596 * @bytes: data length
3597 * @is_read: read or write
3598 *
3599 * Returns:
3600 * Zero on success, negative error code if failed.
3601 */
3602 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3603 void *pdata, unsigned int bytes, bool is_read)
3604 {
3605 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
3606 struct intel_gvt *gvt = vgpu->gvt;
3607 struct intel_gvt_mmio_info *mmio_info;
3608 struct gvt_mmio_block *mmio_block;
3609 gvt_mmio_func func;
3610 int ret;
3611
3612 if (drm_WARN_ON(&i915->drm, bytes > 8))
3613 return -EINVAL;
3614
3615 /*
3616 * Handle special MMIO blocks.
3617 */
3618 mmio_block = find_mmio_block(gvt, offset);
3619 if (mmio_block) {
3620 func = is_read ? mmio_block->read : mmio_block->write;
3621 if (func)
3622 return func(vgpu, offset, pdata, bytes);
3623 goto default_rw;
3624 }
3625
3626 /*
3627 * Normal tracked MMIOs.
3628 */
3629 mmio_info = find_mmio_info(gvt, offset);
3630 if (!mmio_info) {
3631 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3632 goto default_rw;
3633 }
3634
3635 if (is_read)
3636 return mmio_info->read(vgpu, offset, pdata, bytes);
3637 else {
3638 u64 ro_mask = mmio_info->ro_mask;
3639 u32 old_vreg = 0;
3640 u64 data = 0;
3641
3642 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3643 old_vreg = vgpu_vreg(vgpu, offset);
3644 }
3645
3646 if (likely(!ro_mask))
3647 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3648 else if (!~ro_mask) {
3649 gvt_vgpu_err("try to write RO reg %x\n", offset);
3650 return 0;
3651 } else {
3652 /* keep the RO bits in the virtual register */
3653 memcpy(&data, pdata, bytes);
3654 data &= ~ro_mask;
3655 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3656 ret = mmio_info->write(vgpu, offset, &data, bytes);
3657 }
3658
3659 /* higher 16bits of mode ctl regs are mask bits for change */
3660 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3661 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3662
3663 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3664 | (vgpu_vreg(vgpu, offset) & mask);
3665 }
3666 }
3667
3668 return ret;
3669
3670 default_rw:
3671 return is_read ?
3672 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3673 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3674 }
3675
3676 void intel_gvt_restore_fence(struct intel_gvt *gvt)
3677 {
3678 struct intel_vgpu *vgpu;
3679 int i, id;
3680
3681 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3682 mmio_hw_access_pre(gvt->gt);
3683 for (i = 0; i < vgpu_fence_sz(vgpu); i++)
3684 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i)));
3685 mmio_hw_access_post(gvt->gt);
3686 }
3687 }
3688
3689 static inline int mmio_pm_restore_handler(struct intel_gvt *gvt,
3690 u32 offset, void *data)
3691 {
3692 struct intel_vgpu *vgpu = data;
3693 struct drm_i915_private *dev_priv = gvt->gt->i915;
3694
3695 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE)
3696 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
3697
3698 return 0;
3699 }
3700
3701 void intel_gvt_restore_mmio(struct intel_gvt *gvt)
3702 {
3703 struct intel_vgpu *vgpu;
3704 int id;
3705
3706 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3707 mmio_hw_access_pre(gvt->gt);
3708 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu);
3709 mmio_hw_access_post(gvt->gt);
3710 }
3711 }
Linux with added FPC-III support