drivers/gpu/drm/i915/gvt/mmio.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Dexuan Cui
  27  *
  28  * Contributors:
  29  *    Tina Zhang <tina.zhang@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Niu Bing <bing.niu@intel.com>
  32  *    Zhi Wang <zhi.a.wang@intel.com>
  33  *
  34  */
  35
  36 #include "i915_drv.h"
  37 #include "gvt.h"
  38
  39 /**
  40  * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
  41  * @vgpu: a vGPU
  42  * @gpa: guest physical address
  43  *
  44  * Returns:
  45  * Zero on success, negative error code if failed
  46  */
  47 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
  48 {
  49         u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
  50         return gpa - gttmmio_gpa;
  51 }
  52
  53 #define reg_is_mmio(gvt, reg)  \
  54         (reg >= 0 && reg < gvt->device_info.mmio_size)
  55
  56 #define reg_is_gtt(gvt, reg)   \
  57         (reg >= gvt->device_info.gtt_start_offset \
  58          && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
  59
  60 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
  61                 void *p_data, unsigned int bytes, bool read)
  62 {
  63         struct intel_gvt *gvt = NULL;
  64         void *pt = NULL;
  65         unsigned int offset = 0;
  66
  67         if (!vgpu || !p_data)
  68                 return;
  69
  70         gvt = vgpu->gvt;
  71         mutex_lock(&vgpu->vgpu_lock);
  72         offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
  73         if (reg_is_mmio(gvt, offset)) {
  74                 if (read)
  75                         intel_vgpu_default_mmio_read(vgpu, offset, p_data,
  76                                         bytes);
  77                 else
  78                         intel_vgpu_default_mmio_write(vgpu, offset, p_data,
  79                                         bytes);
  80         } else if (reg_is_gtt(gvt, offset)) {
  81                 offset -= gvt->device_info.gtt_start_offset;
  82                 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
  83                 if (read)
  84                         memcpy(p_data, pt, bytes);
  85                 else
  86                         memcpy(pt, p_data, bytes);
  87
  88         }
  89         mutex_unlock(&vgpu->vgpu_lock);
  90 }
  91
  92 /**
  93  * intel_vgpu_emulate_mmio_read - emulate MMIO read
  94  * @vgpu: a vGPU
  95  * @pa: guest physical address
  96  * @p_data: data return buffer
  97  * @bytes: access data length
  98  *
  99  * Returns:
 100  * Zero on success, negative error code if failed
 101  */
 102 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
 103                 void *p_data, unsigned int bytes)
 104 {
 105         struct intel_gvt *gvt = vgpu->gvt;
 106         struct drm_i915_private *i915 = gvt->gt->i915;
 107         unsigned int offset = 0;
 108         int ret = -EINVAL;
 109
 110         if (vgpu->failsafe) {
 111                 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
 112                 return 0;
 113         }
 114         mutex_lock(&vgpu->vgpu_lock);
 115
 116         offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
 117
 118         if (drm_WARN_ON(&i915->drm, bytes > 8))
 119                 goto err;
 120
 121         if (reg_is_gtt(gvt, offset)) {
 122                 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
 123                                 !IS_ALIGNED(offset, 8)))
 124                         goto err;
 125                 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
 126                         goto err;
 127                 if (drm_WARN_ON(&i915->drm,
 128                                 !reg_is_gtt(gvt, offset + bytes - 1)))
 129                         goto err;
 130
 131                 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
 132                                 p_data, bytes);
 133                 if (ret)
 134                         goto err;
 135                 goto out;
 136         }
 137
 138         if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
 139                 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
 140                 goto out;
 141         }
 142
 143         if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))
 144                 goto err;
 145
 146         if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
 147                 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))
 148                         goto err;
 149         }
 150
 151         ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
 152         if (ret < 0)
 153                 goto err;
 154
 155         intel_gvt_mmio_set_accessed(gvt, offset);
 156         ret = 0;
 157         goto out;
 158
 159 err:
 160         gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
 161                         offset, bytes);
 162 out:
 163         mutex_unlock(&vgpu->vgpu_lock);
 164         return ret;
 165 }
 166
 167 /**
 168  * intel_vgpu_emulate_mmio_write - emulate MMIO write
 169  * @vgpu: a vGPU
 170  * @pa: guest physical address
 171  * @p_data: write data buffer
 172  * @bytes: access data length
 173  *
 174  * Returns:
 175  * Zero on success, negative error code if failed
 176  */
 177 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
 178                 void *p_data, unsigned int bytes)
 179 {
 180         struct intel_gvt *gvt = vgpu->gvt;
 181         struct drm_i915_private *i915 = gvt->gt->i915;
 182         unsigned int offset = 0;
 183         int ret = -EINVAL;
 184
 185         if (vgpu->failsafe) {
 186                 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
 187                 return 0;
 188         }
 189
 190         mutex_lock(&vgpu->vgpu_lock);
 191
 192         offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
 193
 194         if (drm_WARN_ON(&i915->drm, bytes > 8))
 195                 goto err;
 196
 197         if (reg_is_gtt(gvt, offset)) {
 198                 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
 199                                 !IS_ALIGNED(offset, 8)))
 200                         goto err;
 201                 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
 202                         goto err;
 203                 if (drm_WARN_ON(&i915->drm,
 204                                 !reg_is_gtt(gvt, offset + bytes - 1)))
 205                         goto err;
 206
 207                 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
 208                                 p_data, bytes);
 209                 if (ret)
 210                         goto err;
 211                 goto out;
 212         }
 213
 214         if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
 215                 ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
 216                 goto out;
 217         }
 218
 219         ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
 220         if (ret < 0)
 221                 goto err;
 222
 223         intel_gvt_mmio_set_accessed(gvt, offset);
 224         ret = 0;
 225         goto out;
 226 err:
 227         gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
 228                      bytes);
 229 out:
 230         mutex_unlock(&vgpu->vgpu_lock);
 231         return ret;
 232 }
 233
 234
 235 /**
 236  * intel_vgpu_reset_mmio - reset virtual MMIO space
 237  * @vgpu: a vGPU
 238  * @dmlr: whether this is device model level reset
 239  */
 240 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
 241 {
 242         struct intel_gvt *gvt = vgpu->gvt;
 243         const struct intel_gvt_device_info *info = &gvt->device_info;
 244         void  *mmio = gvt->firmware.mmio;
 245
 246         if (dmlr) {
 247                 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
 248
 249                 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
 250
 251                 /* set the bit 0:2(Core C-State ) to C0 */
 252                 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
 253
 254                 /* uc reset hw expect GS_MIA_IN_RESET */
 255                 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
 256
 257                 if (IS_BROXTON(vgpu->gvt->gt->i915)) {
 258                         vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
 259                                     ~(BIT(0) | BIT(1));
 260                         vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
 261                                     ~PHY_POWER_GOOD;
 262                         vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
 263                                     ~PHY_POWER_GOOD;
 264                         vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
 265                                     ~BIT(30);
 266                         vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
 267                                     ~BIT(30);
 268                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
 269                                     ~BXT_PHY_LANE_ENABLED;
 270                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
 271                                     BXT_PHY_CMNLANE_POWERDOWN_ACK |
 272                                     BXT_PHY_LANE_POWERDOWN_ACK;
 273                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
 274                                     ~BXT_PHY_LANE_ENABLED;
 275                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
 276                                     BXT_PHY_CMNLANE_POWERDOWN_ACK |
 277                                     BXT_PHY_LANE_POWERDOWN_ACK;
 278                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
 279                                     ~BXT_PHY_LANE_ENABLED;
 280                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
 281                                     BXT_PHY_CMNLANE_POWERDOWN_ACK |
 282                                     BXT_PHY_LANE_POWERDOWN_ACK;
 283                         vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
 284                                 SKL_FUSE_DOWNLOAD_STATUS |
 285                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
 286                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
 287                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
 288                 }
 289         } else {
 290 #define GVT_GEN8_MMIO_RESET_OFFSET              (0x44200)
 291                 /* only reset the engine related, so starting with 0x44200
 292                  * interrupt include DE,display mmio related will not be
 293                  * touched
 294                  */
 295                 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
 296         }
 297
 298 }
 299
 300 /**
 301  * intel_vgpu_init_mmio - init MMIO  space
 302  * @vgpu: a vGPU
 303  *
 304  * Returns:
 305  * Zero on success, negative error code if failed
 306  */
 307 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
 308 {
 309         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
 310
 311         vgpu->mmio.vreg = vzalloc(info->mmio_size);
 312         if (!vgpu->mmio.vreg)
 313                 return -ENOMEM;
 314
 315         intel_vgpu_reset_mmio(vgpu, true);
 316
 317         return 0;
 318 }
 319
 320 /**
 321  * intel_vgpu_clean_mmio - clean MMIO space
 322  * @vgpu: a vGPU
 323  *
 324  */
 325 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
 326 {
 327         vfree(vgpu->mmio.vreg);
 328         vgpu->mmio.vreg = NULL;
 329 }