drivers/gpu/drm/imx/imx-tve.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * i.MX drm driver - Television Encoder (TVEv2)
   4  *
   5  * Copyright (C) 2013 Philipp Zabel, Pengutronix
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/i2c.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/videodev2.h>
  17
  18 #include <video/imx-ipu-v3.h>
  19
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_fb_helper.h>
  22 #include <drm/drm_probe_helper.h>
  23 #include <drm/drm_simple_kms_helper.h>
  24
  25 #include "imx-drm.h"
  26
  27 #define TVE_COM_CONF_REG        0x00
  28 #define TVE_TVDAC0_CONT_REG     0x28
  29 #define TVE_TVDAC1_CONT_REG     0x2c
  30 #define TVE_TVDAC2_CONT_REG     0x30
  31 #define TVE_CD_CONT_REG         0x34
  32 #define TVE_INT_CONT_REG        0x64
  33 #define TVE_STAT_REG            0x68
  34 #define TVE_TST_MODE_REG        0x6c
  35 #define TVE_MV_CONT_REG         0xdc
  36
  37 /* TVE_COM_CONF_REG */
  38 #define TVE_SYNC_CH_2_EN        BIT(22)
  39 #define TVE_SYNC_CH_1_EN        BIT(21)
  40 #define TVE_SYNC_CH_0_EN        BIT(20)
  41 #define TVE_TV_OUT_MODE_MASK    (0x7 << 12)
  42 #define TVE_TV_OUT_DISABLE      (0x0 << 12)
  43 #define TVE_TV_OUT_CVBS_0       (0x1 << 12)
  44 #define TVE_TV_OUT_CVBS_2       (0x2 << 12)
  45 #define TVE_TV_OUT_CVBS_0_2     (0x3 << 12)
  46 #define TVE_TV_OUT_SVIDEO_0_1   (0x4 << 12)
  47 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2   (0x5 << 12)
  48 #define TVE_TV_OUT_YPBPR        (0x6 << 12)
  49 #define TVE_TV_OUT_RGB          (0x7 << 12)
  50 #define TVE_TV_STAND_MASK       (0xf << 8)
  51 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
  52 #define TVE_P2I_CONV_EN         BIT(7)
  53 #define TVE_INP_VIDEO_FORM      BIT(6)
  54 #define TVE_INP_YCBCR_422       (0x0 << 6)
  55 #define TVE_INP_YCBCR_444       (0x1 << 6)
  56 #define TVE_DATA_SOURCE_MASK    (0x3 << 4)
  57 #define TVE_DATA_SOURCE_BUS1    (0x0 << 4)
  58 #define TVE_DATA_SOURCE_BUS2    (0x1 << 4)
  59 #define TVE_DATA_SOURCE_EXT     (0x2 << 4)
  60 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
  61 #define TVE_IPU_CLK_EN_OFS      3
  62 #define TVE_IPU_CLK_EN          BIT(3)
  63 #define TVE_DAC_SAMP_RATE_OFS   1
  64 #define TVE_DAC_SAMP_RATE_WIDTH 2
  65 #define TVE_DAC_SAMP_RATE_MASK  (0x3 << 1)
  66 #define TVE_DAC_FULL_RATE       (0x0 << 1)
  67 #define TVE_DAC_DIV2_RATE       (0x1 << 1)
  68 #define TVE_DAC_DIV4_RATE       (0x2 << 1)
  69 #define TVE_EN                  BIT(0)
  70
  71 /* TVE_TVDACx_CONT_REG */
  72 #define TVE_TVDAC_GAIN_MASK     (0x3f << 0)
  73
  74 /* TVE_CD_CONT_REG */
  75 #define TVE_CD_CH_2_SM_EN       BIT(22)
  76 #define TVE_CD_CH_1_SM_EN       BIT(21)
  77 #define TVE_CD_CH_0_SM_EN       BIT(20)
  78 #define TVE_CD_CH_2_LM_EN       BIT(18)
  79 #define TVE_CD_CH_1_LM_EN       BIT(17)
  80 #define TVE_CD_CH_0_LM_EN       BIT(16)
  81 #define TVE_CD_CH_2_REF_LVL     BIT(10)
  82 #define TVE_CD_CH_1_REF_LVL     BIT(9)
  83 #define TVE_CD_CH_0_REF_LVL     BIT(8)
  84 #define TVE_CD_EN               BIT(0)
  85
  86 /* TVE_INT_CONT_REG */
  87 #define TVE_FRAME_END_IEN       BIT(13)
  88 #define TVE_CD_MON_END_IEN      BIT(2)
  89 #define TVE_CD_SM_IEN           BIT(1)
  90 #define TVE_CD_LM_IEN           BIT(0)
  91
  92 /* TVE_TST_MODE_REG */
  93 #define TVE_TVDAC_TEST_MODE_MASK        (0x7 << 0)
  94
  95 #define IMX_TVE_DAC_VOLTAGE     2750000
  96
  97 enum {
  98         TVE_MODE_TVOUT,
  99         TVE_MODE_VGA,
 100 };
 101
 102 struct imx_tve {
 103         struct drm_connector connector;
 104         struct drm_encoder encoder;
 105         struct device *dev;
 106         int mode;
 107         int di_hsync_pin;
 108         int di_vsync_pin;
 109
 110         struct regmap *regmap;
 111         struct regulator *dac_reg;
 112         struct i2c_adapter *ddc;
 113         struct clk *clk;
 114         struct clk *di_sel_clk;
 115         struct clk_hw clk_hw_di;
 116         struct clk *di_clk;
 117 };
 118
 119 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
 120 {
 121         return container_of(c, struct imx_tve, connector);
 122 }
 123
 124 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
 125 {
 126         return container_of(e, struct imx_tve, encoder);
 127 }
 128
 129 static void tve_enable(struct imx_tve *tve)
 130 {
 131         clk_prepare_enable(tve->clk);
 132         regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
 133
 134         /* clear interrupt status register */
 135         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
 136
 137         /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
 138         if (tve->mode == TVE_MODE_VGA)
 139                 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
 140         else
 141                 regmap_write(tve->regmap, TVE_INT_CONT_REG,
 142                              TVE_CD_SM_IEN |
 143                              TVE_CD_LM_IEN |
 144                              TVE_CD_MON_END_IEN);
 145 }
 146
 147 static void tve_disable(struct imx_tve *tve)
 148 {
 149         regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
 150         clk_disable_unprepare(tve->clk);
 151 }
 152
 153 static int tve_setup_tvout(struct imx_tve *tve)
 154 {
 155         return -ENOTSUPP;
 156 }
 157
 158 static int tve_setup_vga(struct imx_tve *tve)
 159 {
 160         unsigned int mask;
 161         unsigned int val;
 162         int ret;
 163
 164         /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
 165         ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
 166                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 167         if (ret)
 168                 return ret;
 169
 170         ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
 171                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 172         if (ret)
 173                 return ret;
 174
 175         ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
 176                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 177         if (ret)
 178                 return ret;
 179
 180         /* set configuration register */
 181         mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
 182         val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
 183         mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
 184         val  |= TVE_TV_STAND_HD_1080P30 | 0;
 185         mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
 186         val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
 187         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
 188         if (ret)
 189                 return ret;
 190
 191         /* set test mode (as documented) */
 192         return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
 193                                  TVE_TVDAC_TEST_MODE_MASK, 1);
 194 }
 195
 196 static int imx_tve_connector_get_modes(struct drm_connector *connector)
 197 {
 198         struct imx_tve *tve = con_to_tve(connector);
 199         struct edid *edid;
 200         int ret = 0;
 201
 202         if (!tve->ddc)
 203                 return 0;
 204
 205         edid = drm_get_edid(connector, tve->ddc);
 206         if (edid) {
 207                 drm_connector_update_edid_property(connector, edid);
 208                 ret = drm_add_edid_modes(connector, edid);
 209                 kfree(edid);
 210         }
 211
 212         return ret;
 213 }
 214
 215 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
 216                                         struct drm_display_mode *mode)
 217 {
 218         struct imx_tve *tve = con_to_tve(connector);
 219         unsigned long rate;
 220
 221         /* pixel clock with 2x oversampling */
 222         rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
 223         if (rate == mode->clock)
 224                 return MODE_OK;
 225
 226         /* pixel clock without oversampling */
 227         rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
 228         if (rate == mode->clock)
 229                 return MODE_OK;
 230
 231         dev_warn(tve->dev, "ignoring mode %dx%d\n",
 232                  mode->hdisplay, mode->vdisplay);
 233
 234         return MODE_BAD;
 235 }
 236
 237 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
 238                                      struct drm_display_mode *orig_mode,
 239                                      struct drm_display_mode *mode)
 240 {
 241         struct imx_tve *tve = enc_to_tve(encoder);
 242         unsigned long rounded_rate;
 243         unsigned long rate;
 244         int div = 1;
 245         int ret;
 246
 247         /*
 248          * FIXME
 249          * we should try 4k * mode->clock first,
 250          * and enable 4x oversampling for lower resolutions
 251          */
 252         rate = 2000UL * mode->clock;
 253         clk_set_rate(tve->clk, rate);
 254         rounded_rate = clk_get_rate(tve->clk);
 255         if (rounded_rate >= rate)
 256                 div = 2;
 257         clk_set_rate(tve->di_clk, rounded_rate / div);
 258
 259         ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
 260         if (ret < 0) {
 261                 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
 262                         ret);
 263         }
 264
 265         regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 266                            TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
 267
 268         if (tve->mode == TVE_MODE_VGA)
 269                 ret = tve_setup_vga(tve);
 270         else
 271                 ret = tve_setup_tvout(tve);
 272         if (ret)
 273                 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
 274 }
 275
 276 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
 277 {
 278         struct imx_tve *tve = enc_to_tve(encoder);
 279
 280         tve_enable(tve);
 281 }
 282
 283 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
 284 {
 285         struct imx_tve *tve = enc_to_tve(encoder);
 286
 287         tve_disable(tve);
 288 }
 289
 290 static int imx_tve_atomic_check(struct drm_encoder *encoder,
 291                                 struct drm_crtc_state *crtc_state,
 292                                 struct drm_connector_state *conn_state)
 293 {
 294         struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
 295         struct imx_tve *tve = enc_to_tve(encoder);
 296
 297         imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
 298         imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
 299         imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
 300
 301         return 0;
 302 }
 303
 304 static const struct drm_connector_funcs imx_tve_connector_funcs = {
 305         .fill_modes = drm_helper_probe_single_connector_modes,
 306         .destroy = imx_drm_connector_destroy,
 307         .reset = drm_atomic_helper_connector_reset,
 308         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 309         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 310 };
 311
 312 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
 313         .get_modes = imx_tve_connector_get_modes,
 314         .mode_valid = imx_tve_connector_mode_valid,
 315 };
 316
 317 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
 318         .mode_set = imx_tve_encoder_mode_set,
 319         .enable = imx_tve_encoder_enable,
 320         .disable = imx_tve_encoder_disable,
 321         .atomic_check = imx_tve_atomic_check,
 322 };
 323
 324 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
 325 {
 326         struct imx_tve *tve = data;
 327         unsigned int val;
 328
 329         regmap_read(tve->regmap, TVE_STAT_REG, &val);
 330
 331         /* clear interrupt status register */
 332         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
 333
 334         return IRQ_HANDLED;
 335 }
 336
 337 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
 338                                             unsigned long parent_rate)
 339 {
 340         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
 341         unsigned int val;
 342         int ret;
 343
 344         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
 345         if (ret < 0)
 346                 return 0;
 347
 348         switch (val & TVE_DAC_SAMP_RATE_MASK) {
 349         case TVE_DAC_DIV4_RATE:
 350                 return parent_rate / 4;
 351         case TVE_DAC_DIV2_RATE:
 352                 return parent_rate / 2;
 353         case TVE_DAC_FULL_RATE:
 354         default:
 355                 return parent_rate;
 356         }
 357
 358         return 0;
 359 }
 360
 361 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
 362                                   unsigned long *prate)
 363 {
 364         unsigned long div;
 365
 366         div = *prate / rate;
 367         if (div >= 4)
 368                 return *prate / 4;
 369         else if (div >= 2)
 370                 return *prate / 2;
 371         return *prate;
 372 }
 373
 374 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
 375                                unsigned long parent_rate)
 376 {
 377         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
 378         unsigned long div;
 379         u32 val;
 380         int ret;
 381
 382         div = parent_rate / rate;
 383         if (div >= 4)
 384                 val = TVE_DAC_DIV4_RATE;
 385         else if (div >= 2)
 386                 val = TVE_DAC_DIV2_RATE;
 387         else
 388                 val = TVE_DAC_FULL_RATE;
 389
 390         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 391                                  TVE_DAC_SAMP_RATE_MASK, val);
 392
 393         if (ret < 0) {
 394                 dev_err(tve->dev, "failed to set divider: %d\n", ret);
 395                 return ret;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static const struct clk_ops clk_tve_di_ops = {
 402         .round_rate = clk_tve_di_round_rate,
 403         .set_rate = clk_tve_di_set_rate,
 404         .recalc_rate = clk_tve_di_recalc_rate,
 405 };
 406
 407 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
 408 {
 409         const char *tve_di_parent[1];
 410         struct clk_init_data init = {
 411                 .name = "tve_di",
 412                 .ops = &clk_tve_di_ops,
 413                 .num_parents = 1,
 414                 .flags = 0,
 415         };
 416
 417         tve_di_parent[0] = __clk_get_name(tve->clk);
 418         init.parent_names = (const char **)&tve_di_parent;
 419
 420         tve->clk_hw_di.init = &init;
 421         tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
 422         if (IS_ERR(tve->di_clk)) {
 423                 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
 424                         PTR_ERR(tve->di_clk));
 425                 return PTR_ERR(tve->di_clk);
 426         }
 427
 428         return 0;
 429 }
 430
 431 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
 432 {
 433         int encoder_type;
 434         int ret;
 435
 436         encoder_type = tve->mode == TVE_MODE_VGA ?
 437                                 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
 438
 439         ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
 440         if (ret)
 441                 return ret;
 442
 443         drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
 444         drm_simple_encoder_init(drm, &tve->encoder, encoder_type);
 445
 446         drm_connector_helper_add(&tve->connector,
 447                         &imx_tve_connector_helper_funcs);
 448         drm_connector_init_with_ddc(drm, &tve->connector,
 449                                     &imx_tve_connector_funcs,
 450                                     DRM_MODE_CONNECTOR_VGA,
 451                                     tve->ddc);
 452
 453         drm_connector_attach_encoder(&tve->connector, &tve->encoder);
 454
 455         return 0;
 456 }
 457
 458 static void imx_tve_disable_regulator(void *data)
 459 {
 460         struct imx_tve *tve = data;
 461
 462         regulator_disable(tve->dac_reg);
 463 }
 464
 465 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
 466 {
 467         return (reg % 4 == 0) && (reg <= 0xdc);
 468 }
 469
 470 static struct regmap_config tve_regmap_config = {
 471         .reg_bits = 32,
 472         .val_bits = 32,
 473         .reg_stride = 4,
 474
 475         .readable_reg = imx_tve_readable_reg,
 476
 477         .fast_io = true,
 478
 479         .max_register = 0xdc,
 480 };
 481
 482 static const char * const imx_tve_modes[] = {
 483         [TVE_MODE_TVOUT]  = "tvout",
 484         [TVE_MODE_VGA] = "vga",
 485 };
 486
 487 static int of_get_tve_mode(struct device_node *np)
 488 {
 489         const char *bm;
 490         int ret, i;
 491
 492         ret = of_property_read_string(np, "fsl,tve-mode", &bm);
 493         if (ret < 0)
 494                 return ret;
 495
 496         for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
 497                 if (!strcasecmp(bm, imx_tve_modes[i]))
 498                         return i;
 499
 500         return -EINVAL;
 501 }
 502
 503 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
 504 {
 505         struct platform_device *pdev = to_platform_device(dev);
 506         struct drm_device *drm = data;
 507         struct device_node *np = dev->of_node;
 508         struct device_node *ddc_node;
 509         struct imx_tve *tve;
 510         struct resource *res;
 511         void __iomem *base;
 512         unsigned int val;
 513         int irq;
 514         int ret;
 515
 516         tve = dev_get_drvdata(dev);
 517         memset(tve, 0, sizeof(*tve));
 518
 519         tve->dev = dev;
 520
 521         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
 522         if (ddc_node) {
 523                 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
 524                 of_node_put(ddc_node);
 525         }
 526
 527         tve->mode = of_get_tve_mode(np);
 528         if (tve->mode != TVE_MODE_VGA) {
 529                 dev_err(dev, "only VGA mode supported, currently\n");
 530                 return -EINVAL;
 531         }
 532
 533         if (tve->mode == TVE_MODE_VGA) {
 534                 ret = of_property_read_u32(np, "fsl,hsync-pin",
 535                                            &tve->di_hsync_pin);
 536
 537                 if (ret < 0) {
 538                         dev_err(dev, "failed to get hsync pin\n");
 539                         return ret;
 540                 }
 541
 542                 ret = of_property_read_u32(np, "fsl,vsync-pin",
 543                                            &tve->di_vsync_pin);
 544
 545                 if (ret < 0) {
 546                         dev_err(dev, "failed to get vsync pin\n");
 547                         return ret;
 548                 }
 549         }
 550
 551         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 552         base = devm_ioremap_resource(dev, res);
 553         if (IS_ERR(base))
 554                 return PTR_ERR(base);
 555
 556         tve_regmap_config.lock_arg = tve;
 557         tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
 558                                                 &tve_regmap_config);
 559         if (IS_ERR(tve->regmap)) {
 560                 dev_err(dev, "failed to init regmap: %ld\n",
 561                         PTR_ERR(tve->regmap));
 562                 return PTR_ERR(tve->regmap);
 563         }
 564
 565         irq = platform_get_irq(pdev, 0);
 566         if (irq < 0)
 567                 return irq;
 568
 569         ret = devm_request_threaded_irq(dev, irq, NULL,
 570                                         imx_tve_irq_handler, IRQF_ONESHOT,
 571                                         "imx-tve", tve);
 572         if (ret < 0) {
 573                 dev_err(dev, "failed to request irq: %d\n", ret);
 574                 return ret;
 575         }
 576
 577         tve->dac_reg = devm_regulator_get(dev, "dac");
 578         if (!IS_ERR(tve->dac_reg)) {
 579                 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
 580                         dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
 581                 ret = regulator_enable(tve->dac_reg);
 582                 if (ret)
 583                         return ret;
 584                 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
 585                 if (ret)
 586                         return ret;
 587         }
 588
 589         tve->clk = devm_clk_get(dev, "tve");
 590         if (IS_ERR(tve->clk)) {
 591                 dev_err(dev, "failed to get high speed tve clock: %ld\n",
 592                         PTR_ERR(tve->clk));
 593                 return PTR_ERR(tve->clk);
 594         }
 595
 596         /* this is the IPU DI clock input selector, can be parented to tve_di */
 597         tve->di_sel_clk = devm_clk_get(dev, "di_sel");
 598         if (IS_ERR(tve->di_sel_clk)) {
 599                 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
 600                         PTR_ERR(tve->di_sel_clk));
 601                 return PTR_ERR(tve->di_sel_clk);
 602         }
 603
 604         ret = tve_clk_init(tve, base);
 605         if (ret < 0)
 606                 return ret;
 607
 608         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
 609         if (ret < 0) {
 610                 dev_err(dev, "failed to read configuration register: %d\n",
 611                         ret);
 612                 return ret;
 613         }
 614         if (val != 0x00100000) {
 615                 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
 616                 return -ENODEV;
 617         }
 618
 619         /* disable cable detection for VGA mode */
 620         ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
 621         if (ret)
 622                 return ret;
 623
 624         ret = imx_tve_register(drm, tve);
 625         if (ret)
 626                 return ret;
 627
 628         return 0;
 629 }
 630
 631 static const struct component_ops imx_tve_ops = {
 632         .bind   = imx_tve_bind,
 633 };
 634
 635 static int imx_tve_probe(struct platform_device *pdev)
 636 {
 637         struct imx_tve *tve;
 638
 639         tve = devm_kzalloc(&pdev->dev, sizeof(*tve), GFP_KERNEL);
 640         if (!tve)
 641                 return -ENOMEM;
 642
 643         platform_set_drvdata(pdev, tve);
 644
 645         return component_add(&pdev->dev, &imx_tve_ops);
 646 }
 647
 648 static int imx_tve_remove(struct platform_device *pdev)
 649 {
 650         component_del(&pdev->dev, &imx_tve_ops);
 651         return 0;
 652 }
 653
 654 static const struct of_device_id imx_tve_dt_ids[] = {
 655         { .compatible = "fsl,imx53-tve", },
 656         { /* sentinel */ }
 657 };
 658 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
 659
 660 static struct platform_driver imx_tve_driver = {
 661         .probe          = imx_tve_probe,
 662         .remove         = imx_tve_remove,
 663         .driver         = {
 664                 .of_match_table = imx_tve_dt_ids,
 665                 .name   = "imx-tve",
 666         },
 667 };
 668
 669 module_platform_driver(imx_tve_driver);
 670
 671 MODULE_DESCRIPTION("i.MX Television Encoder driver");
 672 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
 673 MODULE_LICENSE("GPL");
 674 MODULE_ALIAS("platform:imx-tve");