WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / kmb / kmb_drv.c
bloba31a840ce63491078a4ebf888e327ff32810ed4a
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright © 2018-2020 Intel Corporation
4 */
6 #include <linux/clk.h>
7 #include <linux/module.h>
8 #include <linux/of_graph.h>
9 #include <linux/of_platform.h>
10 #include <linux/of_reserved_mem.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_drv.h>
18 #include <drm/drm_gem_cma_helper.h>
19 #include <drm/drm_gem_framebuffer_helper.h>
20 #include <drm/drm_irq.h>
21 #include <drm/drm_probe_helper.h>
22 #include <drm/drm_vblank.h>
24 #include "kmb_drv.h"
25 #include "kmb_dsi.h"
26 #include "kmb_regs.h"
28 static int kmb_display_clk_enable(struct kmb_drm_private *kmb)
30 int ret = 0;
32 ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd);
33 if (ret) {
34 drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret);
35 return ret;
37 DRM_INFO("SUCCESS : enabled LCD clocks\n");
38 return 0;
41 static int kmb_initialize_clocks(struct kmb_drm_private *kmb, struct device *dev)
43 int ret = 0;
44 struct regmap *msscam;
46 kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd");
47 if (IS_ERR(kmb->kmb_clk.clk_lcd)) {
48 drm_err(&kmb->drm, "clk_get() failed clk_lcd\n");
49 return PTR_ERR(kmb->kmb_clk.clk_lcd);
52 kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0");
53 if (IS_ERR(kmb->kmb_clk.clk_pll0)) {
54 drm_err(&kmb->drm, "clk_get() failed clk_pll0 ");
55 return PTR_ERR(kmb->kmb_clk.clk_pll0);
57 kmb->sys_clk_mhz = clk_get_rate(kmb->kmb_clk.clk_pll0) / 1000000;
58 drm_info(&kmb->drm, "system clk = %d Mhz", kmb->sys_clk_mhz);
60 ret = kmb_dsi_clk_init(kmb->kmb_dsi);
62 /* Set LCD clock to 200 Mhz */
63 clk_set_rate(kmb->kmb_clk.clk_lcd, KMB_LCD_DEFAULT_CLK);
64 if (clk_get_rate(kmb->kmb_clk.clk_lcd) != KMB_LCD_DEFAULT_CLK) {
65 drm_err(&kmb->drm, "failed to set to clk_lcd to %d\n",
66 KMB_LCD_DEFAULT_CLK);
67 return -1;
69 drm_dbg(&kmb->drm, "clk_lcd = %ld\n", clk_get_rate(kmb->kmb_clk.clk_lcd));
71 ret = kmb_display_clk_enable(kmb);
72 if (ret)
73 return ret;
75 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam");
76 if (IS_ERR(msscam)) {
77 drm_err(&kmb->drm, "failed to get msscam syscon");
78 return -1;
81 /* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */
82 regmap_update_bits(msscam, MSS_CAM_CLK_CTRL, 0x1fff, 0x1fff);
83 regmap_update_bits(msscam, MSS_CAM_RSTN_CTRL, 0xffffffff, 0xffffffff);
84 return 0;
87 static void kmb_display_clk_disable(struct kmb_drm_private *kmb)
89 clk_disable_unprepare(kmb->kmb_clk.clk_lcd);
92 static void __iomem *kmb_map_mmio(struct drm_device *drm,
93 struct platform_device *pdev,
94 char *name)
96 struct resource *res;
97 void __iomem *mem;
99 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
100 if (!res) {
101 drm_err(drm, "failed to get resource for %s", name);
102 return ERR_PTR(-ENOMEM);
104 mem = devm_ioremap_resource(drm->dev, res);
105 if (IS_ERR(mem))
106 drm_err(drm, "failed to ioremap %s registers", name);
107 return mem;
110 static int kmb_hw_init(struct drm_device *drm, unsigned long flags)
112 struct kmb_drm_private *kmb = to_kmb(drm);
113 struct platform_device *pdev = to_platform_device(drm->dev);
114 int irq_lcd;
115 int ret = 0;
117 /* Map LCD MMIO registers */
118 kmb->lcd_mmio = kmb_map_mmio(drm, pdev, "lcd");
119 if (IS_ERR(kmb->lcd_mmio)) {
120 drm_err(&kmb->drm, "failed to map LCD registers\n");
121 return -ENOMEM;
124 /* Map MIPI MMIO registers */
125 ret = kmb_dsi_map_mmio(kmb->kmb_dsi);
126 if (ret)
127 return ret;
129 /* Enable display clocks */
130 kmb_initialize_clocks(kmb, &pdev->dev);
132 /* Register irqs here - section 17.3 in databook
133 * lists LCD at 79 and 82 for MIPI under MSS CPU -
134 * firmware has redirected 79 to A53 IRQ 33
137 /* Allocate LCD interrupt resources */
138 irq_lcd = platform_get_irq(pdev, 0);
139 if (irq_lcd < 0) {
140 drm_err(&kmb->drm, "irq_lcd not found");
141 goto setup_fail;
144 /* Get the optional framebuffer memory resource */
145 ret = of_reserved_mem_device_init(drm->dev);
146 if (ret && ret != -ENODEV)
147 return ret;
149 spin_lock_init(&kmb->irq_lock);
151 kmb->irq_lcd = irq_lcd;
153 return 0;
155 setup_fail:
156 of_reserved_mem_device_release(drm->dev);
158 return ret;
161 static const struct drm_mode_config_funcs kmb_mode_config_funcs = {
162 .fb_create = drm_gem_fb_create,
163 .atomic_check = drm_atomic_helper_check,
164 .atomic_commit = drm_atomic_helper_commit,
167 static int kmb_setup_mode_config(struct drm_device *drm)
169 int ret;
170 struct kmb_drm_private *kmb = to_kmb(drm);
172 ret = drmm_mode_config_init(drm);
173 if (ret)
174 return ret;
175 drm->mode_config.min_width = KMB_MIN_WIDTH;
176 drm->mode_config.min_height = KMB_MIN_HEIGHT;
177 drm->mode_config.max_width = KMB_MAX_WIDTH;
178 drm->mode_config.max_height = KMB_MAX_HEIGHT;
179 drm->mode_config.funcs = &kmb_mode_config_funcs;
181 ret = kmb_setup_crtc(drm);
182 if (ret < 0) {
183 drm_err(drm, "failed to create crtc\n");
184 return ret;
186 ret = kmb_dsi_encoder_init(drm, kmb->kmb_dsi);
187 /* Set the CRTC's port so that the encoder component can find it */
188 kmb->crtc.port = of_graph_get_port_by_id(drm->dev->of_node, 0);
189 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
190 if (ret < 0) {
191 drm_err(drm, "failed to initialize vblank\n");
192 pm_runtime_disable(drm->dev);
193 return ret;
196 drm_mode_config_reset(drm);
197 return 0;
200 static irqreturn_t handle_lcd_irq(struct drm_device *dev)
202 unsigned long status, val, val1;
203 int plane_id, dma0_state, dma1_state;
204 struct kmb_drm_private *kmb = to_kmb(dev);
206 status = kmb_read_lcd(kmb, LCD_INT_STATUS);
208 spin_lock(&kmb->irq_lock);
209 if (status & LCD_INT_EOF) {
210 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF);
212 /* When disabling/enabling LCD layers, the change takes effect
213 * immediately and does not wait for EOF (end of frame).
214 * When kmb_plane_atomic_disable is called, mark the plane as
215 * disabled but actually disable the plane when EOF irq is
216 * being handled.
218 for (plane_id = LAYER_0;
219 plane_id < KMB_MAX_PLANES; plane_id++) {
220 if (kmb->plane_status[plane_id].disable) {
221 kmb_clr_bitmask_lcd(kmb,
222 LCD_LAYERn_DMA_CFG
223 (plane_id),
224 LCD_DMA_LAYER_ENABLE);
226 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
227 kmb->plane_status[plane_id].ctrl);
229 kmb->plane_status[plane_id].disable = false;
232 if (kmb->kmb_under_flow) {
233 /* DMA Recovery after underflow */
234 dma0_state = (kmb->layer_no == 0) ?
235 LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE;
236 dma1_state = (kmb->layer_no == 0) ?
237 LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE;
239 do {
240 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
241 val = kmb_read_lcd(kmb, dma0_state)
242 & LCD_DMA_STATE_ACTIVE;
243 val1 = kmb_read_lcd(kmb, dma1_state)
244 & LCD_DMA_STATE_ACTIVE;
245 } while ((val || val1));
246 /* disable dma */
247 kmb_clr_bitmask_lcd(kmb,
248 LCD_LAYERn_DMA_CFG(kmb->layer_no),
249 LCD_DMA_LAYER_ENABLE);
250 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
251 kmb->kmb_flush_done = 1;
252 kmb->kmb_under_flow = 0;
256 if (status & LCD_INT_LINE_CMP) {
257 /* clear line compare interrupt */
258 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LINE_CMP);
261 if (status & LCD_INT_VERT_COMP) {
262 /* Read VSTATUS */
263 val = kmb_read_lcd(kmb, LCD_VSTATUS);
264 val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK);
265 switch (val) {
266 case LCD_VSTATUS_COMPARE_VSYNC:
267 /* Clear vertical compare interrupt */
268 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
269 if (kmb->kmb_flush_done) {
270 kmb_set_bitmask_lcd(kmb,
271 LCD_LAYERn_DMA_CFG
272 (kmb->layer_no),
273 LCD_DMA_LAYER_ENABLE);
274 kmb->kmb_flush_done = 0;
276 drm_crtc_handle_vblank(&kmb->crtc);
277 break;
278 case LCD_VSTATUS_COMPARE_BACKPORCH:
279 case LCD_VSTATUS_COMPARE_ACTIVE:
280 case LCD_VSTATUS_COMPARE_FRONT_PORCH:
281 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
282 break;
285 if (status & LCD_INT_DMA_ERR) {
286 val =
287 (status & LCD_INT_DMA_ERR &
288 kmb_read_lcd(kmb, LCD_INT_ENABLE));
289 /* LAYER0 - VL0 */
290 if (val & (LAYER0_DMA_FIFO_UNDERFLOW |
291 LAYER0_DMA_CB_FIFO_UNDERFLOW |
292 LAYER0_DMA_CR_FIFO_UNDERFLOW)) {
293 kmb->kmb_under_flow++;
294 drm_info(&kmb->drm,
295 "!LAYER0:VL0 DMA UNDERFLOW val = 0x%lx,under_flow=%d",
296 val, kmb->kmb_under_flow);
297 /* disable underflow interrupt */
298 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
299 LAYER0_DMA_FIFO_UNDERFLOW |
300 LAYER0_DMA_CB_FIFO_UNDERFLOW |
301 LAYER0_DMA_CR_FIFO_UNDERFLOW);
302 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR,
303 LAYER0_DMA_CB_FIFO_UNDERFLOW |
304 LAYER0_DMA_FIFO_UNDERFLOW |
305 LAYER0_DMA_CR_FIFO_UNDERFLOW);
306 /* disable auto restart mode */
307 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(0),
308 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE);
310 kmb->layer_no = 0;
313 if (val & LAYER0_DMA_FIFO_OVERFLOW)
314 drm_dbg(&kmb->drm,
315 "LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val);
316 if (val & LAYER0_DMA_CB_FIFO_OVERFLOW)
317 drm_dbg(&kmb->drm,
318 "LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val);
319 if (val & LAYER0_DMA_CR_FIFO_OVERFLOW)
320 drm_dbg(&kmb->drm,
321 "LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val);
323 /* LAYER1 - VL1 */
324 if (val & (LAYER1_DMA_FIFO_UNDERFLOW |
325 LAYER1_DMA_CB_FIFO_UNDERFLOW |
326 LAYER1_DMA_CR_FIFO_UNDERFLOW)) {
327 kmb->kmb_under_flow++;
328 drm_info(&kmb->drm,
329 "!LAYER1:VL1 DMA UNDERFLOW val = 0x%lx, under_flow=%d",
330 val, kmb->kmb_under_flow);
331 /* disable underflow interrupt */
332 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
333 LAYER1_DMA_FIFO_UNDERFLOW |
334 LAYER1_DMA_CB_FIFO_UNDERFLOW |
335 LAYER1_DMA_CR_FIFO_UNDERFLOW);
336 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR,
337 LAYER1_DMA_CB_FIFO_UNDERFLOW |
338 LAYER1_DMA_FIFO_UNDERFLOW |
339 LAYER1_DMA_CR_FIFO_UNDERFLOW);
340 /* disable auto restart mode */
341 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(1),
342 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE);
343 kmb->layer_no = 1;
346 /* LAYER1 - VL1 */
347 if (val & LAYER1_DMA_FIFO_OVERFLOW)
348 drm_dbg(&kmb->drm,
349 "LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val);
350 if (val & LAYER1_DMA_CB_FIFO_OVERFLOW)
351 drm_dbg(&kmb->drm,
352 "LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val);
353 if (val & LAYER1_DMA_CR_FIFO_OVERFLOW)
354 drm_dbg(&kmb->drm,
355 "LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val);
357 /* LAYER2 - GL0 */
358 if (val & LAYER2_DMA_FIFO_UNDERFLOW)
359 drm_dbg(&kmb->drm,
360 "LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val);
361 if (val & LAYER2_DMA_FIFO_OVERFLOW)
362 drm_dbg(&kmb->drm,
363 "LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val);
365 /* LAYER3 - GL1 */
366 if (val & LAYER3_DMA_FIFO_UNDERFLOW)
367 drm_dbg(&kmb->drm,
368 "LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val);
369 if (val & LAYER3_DMA_FIFO_UNDERFLOW)
370 drm_dbg(&kmb->drm,
371 "LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val);
374 spin_unlock(&kmb->irq_lock);
376 if (status & LCD_INT_LAYER) {
377 /* Clear layer interrupts */
378 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LAYER);
381 /* Clear all interrupts */
382 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 1);
383 return IRQ_HANDLED;
386 /* IRQ handler */
387 static irqreturn_t kmb_isr(int irq, void *arg)
389 struct drm_device *dev = (struct drm_device *)arg;
391 handle_lcd_irq(dev);
392 return IRQ_HANDLED;
395 static void kmb_irq_reset(struct drm_device *drm)
397 kmb_write_lcd(to_kmb(drm), LCD_INT_CLEAR, 0xFFFF);
398 kmb_write_lcd(to_kmb(drm), LCD_INT_ENABLE, 0);
401 DEFINE_DRM_GEM_CMA_FOPS(fops);
403 static struct drm_driver kmb_driver = {
404 .driver_features = DRIVER_GEM |
405 DRIVER_MODESET | DRIVER_ATOMIC,
406 .irq_handler = kmb_isr,
407 .irq_preinstall = kmb_irq_reset,
408 .irq_uninstall = kmb_irq_reset,
409 /* GEM Operations */
410 .fops = &fops,
411 DRM_GEM_CMA_DRIVER_OPS_VMAP,
412 .name = "kmb-drm",
413 .desc = "KEEMBAY DISPLAY DRIVER ",
414 .date = "20201008",
415 .major = 1,
416 .minor = 0,
419 static int kmb_remove(struct platform_device *pdev)
421 struct device *dev = &pdev->dev;
422 struct drm_device *drm = dev_get_drvdata(dev);
423 struct kmb_drm_private *kmb = to_kmb(drm);
425 drm_dev_unregister(drm);
426 drm_kms_helper_poll_fini(drm);
427 of_node_put(kmb->crtc.port);
428 kmb->crtc.port = NULL;
429 pm_runtime_get_sync(drm->dev);
430 drm_irq_uninstall(drm);
431 pm_runtime_put_sync(drm->dev);
432 pm_runtime_disable(drm->dev);
434 of_reserved_mem_device_release(drm->dev);
436 /* Release clks */
437 kmb_display_clk_disable(kmb);
439 dev_set_drvdata(dev, NULL);
441 /* Unregister DSI host */
442 kmb_dsi_host_unregister(kmb->kmb_dsi);
443 drm_atomic_helper_shutdown(drm);
444 return 0;
447 static int kmb_probe(struct platform_device *pdev)
449 struct device *dev = get_device(&pdev->dev);
450 struct kmb_drm_private *kmb;
451 int ret = 0;
452 struct device_node *dsi_in;
453 struct device_node *dsi_node;
454 struct platform_device *dsi_pdev;
456 /* The bridge (ADV 7535) will return -EPROBE_DEFER until it
457 * has a mipi_dsi_host to register its device to. So, we
458 * first register the DSI host during probe time, and then return
459 * -EPROBE_DEFER until the bridge is loaded. Probe will be called again
460 * and then the rest of the driver initialization can proceed
461 * afterwards and the bridge can be successfully attached.
463 dsi_in = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
464 if (!dsi_in) {
465 DRM_ERROR("Failed to get dsi_in node info from DT");
466 return -EINVAL;
468 dsi_node = of_graph_get_remote_port_parent(dsi_in);
469 if (!dsi_node) {
470 of_node_put(dsi_in);
471 DRM_ERROR("Failed to get dsi node from DT\n");
472 return -EINVAL;
475 dsi_pdev = of_find_device_by_node(dsi_node);
476 if (!dsi_pdev) {
477 of_node_put(dsi_in);
478 of_node_put(dsi_node);
479 DRM_ERROR("Failed to get dsi platform device\n");
480 return -EINVAL;
483 of_node_put(dsi_in);
484 of_node_put(dsi_node);
485 ret = kmb_dsi_host_bridge_init(get_device(&dsi_pdev->dev));
487 if (ret == -EPROBE_DEFER) {
488 return -EPROBE_DEFER;
489 } else if (ret) {
490 DRM_ERROR("probe failed to initialize DSI host bridge\n");
491 return ret;
494 /* Create DRM device */
495 kmb = devm_drm_dev_alloc(dev, &kmb_driver,
496 struct kmb_drm_private, drm);
497 if (IS_ERR(kmb))
498 return PTR_ERR(kmb);
500 dev_set_drvdata(dev, &kmb->drm);
502 /* Initialize MIPI DSI */
503 kmb->kmb_dsi = kmb_dsi_init(dsi_pdev);
504 if (IS_ERR(kmb->kmb_dsi)) {
505 drm_err(&kmb->drm, "failed to initialize DSI\n");
506 ret = PTR_ERR(kmb->kmb_dsi);
507 goto err_free1;
510 kmb->kmb_dsi->dev = &dsi_pdev->dev;
511 kmb->kmb_dsi->pdev = dsi_pdev;
512 ret = kmb_hw_init(&kmb->drm, 0);
513 if (ret)
514 goto err_free1;
516 ret = kmb_setup_mode_config(&kmb->drm);
517 if (ret)
518 goto err_free;
520 ret = drm_irq_install(&kmb->drm, kmb->irq_lcd);
521 if (ret < 0) {
522 drm_err(&kmb->drm, "failed to install IRQ handler\n");
523 goto err_irq;
526 drm_kms_helper_poll_init(&kmb->drm);
528 /* Register graphics device with the kernel */
529 ret = drm_dev_register(&kmb->drm, 0);
530 if (ret)
531 goto err_register;
533 return 0;
535 err_register:
536 drm_kms_helper_poll_fini(&kmb->drm);
537 err_irq:
538 pm_runtime_disable(kmb->drm.dev);
539 err_free:
540 drm_crtc_cleanup(&kmb->crtc);
541 drm_mode_config_cleanup(&kmb->drm);
542 err_free1:
543 dev_set_drvdata(dev, NULL);
544 kmb_dsi_host_unregister(kmb->kmb_dsi);
546 return ret;
549 static const struct of_device_id kmb_of_match[] = {
550 {.compatible = "intel,keembay-display"},
554 MODULE_DEVICE_TABLE(of, kmb_of_match);
556 static int __maybe_unused kmb_pm_suspend(struct device *dev)
558 struct drm_device *drm = dev_get_drvdata(dev);
559 struct kmb_drm_private *kmb = drm ? to_kmb(drm) : NULL;
561 drm_kms_helper_poll_disable(drm);
563 kmb->state = drm_atomic_helper_suspend(drm);
564 if (IS_ERR(kmb->state)) {
565 drm_kms_helper_poll_enable(drm);
566 return PTR_ERR(kmb->state);
569 return 0;
572 static int __maybe_unused kmb_pm_resume(struct device *dev)
574 struct drm_device *drm = dev_get_drvdata(dev);
575 struct kmb_drm_private *kmb = drm ? to_kmb(drm) : NULL;
577 if (!kmb)
578 return 0;
580 drm_atomic_helper_resume(drm, kmb->state);
581 drm_kms_helper_poll_enable(drm);
583 return 0;
586 static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume);
588 static struct platform_driver kmb_platform_driver = {
589 .probe = kmb_probe,
590 .remove = kmb_remove,
591 .driver = {
592 .name = "kmb-drm",
593 .pm = &kmb_pm_ops,
594 .of_match_table = kmb_of_match,
598 module_platform_driver(kmb_platform_driver);
600 MODULE_AUTHOR("Intel Corporation");
601 MODULE_DESCRIPTION("Keembay Display driver");
602 MODULE_LICENSE("GPL v2");