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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / msm / adreno / a5xx.xml.h
blob346cc6ff3a36215606329cdad445fc768fa989f5
1 #ifndef A5XX_XML
2 #define A5XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22 - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23 - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24
25 Copyright (C) 2013-2020 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50
51 enum a5xx_color_fmt {
52 RB5_A8_UNORM = 2,
53 RB5_R8_UNORM = 3,
54 RB5_R8_SNORM = 4,
55 RB5_R8_UINT = 5,
56 RB5_R8_SINT = 6,
57 RB5_R4G4B4A4_UNORM = 8,
58 RB5_R5G5B5A1_UNORM = 10,
59 RB5_R5G6B5_UNORM = 14,
60 RB5_R8G8_UNORM = 15,
61 RB5_R8G8_SNORM = 16,
62 RB5_R8G8_UINT = 17,
63 RB5_R8G8_SINT = 18,
64 RB5_R16_UNORM = 21,
65 RB5_R16_SNORM = 22,
66 RB5_R16_FLOAT = 23,
67 RB5_R16_UINT = 24,
68 RB5_R16_SINT = 25,
69 RB5_R8G8B8A8_UNORM = 48,
70 RB5_R8G8B8_UNORM = 49,
71 RB5_R8G8B8A8_SNORM = 50,
72 RB5_R8G8B8A8_UINT = 51,
73 RB5_R8G8B8A8_SINT = 52,
74 RB5_R10G10B10A2_UNORM = 55,
75 RB5_R10G10B10A2_UINT = 58,
76 RB5_R11G11B10_FLOAT = 66,
77 RB5_R16G16_UNORM = 67,
78 RB5_R16G16_SNORM = 68,
79 RB5_R16G16_FLOAT = 69,
80 RB5_R16G16_UINT = 70,
81 RB5_R16G16_SINT = 71,
82 RB5_R32_FLOAT = 74,
83 RB5_R32_UINT = 75,
84 RB5_R32_SINT = 76,
85 RB5_R16G16B16A16_UNORM = 96,
86 RB5_R16G16B16A16_SNORM = 97,
87 RB5_R16G16B16A16_FLOAT = 98,
88 RB5_R16G16B16A16_UINT = 99,
89 RB5_R16G16B16A16_SINT = 100,
90 RB5_R32G32_FLOAT = 103,
91 RB5_R32G32_UINT = 104,
92 RB5_R32G32_SINT = 105,
93 RB5_R32G32B32A32_FLOAT = 130,
94 RB5_R32G32B32A32_UINT = 131,
95 RB5_R32G32B32A32_SINT = 132,
96 RB5_NONE = 255,
97 };
98
99 enum a5xx_tile_mode {
100 TILE5_LINEAR = 0,
101 TILE5_2 = 2,
102 TILE5_3 = 3,
103 };
104
105 enum a5xx_vtx_fmt {
106 VFMT5_8_UNORM = 3,
107 VFMT5_8_SNORM = 4,
108 VFMT5_8_UINT = 5,
109 VFMT5_8_SINT = 6,
110 VFMT5_8_8_UNORM = 15,
111 VFMT5_8_8_SNORM = 16,
112 VFMT5_8_8_UINT = 17,
113 VFMT5_8_8_SINT = 18,
114 VFMT5_16_UNORM = 21,
115 VFMT5_16_SNORM = 22,
116 VFMT5_16_FLOAT = 23,
117 VFMT5_16_UINT = 24,
118 VFMT5_16_SINT = 25,
119 VFMT5_8_8_8_UNORM = 33,
120 VFMT5_8_8_8_SNORM = 34,
121 VFMT5_8_8_8_UINT = 35,
122 VFMT5_8_8_8_SINT = 36,
123 VFMT5_8_8_8_8_UNORM = 48,
124 VFMT5_8_8_8_8_SNORM = 50,
125 VFMT5_8_8_8_8_UINT = 51,
126 VFMT5_8_8_8_8_SINT = 52,
127 VFMT5_10_10_10_2_UNORM = 54,
128 VFMT5_10_10_10_2_SNORM = 57,
129 VFMT5_10_10_10_2_UINT = 58,
130 VFMT5_10_10_10_2_SINT = 59,
131 VFMT5_11_11_10_FLOAT = 66,
132 VFMT5_16_16_UNORM = 67,
133 VFMT5_16_16_SNORM = 68,
134 VFMT5_16_16_FLOAT = 69,
135 VFMT5_16_16_UINT = 70,
136 VFMT5_16_16_SINT = 71,
137 VFMT5_32_UNORM = 72,
138 VFMT5_32_SNORM = 73,
139 VFMT5_32_FLOAT = 74,
140 VFMT5_32_UINT = 75,
141 VFMT5_32_SINT = 76,
142 VFMT5_32_FIXED = 77,
143 VFMT5_16_16_16_UNORM = 88,
144 VFMT5_16_16_16_SNORM = 89,
145 VFMT5_16_16_16_FLOAT = 90,
146 VFMT5_16_16_16_UINT = 91,
147 VFMT5_16_16_16_SINT = 92,
148 VFMT5_16_16_16_16_UNORM = 96,
149 VFMT5_16_16_16_16_SNORM = 97,
150 VFMT5_16_16_16_16_FLOAT = 98,
151 VFMT5_16_16_16_16_UINT = 99,
152 VFMT5_16_16_16_16_SINT = 100,
153 VFMT5_32_32_UNORM = 101,
154 VFMT5_32_32_SNORM = 102,
155 VFMT5_32_32_FLOAT = 103,
156 VFMT5_32_32_UINT = 104,
157 VFMT5_32_32_SINT = 105,
158 VFMT5_32_32_FIXED = 106,
159 VFMT5_32_32_32_UNORM = 112,
160 VFMT5_32_32_32_SNORM = 113,
161 VFMT5_32_32_32_UINT = 114,
162 VFMT5_32_32_32_SINT = 115,
163 VFMT5_32_32_32_FLOAT = 116,
164 VFMT5_32_32_32_FIXED = 117,
165 VFMT5_32_32_32_32_UNORM = 128,
166 VFMT5_32_32_32_32_SNORM = 129,
167 VFMT5_32_32_32_32_FLOAT = 130,
168 VFMT5_32_32_32_32_UINT = 131,
169 VFMT5_32_32_32_32_SINT = 132,
170 VFMT5_32_32_32_32_FIXED = 133,
171 VFMT5_NONE = 255,
172 };
173
174 enum a5xx_tex_fmt {
175 TFMT5_A8_UNORM = 2,
176 TFMT5_8_UNORM = 3,
177 TFMT5_8_SNORM = 4,
178 TFMT5_8_UINT = 5,
179 TFMT5_8_SINT = 6,
180 TFMT5_4_4_4_4_UNORM = 8,
181 TFMT5_5_5_5_1_UNORM = 10,
182 TFMT5_5_6_5_UNORM = 14,
183 TFMT5_8_8_UNORM = 15,
184 TFMT5_8_8_SNORM = 16,
185 TFMT5_8_8_UINT = 17,
186 TFMT5_8_8_SINT = 18,
187 TFMT5_L8_A8_UNORM = 19,
188 TFMT5_16_UNORM = 21,
189 TFMT5_16_SNORM = 22,
190 TFMT5_16_FLOAT = 23,
191 TFMT5_16_UINT = 24,
192 TFMT5_16_SINT = 25,
193 TFMT5_8_8_8_8_UNORM = 48,
194 TFMT5_8_8_8_UNORM = 49,
195 TFMT5_8_8_8_8_SNORM = 50,
196 TFMT5_8_8_8_8_UINT = 51,
197 TFMT5_8_8_8_8_SINT = 52,
198 TFMT5_9_9_9_E5_FLOAT = 53,
199 TFMT5_10_10_10_2_UNORM = 54,
200 TFMT5_10_10_10_2_UINT = 58,
201 TFMT5_11_11_10_FLOAT = 66,
202 TFMT5_16_16_UNORM = 67,
203 TFMT5_16_16_SNORM = 68,
204 TFMT5_16_16_FLOAT = 69,
205 TFMT5_16_16_UINT = 70,
206 TFMT5_16_16_SINT = 71,
207 TFMT5_32_FLOAT = 74,
208 TFMT5_32_UINT = 75,
209 TFMT5_32_SINT = 76,
210 TFMT5_16_16_16_16_UNORM = 96,
211 TFMT5_16_16_16_16_SNORM = 97,
212 TFMT5_16_16_16_16_FLOAT = 98,
213 TFMT5_16_16_16_16_UINT = 99,
214 TFMT5_16_16_16_16_SINT = 100,
215 TFMT5_32_32_FLOAT = 103,
216 TFMT5_32_32_UINT = 104,
217 TFMT5_32_32_SINT = 105,
218 TFMT5_32_32_32_UINT = 114,
219 TFMT5_32_32_32_SINT = 115,
220 TFMT5_32_32_32_FLOAT = 116,
221 TFMT5_32_32_32_32_FLOAT = 130,
222 TFMT5_32_32_32_32_UINT = 131,
223 TFMT5_32_32_32_32_SINT = 132,
224 TFMT5_X8Z24_UNORM = 160,
225 TFMT5_ETC2_RG11_UNORM = 171,
226 TFMT5_ETC2_RG11_SNORM = 172,
227 TFMT5_ETC2_R11_UNORM = 173,
228 TFMT5_ETC2_R11_SNORM = 174,
229 TFMT5_ETC1 = 175,
230 TFMT5_ETC2_RGB8 = 176,
231 TFMT5_ETC2_RGBA8 = 177,
232 TFMT5_ETC2_RGB8A1 = 178,
233 TFMT5_DXT1 = 179,
234 TFMT5_DXT3 = 180,
235 TFMT5_DXT5 = 181,
236 TFMT5_RGTC1_UNORM = 183,
237 TFMT5_RGTC1_SNORM = 184,
238 TFMT5_RGTC2_UNORM = 187,
239 TFMT5_RGTC2_SNORM = 188,
240 TFMT5_BPTC_UFLOAT = 190,
241 TFMT5_BPTC_FLOAT = 191,
242 TFMT5_BPTC = 192,
243 TFMT5_ASTC_4x4 = 193,
244 TFMT5_ASTC_5x4 = 194,
245 TFMT5_ASTC_5x5 = 195,
246 TFMT5_ASTC_6x5 = 196,
247 TFMT5_ASTC_6x6 = 197,
248 TFMT5_ASTC_8x5 = 198,
249 TFMT5_ASTC_8x6 = 199,
250 TFMT5_ASTC_8x8 = 200,
251 TFMT5_ASTC_10x5 = 201,
252 TFMT5_ASTC_10x6 = 202,
253 TFMT5_ASTC_10x8 = 203,
254 TFMT5_ASTC_10x10 = 204,
255 TFMT5_ASTC_12x10 = 205,
256 TFMT5_ASTC_12x12 = 206,
257 TFMT5_NONE = 255,
258 };
259
260 enum a5xx_depth_format {
261 DEPTH5_NONE = 0,
262 DEPTH5_16 = 1,
263 DEPTH5_24_8 = 2,
264 DEPTH5_32 = 4,
265 };
266
267 enum a5xx_blit_buf {
268 BLIT_MRT0 = 0,
269 BLIT_MRT1 = 1,
270 BLIT_MRT2 = 2,
271 BLIT_MRT3 = 3,
272 BLIT_MRT4 = 4,
273 BLIT_MRT5 = 5,
274 BLIT_MRT6 = 6,
275 BLIT_MRT7 = 7,
276 BLIT_ZS = 8,
277 BLIT_S = 9,
278 };
279
280 enum a5xx_cp_perfcounter_select {
281 PERF_CP_ALWAYS_COUNT = 0,
282 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
283 PERF_CP_BUSY_CYCLES = 2,
284 PERF_CP_PFP_IDLE = 3,
285 PERF_CP_PFP_BUSY_WORKING = 4,
286 PERF_CP_PFP_STALL_CYCLES_ANY = 5,
287 PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
288 PERF_CP_PFP_ICACHE_MISS = 7,
289 PERF_CP_PFP_ICACHE_HIT = 8,
290 PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
291 PERF_CP_ME_BUSY_WORKING = 10,
292 PERF_CP_ME_IDLE = 11,
293 PERF_CP_ME_STARVE_CYCLES_ANY = 12,
294 PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
295 PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
296 PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
297 PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
298 PERF_CP_ME_STALL_CYCLES_ANY = 17,
299 PERF_CP_ME_ICACHE_MISS = 18,
300 PERF_CP_ME_ICACHE_HIT = 19,
301 PERF_CP_NUM_PREEMPTIONS = 20,
302 PERF_CP_PREEMPTION_REACTION_DELAY = 21,
303 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
304 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
305 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
306 PERF_CP_PREDICATED_DRAWS_KILLED = 25,
307 PERF_CP_MODE_SWITCH = 26,
308 PERF_CP_ZPASS_DONE = 27,
309 PERF_CP_CONTEXT_DONE = 28,
310 PERF_CP_CACHE_FLUSH = 29,
311 PERF_CP_LONG_PREEMPTIONS = 30,
312 };
313
314 enum a5xx_rbbm_perfcounter_select {
315 PERF_RBBM_ALWAYS_COUNT = 0,
316 PERF_RBBM_ALWAYS_ON = 1,
317 PERF_RBBM_TSE_BUSY = 2,
318 PERF_RBBM_RAS_BUSY = 3,
319 PERF_RBBM_PC_DCALL_BUSY = 4,
320 PERF_RBBM_PC_VSD_BUSY = 5,
321 PERF_RBBM_STATUS_MASKED = 6,
322 PERF_RBBM_COM_BUSY = 7,
323 PERF_RBBM_DCOM_BUSY = 8,
324 PERF_RBBM_VBIF_BUSY = 9,
325 PERF_RBBM_VSC_BUSY = 10,
326 PERF_RBBM_TESS_BUSY = 11,
327 PERF_RBBM_UCHE_BUSY = 12,
328 PERF_RBBM_HLSQ_BUSY = 13,
329 };
330
331 enum a5xx_pc_perfcounter_select {
332 PERF_PC_BUSY_CYCLES = 0,
333 PERF_PC_WORKING_CYCLES = 1,
334 PERF_PC_STALL_CYCLES_VFD = 2,
335 PERF_PC_STALL_CYCLES_TSE = 3,
336 PERF_PC_STALL_CYCLES_VPC = 4,
337 PERF_PC_STALL_CYCLES_UCHE = 5,
338 PERF_PC_STALL_CYCLES_TESS = 6,
339 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
340 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
341 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
342 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
343 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
344 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
345 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
346 PERF_PC_STARVE_CYCLES_DI = 14,
347 PERF_PC_VIS_STREAMS_LOADED = 15,
348 PERF_PC_INSTANCES = 16,
349 PERF_PC_VPC_PRIMITIVES = 17,
350 PERF_PC_DEAD_PRIM = 18,
351 PERF_PC_LIVE_PRIM = 19,
352 PERF_PC_VERTEX_HITS = 20,
353 PERF_PC_IA_VERTICES = 21,
354 PERF_PC_IA_PRIMITIVES = 22,
355 PERF_PC_GS_PRIMITIVES = 23,
356 PERF_PC_HS_INVOCATIONS = 24,
357 PERF_PC_DS_INVOCATIONS = 25,
358 PERF_PC_VS_INVOCATIONS = 26,
359 PERF_PC_GS_INVOCATIONS = 27,
360 PERF_PC_DS_PRIMITIVES = 28,
361 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
362 PERF_PC_3D_DRAWCALLS = 30,
363 PERF_PC_2D_DRAWCALLS = 31,
364 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
365 PERF_TESS_BUSY_CYCLES = 33,
366 PERF_TESS_WORKING_CYCLES = 34,
367 PERF_TESS_STALL_CYCLES_PC = 35,
368 PERF_TESS_STARVE_CYCLES_PC = 36,
369 };
370
371 enum a5xx_vfd_perfcounter_select {
372 PERF_VFD_BUSY_CYCLES = 0,
373 PERF_VFD_STALL_CYCLES_UCHE = 1,
374 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
375 PERF_VFD_STALL_CYCLES_MISS_VB = 3,
376 PERF_VFD_STALL_CYCLES_MISS_Q = 4,
377 PERF_VFD_STALL_CYCLES_SP_INFO = 5,
378 PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
379 PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
380 PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
381 PERF_VFD_DECODER_PACKER_STALL = 9,
382 PERF_VFD_STARVE_CYCLES_UCHE = 10,
383 PERF_VFD_RBUFFER_FULL = 11,
384 PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
385 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
386 PERF_VFD_NUM_ATTRIBUTES = 14,
387 PERF_VFD_INSTRUCTIONS = 15,
388 PERF_VFD_UPPER_SHADER_FIBERS = 16,
389 PERF_VFD_LOWER_SHADER_FIBERS = 17,
390 PERF_VFD_MODE_0_FIBERS = 18,
391 PERF_VFD_MODE_1_FIBERS = 19,
392 PERF_VFD_MODE_2_FIBERS = 20,
393 PERF_VFD_MODE_3_FIBERS = 21,
394 PERF_VFD_MODE_4_FIBERS = 22,
395 PERF_VFD_TOTAL_VERTICES = 23,
396 PERF_VFD_NUM_ATTR_MISS = 24,
397 PERF_VFD_1_BURST_REQ = 25,
398 PERF_VFDP_STALL_CYCLES_VFD = 26,
399 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
400 PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
401 PERF_VFDP_STARVE_CYCLES_PC = 29,
402 PERF_VFDP_VS_STAGE_32_WAVES = 30,
403 };
404
405 enum a5xx_hlsq_perfcounter_select {
406 PERF_HLSQ_BUSY_CYCLES = 0,
407 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
408 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
409 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
410 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
411 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
412 PERF_HLSQ_FS_STAGE_32_WAVES = 6,
413 PERF_HLSQ_FS_STAGE_64_WAVES = 7,
414 PERF_HLSQ_QUADS = 8,
415 PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
416 PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
417 PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
418 PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
419 PERF_HLSQ_CS_INVOCATIONS = 13,
420 PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
421 };
422
423 enum a5xx_vpc_perfcounter_select {
424 PERF_VPC_BUSY_CYCLES = 0,
425 PERF_VPC_WORKING_CYCLES = 1,
426 PERF_VPC_STALL_CYCLES_UCHE = 2,
427 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
428 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
429 PERF_VPC_STALL_CYCLES_PC = 5,
430 PERF_VPC_STALL_CYCLES_SP_LM = 6,
431 PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
432 PERF_VPC_STARVE_CYCLES_SP = 8,
433 PERF_VPC_STARVE_CYCLES_LRZ = 9,
434 PERF_VPC_PC_PRIMITIVES = 10,
435 PERF_VPC_SP_COMPONENTS = 11,
436 PERF_VPC_SP_LM_PRIMITIVES = 12,
437 PERF_VPC_SP_LM_COMPONENTS = 13,
438 PERF_VPC_SP_LM_DWORDS = 14,
439 PERF_VPC_STREAMOUT_COMPONENTS = 15,
440 PERF_VPC_GRANT_PHASES = 16,
441 };
442
443 enum a5xx_tse_perfcounter_select {
444 PERF_TSE_BUSY_CYCLES = 0,
445 PERF_TSE_CLIPPING_CYCLES = 1,
446 PERF_TSE_STALL_CYCLES_RAS = 2,
447 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
448 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
449 PERF_TSE_STARVE_CYCLES_PC = 5,
450 PERF_TSE_INPUT_PRIM = 6,
451 PERF_TSE_INPUT_NULL_PRIM = 7,
452 PERF_TSE_TRIVAL_REJ_PRIM = 8,
453 PERF_TSE_CLIPPED_PRIM = 9,
454 PERF_TSE_ZERO_AREA_PRIM = 10,
455 PERF_TSE_FACENESS_CULLED_PRIM = 11,
456 PERF_TSE_ZERO_PIXEL_PRIM = 12,
457 PERF_TSE_OUTPUT_NULL_PRIM = 13,
458 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
459 PERF_TSE_CINVOCATION = 15,
460 PERF_TSE_CPRIMITIVES = 16,
461 PERF_TSE_2D_INPUT_PRIM = 17,
462 PERF_TSE_2D_ALIVE_CLCLES = 18,
463 };
464
465 enum a5xx_ras_perfcounter_select {
466 PERF_RAS_BUSY_CYCLES = 0,
467 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
468 PERF_RAS_STALL_CYCLES_LRZ = 2,
469 PERF_RAS_STARVE_CYCLES_TSE = 3,
470 PERF_RAS_SUPER_TILES = 4,
471 PERF_RAS_8X4_TILES = 5,
472 PERF_RAS_MASKGEN_ACTIVE = 6,
473 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
474 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
475 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
476 };
477
478 enum a5xx_lrz_perfcounter_select {
479 PERF_LRZ_BUSY_CYCLES = 0,
480 PERF_LRZ_STARVE_CYCLES_RAS = 1,
481 PERF_LRZ_STALL_CYCLES_RB = 2,
482 PERF_LRZ_STALL_CYCLES_VSC = 3,
483 PERF_LRZ_STALL_CYCLES_VPC = 4,
484 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
485 PERF_LRZ_STALL_CYCLES_UCHE = 6,
486 PERF_LRZ_LRZ_READ = 7,
487 PERF_LRZ_LRZ_WRITE = 8,
488 PERF_LRZ_READ_LATENCY = 9,
489 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
490 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
491 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
492 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
493 PERF_LRZ_FULL_8X8_TILES = 14,
494 PERF_LRZ_PARTIAL_8X8_TILES = 15,
495 PERF_LRZ_TILE_KILLED = 16,
496 PERF_LRZ_TOTAL_PIXEL = 17,
497 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
498 };
499
500 enum a5xx_uche_perfcounter_select {
501 PERF_UCHE_BUSY_CYCLES = 0,
502 PERF_UCHE_STALL_CYCLES_VBIF = 1,
503 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
504 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
505 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
506 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
507 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
508 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
509 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
510 PERF_UCHE_READ_REQUESTS_TP = 9,
511 PERF_UCHE_READ_REQUESTS_VFD = 10,
512 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
513 PERF_UCHE_READ_REQUESTS_LRZ = 12,
514 PERF_UCHE_READ_REQUESTS_SP = 13,
515 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
516 PERF_UCHE_WRITE_REQUESTS_SP = 15,
517 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
518 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
519 PERF_UCHE_EVICTS = 18,
520 PERF_UCHE_BANK_REQ0 = 19,
521 PERF_UCHE_BANK_REQ1 = 20,
522 PERF_UCHE_BANK_REQ2 = 21,
523 PERF_UCHE_BANK_REQ3 = 22,
524 PERF_UCHE_BANK_REQ4 = 23,
525 PERF_UCHE_BANK_REQ5 = 24,
526 PERF_UCHE_BANK_REQ6 = 25,
527 PERF_UCHE_BANK_REQ7 = 26,
528 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
529 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
530 PERF_UCHE_GMEM_READ_BEATS = 29,
531 PERF_UCHE_FLAG_COUNT = 30,
532 };
533
534 enum a5xx_tp_perfcounter_select {
535 PERF_TP_BUSY_CYCLES = 0,
536 PERF_TP_STALL_CYCLES_UCHE = 1,
537 PERF_TP_LATENCY_CYCLES = 2,
538 PERF_TP_LATENCY_TRANS = 3,
539 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
540 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
541 PERF_TP_L1_CACHELINE_REQUESTS = 6,
542 PERF_TP_L1_CACHELINE_MISSES = 7,
543 PERF_TP_SP_TP_TRANS = 8,
544 PERF_TP_TP_SP_TRANS = 9,
545 PERF_TP_OUTPUT_PIXELS = 10,
546 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
547 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
548 PERF_TP_QUADS_RECEIVED = 13,
549 PERF_TP_QUADS_OFFSET = 14,
550 PERF_TP_QUADS_SHADOW = 15,
551 PERF_TP_QUADS_ARRAY = 16,
552 PERF_TP_QUADS_GRADIENT = 17,
553 PERF_TP_QUADS_1D = 18,
554 PERF_TP_QUADS_2D = 19,
555 PERF_TP_QUADS_BUFFER = 20,
556 PERF_TP_QUADS_3D = 21,
557 PERF_TP_QUADS_CUBE = 22,
558 PERF_TP_STATE_CACHE_REQUESTS = 23,
559 PERF_TP_STATE_CACHE_MISSES = 24,
560 PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
561 PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
562 PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
563 PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
564 PERF_TP_OUTPUT_PIXELS_POINT = 29,
565 PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
566 PERF_TP_OUTPUT_PIXELS_MIP = 31,
567 PERF_TP_OUTPUT_PIXELS_ANISO = 32,
568 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
569 PERF_TP_FLAG_CACHE_REQUESTS = 34,
570 PERF_TP_FLAG_CACHE_MISSES = 35,
571 PERF_TP_L1_5_L2_REQUESTS = 36,
572 PERF_TP_2D_OUTPUT_PIXELS = 37,
573 PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
574 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
575 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
576 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
577 };
578
579 enum a5xx_sp_perfcounter_select {
580 PERF_SP_BUSY_CYCLES = 0,
581 PERF_SP_ALU_WORKING_CYCLES = 1,
582 PERF_SP_EFU_WORKING_CYCLES = 2,
583 PERF_SP_STALL_CYCLES_VPC = 3,
584 PERF_SP_STALL_CYCLES_TP = 4,
585 PERF_SP_STALL_CYCLES_UCHE = 5,
586 PERF_SP_STALL_CYCLES_RB = 6,
587 PERF_SP_SCHEDULER_NON_WORKING = 7,
588 PERF_SP_WAVE_CONTEXTS = 8,
589 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
590 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
591 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
592 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
593 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
594 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
595 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
596 PERF_SP_WAVE_CTRL_CYCLES = 16,
597 PERF_SP_WAVE_LOAD_CYCLES = 17,
598 PERF_SP_WAVE_EMIT_CYCLES = 18,
599 PERF_SP_WAVE_NOP_CYCLES = 19,
600 PERF_SP_WAVE_WAIT_CYCLES = 20,
601 PERF_SP_WAVE_FETCH_CYCLES = 21,
602 PERF_SP_WAVE_IDLE_CYCLES = 22,
603 PERF_SP_WAVE_END_CYCLES = 23,
604 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
605 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
606 PERF_SP_WAVE_JOIN_CYCLES = 26,
607 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
608 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
609 PERF_SP_LM_ATOMICS = 29,
610 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
611 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
612 PERF_SP_GM_ATOMICS = 32,
613 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
614 PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
615 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
616 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
617 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
618 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
619 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
620 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
621 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
622 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
623 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
624 PERF_SP_VS_INSTRUCTIONS = 44,
625 PERF_SP_FS_INSTRUCTIONS = 45,
626 PERF_SP_ADDR_LOCK_COUNT = 46,
627 PERF_SP_UCHE_READ_TRANS = 47,
628 PERF_SP_UCHE_WRITE_TRANS = 48,
629 PERF_SP_EXPORT_VPC_TRANS = 49,
630 PERF_SP_EXPORT_RB_TRANS = 50,
631 PERF_SP_PIXELS_KILLED = 51,
632 PERF_SP_ICL1_REQUESTS = 52,
633 PERF_SP_ICL1_MISSES = 53,
634 PERF_SP_ICL0_REQUESTS = 54,
635 PERF_SP_ICL0_MISSES = 55,
636 PERF_SP_HS_INSTRUCTIONS = 56,
637 PERF_SP_DS_INSTRUCTIONS = 57,
638 PERF_SP_GS_INSTRUCTIONS = 58,
639 PERF_SP_CS_INSTRUCTIONS = 59,
640 PERF_SP_GPR_READ = 60,
641 PERF_SP_GPR_WRITE = 61,
642 PERF_SP_LM_CH0_REQUESTS = 62,
643 PERF_SP_LM_CH1_REQUESTS = 63,
644 PERF_SP_LM_BANK_CONFLICTS = 64,
645 };
646
647 enum a5xx_rb_perfcounter_select {
648 PERF_RB_BUSY_CYCLES = 0,
649 PERF_RB_STALL_CYCLES_CCU = 1,
650 PERF_RB_STALL_CYCLES_HLSQ = 2,
651 PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
652 PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
653 PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
654 PERF_RB_STARVE_CYCLES_SP = 6,
655 PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
656 PERF_RB_STARVE_CYCLES_CCU = 8,
657 PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
658 PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
659 PERF_RB_Z_WORKLOAD = 11,
660 PERF_RB_HLSQ_ACTIVE = 12,
661 PERF_RB_Z_READ = 13,
662 PERF_RB_Z_WRITE = 14,
663 PERF_RB_C_READ = 15,
664 PERF_RB_C_WRITE = 16,
665 PERF_RB_TOTAL_PASS = 17,
666 PERF_RB_Z_PASS = 18,
667 PERF_RB_Z_FAIL = 19,
668 PERF_RB_S_FAIL = 20,
669 PERF_RB_BLENDED_FXP_COMPONENTS = 21,
670 PERF_RB_BLENDED_FP16_COMPONENTS = 22,
671 RB_RESERVED = 23,
672 PERF_RB_2D_ALIVE_CYCLES = 24,
673 PERF_RB_2D_STALL_CYCLES_A2D = 25,
674 PERF_RB_2D_STARVE_CYCLES_SRC = 26,
675 PERF_RB_2D_STARVE_CYCLES_SP = 27,
676 PERF_RB_2D_STARVE_CYCLES_DST = 28,
677 PERF_RB_2D_VALID_PIXELS = 29,
678 };
679
680 enum a5xx_rb_samples_perfcounter_select {
681 TOTAL_SAMPLES = 0,
682 ZPASS_SAMPLES = 1,
683 ZFAIL_SAMPLES = 2,
684 SFAIL_SAMPLES = 3,
685 };
686
687 enum a5xx_vsc_perfcounter_select {
688 PERF_VSC_BUSY_CYCLES = 0,
689 PERF_VSC_WORKING_CYCLES = 1,
690 PERF_VSC_STALL_CYCLES_UCHE = 2,
691 PERF_VSC_EOT_NUM = 3,
692 };
693
694 enum a5xx_ccu_perfcounter_select {
695 PERF_CCU_BUSY_CYCLES = 0,
696 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
697 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
698 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
699 PERF_CCU_DEPTH_BLOCKS = 4,
700 PERF_CCU_COLOR_BLOCKS = 5,
701 PERF_CCU_DEPTH_BLOCK_HIT = 6,
702 PERF_CCU_COLOR_BLOCK_HIT = 7,
703 PERF_CCU_PARTIAL_BLOCK_READ = 8,
704 PERF_CCU_GMEM_READ = 9,
705 PERF_CCU_GMEM_WRITE = 10,
706 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
707 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
708 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
709 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
710 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
711 PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
712 PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
713 PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
714 PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
715 PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
716 PERF_CCU_2D_BUSY_CYCLES = 21,
717 PERF_CCU_2D_RD_REQ = 22,
718 PERF_CCU_2D_WR_REQ = 23,
719 PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
720 PERF_CCU_2D_PIXELS = 25,
721 };
722
723 enum a5xx_cmp_perfcounter_select {
724 PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
725 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
726 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
727 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
728 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
729 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
730 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
731 PERF_CMPDECMP_VBIF_READ_DATA = 7,
732 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
733 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
734 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
735 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
736 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
737 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
738 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
739 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
740 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
741 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
742 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
743 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
744 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
745 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
746 PERF_CMPDECMP_2D_RD_DATA = 22,
747 PERF_CMPDECMP_2D_WR_DATA = 23,
748 };
749
750 enum a5xx_vbif_perfcounter_select {
751 AXI_READ_REQUESTS_ID_0 = 0,
752 AXI_READ_REQUESTS_ID_1 = 1,
753 AXI_READ_REQUESTS_ID_2 = 2,
754 AXI_READ_REQUESTS_ID_3 = 3,
755 AXI_READ_REQUESTS_ID_4 = 4,
756 AXI_READ_REQUESTS_ID_5 = 5,
757 AXI_READ_REQUESTS_ID_6 = 6,
758 AXI_READ_REQUESTS_ID_7 = 7,
759 AXI_READ_REQUESTS_ID_8 = 8,
760 AXI_READ_REQUESTS_ID_9 = 9,
761 AXI_READ_REQUESTS_ID_10 = 10,
762 AXI_READ_REQUESTS_ID_11 = 11,
763 AXI_READ_REQUESTS_ID_12 = 12,
764 AXI_READ_REQUESTS_ID_13 = 13,
765 AXI_READ_REQUESTS_ID_14 = 14,
766 AXI_READ_REQUESTS_ID_15 = 15,
767 AXI0_READ_REQUESTS_TOTAL = 16,
768 AXI1_READ_REQUESTS_TOTAL = 17,
769 AXI2_READ_REQUESTS_TOTAL = 18,
770 AXI3_READ_REQUESTS_TOTAL = 19,
771 AXI_READ_REQUESTS_TOTAL = 20,
772 AXI_WRITE_REQUESTS_ID_0 = 21,
773 AXI_WRITE_REQUESTS_ID_1 = 22,
774 AXI_WRITE_REQUESTS_ID_2 = 23,
775 AXI_WRITE_REQUESTS_ID_3 = 24,
776 AXI_WRITE_REQUESTS_ID_4 = 25,
777 AXI_WRITE_REQUESTS_ID_5 = 26,
778 AXI_WRITE_REQUESTS_ID_6 = 27,
779 AXI_WRITE_REQUESTS_ID_7 = 28,
780 AXI_WRITE_REQUESTS_ID_8 = 29,
781 AXI_WRITE_REQUESTS_ID_9 = 30,
782 AXI_WRITE_REQUESTS_ID_10 = 31,
783 AXI_WRITE_REQUESTS_ID_11 = 32,
784 AXI_WRITE_REQUESTS_ID_12 = 33,
785 AXI_WRITE_REQUESTS_ID_13 = 34,
786 AXI_WRITE_REQUESTS_ID_14 = 35,
787 AXI_WRITE_REQUESTS_ID_15 = 36,
788 AXI0_WRITE_REQUESTS_TOTAL = 37,
789 AXI1_WRITE_REQUESTS_TOTAL = 38,
790 AXI2_WRITE_REQUESTS_TOTAL = 39,
791 AXI3_WRITE_REQUESTS_TOTAL = 40,
792 AXI_WRITE_REQUESTS_TOTAL = 41,
793 AXI_TOTAL_REQUESTS = 42,
794 AXI_READ_DATA_BEATS_ID_0 = 43,
795 AXI_READ_DATA_BEATS_ID_1 = 44,
796 AXI_READ_DATA_BEATS_ID_2 = 45,
797 AXI_READ_DATA_BEATS_ID_3 = 46,
798 AXI_READ_DATA_BEATS_ID_4 = 47,
799 AXI_READ_DATA_BEATS_ID_5 = 48,
800 AXI_READ_DATA_BEATS_ID_6 = 49,
801 AXI_READ_DATA_BEATS_ID_7 = 50,
802 AXI_READ_DATA_BEATS_ID_8 = 51,
803 AXI_READ_DATA_BEATS_ID_9 = 52,
804 AXI_READ_DATA_BEATS_ID_10 = 53,
805 AXI_READ_DATA_BEATS_ID_11 = 54,
806 AXI_READ_DATA_BEATS_ID_12 = 55,
807 AXI_READ_DATA_BEATS_ID_13 = 56,
808 AXI_READ_DATA_BEATS_ID_14 = 57,
809 AXI_READ_DATA_BEATS_ID_15 = 58,
810 AXI0_READ_DATA_BEATS_TOTAL = 59,
811 AXI1_READ_DATA_BEATS_TOTAL = 60,
812 AXI2_READ_DATA_BEATS_TOTAL = 61,
813 AXI3_READ_DATA_BEATS_TOTAL = 62,
814 AXI_READ_DATA_BEATS_TOTAL = 63,
815 AXI_WRITE_DATA_BEATS_ID_0 = 64,
816 AXI_WRITE_DATA_BEATS_ID_1 = 65,
817 AXI_WRITE_DATA_BEATS_ID_2 = 66,
818 AXI_WRITE_DATA_BEATS_ID_3 = 67,
819 AXI_WRITE_DATA_BEATS_ID_4 = 68,
820 AXI_WRITE_DATA_BEATS_ID_5 = 69,
821 AXI_WRITE_DATA_BEATS_ID_6 = 70,
822 AXI_WRITE_DATA_BEATS_ID_7 = 71,
823 AXI_WRITE_DATA_BEATS_ID_8 = 72,
824 AXI_WRITE_DATA_BEATS_ID_9 = 73,
825 AXI_WRITE_DATA_BEATS_ID_10 = 74,
826 AXI_WRITE_DATA_BEATS_ID_11 = 75,
827 AXI_WRITE_DATA_BEATS_ID_12 = 76,
828 AXI_WRITE_DATA_BEATS_ID_13 = 77,
829 AXI_WRITE_DATA_BEATS_ID_14 = 78,
830 AXI_WRITE_DATA_BEATS_ID_15 = 79,
831 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
832 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
833 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
834 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
835 AXI_WRITE_DATA_BEATS_TOTAL = 84,
836 AXI_DATA_BEATS_TOTAL = 85,
837 };
838
839 enum a5xx_tex_filter {
840 A5XX_TEX_NEAREST = 0,
841 A5XX_TEX_LINEAR = 1,
842 A5XX_TEX_ANISO = 2,
843 };
844
845 enum a5xx_tex_clamp {
846 A5XX_TEX_REPEAT = 0,
847 A5XX_TEX_CLAMP_TO_EDGE = 1,
848 A5XX_TEX_MIRROR_REPEAT = 2,
849 A5XX_TEX_CLAMP_TO_BORDER = 3,
850 A5XX_TEX_MIRROR_CLAMP = 4,
851 };
852
853 enum a5xx_tex_aniso {
854 A5XX_TEX_ANISO_1 = 0,
855 A5XX_TEX_ANISO_2 = 1,
856 A5XX_TEX_ANISO_4 = 2,
857 A5XX_TEX_ANISO_8 = 3,
858 A5XX_TEX_ANISO_16 = 4,
859 };
860
861 enum a5xx_tex_swiz {
862 A5XX_TEX_X = 0,
863 A5XX_TEX_Y = 1,
864 A5XX_TEX_Z = 2,
865 A5XX_TEX_W = 3,
866 A5XX_TEX_ZERO = 4,
867 A5XX_TEX_ONE = 5,
868 };
869
870 enum a5xx_tex_type {
871 A5XX_TEX_1D = 0,
872 A5XX_TEX_2D = 1,
873 A5XX_TEX_CUBE = 2,
874 A5XX_TEX_3D = 3,
875 };
876
877 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
878 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
879 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
880 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
881 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
882 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
883 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
884 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
885 #define A5XX_INT0_CP_SW 0x00000100
886 #define A5XX_INT0_CP_HW_ERROR 0x00000200
887 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
888 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
889 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
890 #define A5XX_INT0_CP_IB2 0x00002000
891 #define A5XX_INT0_CP_IB1 0x00004000
892 #define A5XX_INT0_CP_RB 0x00008000
893 #define A5XX_INT0_CP_UNUSED_1 0x00010000
894 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000
895 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000
896 #define A5XX_INT0_UNKNOWN_1 0x00080000
897 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
898 #define A5XX_INT0_UNUSED_2 0x00200000
899 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
900 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000
901 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
902 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
903 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000
904 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000
905 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
906 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000
907 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
908 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
909 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
910 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
911 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
912 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
913 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
914 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
915 #define REG_A5XX_CP_RB_BASE 0x00000800
916
917 #define REG_A5XX_CP_RB_BASE_HI 0x00000801
918
919 #define REG_A5XX_CP_RB_CNTL 0x00000802
920
921 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
922
923 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
924
925 #define REG_A5XX_CP_RB_RPTR 0x00000806
926
927 #define REG_A5XX_CP_RB_WPTR 0x00000807
928
929 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
930
931 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
932
933 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
934
935 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
936
937 #define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d
938
939 #define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e
940
941 #define REG_A5XX_CP_ME_NRT_DATA 0x00000810
942
943 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
944
945 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
946
947 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
948
949 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
950
951 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
952
953 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
954
955 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
956
957 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
958
959 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
960
961 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
962
963 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
964
965 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826
966
967 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
968
969 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
970
971 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
972
973 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
974
975 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
976
977 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
978
979 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
980
981 #define REG_A5XX_CP_CNTL 0x00000831
982
983 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
984
985 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833
986
987 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
988
989 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
990
991 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
992
993 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
994
995 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
996
997 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
998
999 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
1000
1001 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
1002
1003 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
1004
1005 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
1006
1007 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
1008
1009 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
1010
1011 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
1012
1013 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
1014
1015 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
1016
1017 #define REG_A5XX_CP_HW_FAULT 0x00000b1a
1018
1019 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
1020
1021 #define REG_A5XX_CP_IB1_BASE 0x00000b1f
1022
1023 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
1024
1025 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
1026
1027 #define REG_A5XX_CP_IB2_BASE 0x00000b22
1028
1029 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
1030
1031 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
1032
1033 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1034
1035 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1036
1037 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1038
1039 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1040 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
1041 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
1042 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1043 {
1044 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1045 }
1046 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
1047 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
1048 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1049 {
1050 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
1051 }
1052 #define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
1053 #define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29
1054 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
1055 {
1056 return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
1057 }
1058 #define A5XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
1059 #define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30
1060 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
1061 {
1062 return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK;
1063 }
1064
1065 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
1066
1067 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b
1068
1069 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
1070
1071 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
1072
1073 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
1074
1075 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
1076
1077 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
1078
1079 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
1080
1081 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
1082
1083 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
1084
1085 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
1086
1087 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
1088
1089 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
1090
1091 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
1092
1093 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
1094
1095 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
1096
1097 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
1098
1099 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
1100
1101 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
1102
1103 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
1104
1105 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
1106
1107 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
1108
1109 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
1110
1111 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
1112
1113 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
1114
1115 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
1116
1117 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
1118
1119 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
1120
1121 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
1122
1123 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
1124
1125 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
1126
1127 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
1128
1129 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
1130
1131 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
1132
1133 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
1134
1135 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
1136
1137 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
1138
1139 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
1140
1141 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
1142
1143 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
1144
1145 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
1146
1147 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
1148
1149 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
1150
1151 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
1152
1153 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
1154
1155 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
1156
1157 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
1158
1159 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
1160
1161 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
1162
1163 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
1164
1165 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
1166
1167 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038
1168 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
1169 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
1170 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
1171 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
1172 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
1173 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
1174 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
1175 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
1176 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
1177 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
1178 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
1179 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
1180 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
1181 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
1182 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
1183 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
1184 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
1185 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
1186 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
1187 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
1188 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
1189 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
1190 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
1191 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
1192 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
1193 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
1194 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
1195 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
1196 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
1197
1198 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
1199
1200 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
1201
1202 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
1203
1204 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1205
1206 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1207
1208 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
1209
1210 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
1211
1212 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
1213
1214 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
1215
1216 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
1217
1218 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
1219
1220 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
1221
1222 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
1223
1224 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
1225
1226 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
1227
1228 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
1229
1230 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
1231
1232 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
1233
1234 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
1235
1236 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
1237
1238 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
1239
1240 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
1241
1242 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
1243
1244 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
1245
1246 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
1247
1248 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
1249
1250 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
1251
1252 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
1253
1254 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
1255
1256 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
1257
1258 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
1259
1260 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
1261
1262 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
1263
1264 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
1265
1266 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
1267
1268 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
1269
1270 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
1271
1272 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
1273
1274 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
1275
1276 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
1277
1278 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
1279
1280 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
1281
1282 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
1283
1284 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
1285
1286 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
1287
1288 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
1289
1290 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
1291
1292 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
1293
1294 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
1295
1296 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
1297
1298 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
1299
1300 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
1301
1302 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
1303
1304 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
1305
1306 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
1307
1308 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
1309
1310 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
1311
1312 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
1313
1314 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
1315
1316 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
1317
1318 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
1319
1320 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
1321
1322 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
1323
1324 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
1325
1326 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
1327
1328 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
1329
1330 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
1331
1332 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
1333
1334 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
1335
1336 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
1337
1338 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
1339
1340 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
1341
1342 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
1343
1344 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
1345
1346 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
1347
1348 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
1349
1350 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
1351
1352 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
1353
1354 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
1355
1356 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
1357
1358 #define REG_A5XX_RBBM_AHB_CMD 0x00000096
1359
1360 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
1361
1362 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
1363
1364 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
1365
1366 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
1367
1368 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
1369
1370 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
1371
1372 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
1373
1374 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
1375
1376 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
1377
1378 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
1379
1380 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
1381
1382 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
1383
1384 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
1385
1386 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
1387
1388 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
1389
1390 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
1391
1392 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
1393
1394 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
1395
1396 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
1397
1398 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
1399
1400 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
1401
1402 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
1403
1404 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
1405
1406 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
1407
1408 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
1409
1410 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
1411
1412 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
1413
1414 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
1415
1416 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
1417
1418 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
1419
1420 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
1421
1422 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
1423
1424 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
1425
1426 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
1427
1428 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
1429
1430 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
1431
1432 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
1433
1434 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
1435
1436 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
1437
1438 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
1439
1440 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
1441
1442 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
1443
1444 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
1445
1446 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
1447
1448 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
1449
1450 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
1451
1452 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
1453
1454 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
1455
1456 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
1457
1458 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
1459
1460 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
1461
1462 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
1463
1464 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
1465
1466 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
1467
1468 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
1469
1470 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
1471
1472 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
1473
1474 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
1475
1476 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
1477
1478 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
1479
1480 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
1481
1482 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
1483
1484 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
1485
1486 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
1487
1488 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
1489
1490 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
1491
1492 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
1493
1494 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
1495
1496 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
1497
1498 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
1499
1500 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
1501
1502 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
1503
1504 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
1505
1506 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
1507
1508 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
1509
1510 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
1511
1512 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
1513
1514 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
1515
1516 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
1517
1518 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
1519
1520 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
1521
1522 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
1523
1524 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
1525
1526 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
1527
1528 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
1529
1530 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
1531
1532 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
1533
1534 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
1535
1536 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
1537
1538 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
1539
1540 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
1541
1542 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
1543
1544 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
1545
1546 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
1547
1548 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
1549
1550 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
1551
1552 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
1553
1554 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
1555
1556 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
1557
1558 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
1559
1560 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
1561
1562 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
1563
1564 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
1565
1566 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
1567
1568 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
1569
1570 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
1571
1572 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
1573
1574 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
1575
1576 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
1577
1578 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
1579
1580 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
1581
1582 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
1583
1584 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
1585
1586 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
1587
1588 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
1589
1590 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
1591
1592 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
1593
1594 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
1595
1596 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
1597
1598 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
1599
1600 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
1601
1602 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
1603
1604 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
1605
1606 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
1607
1608 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
1609
1610 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
1611
1612 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
1613
1614 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
1615
1616 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
1617
1618 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
1619
1620 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
1621
1622 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
1623
1624 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
1625
1626 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
1627
1628 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
1629
1630 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
1631
1632 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
1633
1634 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
1635
1636 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
1637
1638 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
1639
1640 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
1641
1642 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
1643
1644 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
1645
1646 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
1647
1648 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
1649
1650 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
1651
1652 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
1653
1654 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
1655
1656 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
1657
1658 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
1659
1660 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
1661
1662 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
1663
1664 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
1665
1666 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
1667
1668 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
1669
1670 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1671
1672 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1673
1674 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1675
1676 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1677
1678 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1679
1680 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1681
1682 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1683
1684 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1685
1686 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1687
1688 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1689
1690 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1691
1692 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1693
1694 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1695
1696 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1697
1698 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1699
1700 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1701
1702 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1703
1704 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1705
1706 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1707
1708 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1709
1710 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1711
1712 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1713
1714 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1715
1716 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1717
1718 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1719
1720 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1721
1722 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1723
1724 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1725
1726 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1727
1728 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1729
1730 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1731
1732 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1733
1734 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1735
1736 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1737
1738 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1739
1740 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1741
1742 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1743
1744 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1745
1746 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1747
1748 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1749
1750 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1751
1752 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1753
1754 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1755
1756 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1757
1758 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1759
1760 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1761
1762 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1763
1764 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1765
1766 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1767
1768 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1769
1770 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1771
1772 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1773
1774 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1775
1776 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1777
1778 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1779
1780 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1781
1782 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1783
1784 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1785
1786 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1787
1788 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1789
1790 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1791
1792 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1793
1794 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1795
1796 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1797
1798 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1799
1800 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1801
1802 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1803
1804 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1805
1806 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1807
1808 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1809
1810 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1811
1812 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1813
1814 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1815
1816 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1817
1818 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1819
1820 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1821
1822 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1823
1824 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1825
1826 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1827
1828 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1829
1830 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1831
1832 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1833
1834 #define REG_A5XX_RBBM_STATUS 0x000004f5
1835 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK 0x80000000
1836 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT 31
1837 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)
1838 {
1839 return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK;
1840 }
1841 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK 0x40000000
1842 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT 30
1843 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)
1844 {
1845 return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK;
1846 }
1847 #define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK 0x20000000
1848 #define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT 29
1849 static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)
1850 {
1851 return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK;
1852 }
1853 #define A5XX_RBBM_STATUS_VSC_BUSY__MASK 0x10000000
1854 #define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT 28
1855 static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)
1856 {
1857 return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK;
1858 }
1859 #define A5XX_RBBM_STATUS_TPL1_BUSY__MASK 0x08000000
1860 #define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT 27
1861 static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)
1862 {
1863 return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK;
1864 }
1865 #define A5XX_RBBM_STATUS_SP_BUSY__MASK 0x04000000
1866 #define A5XX_RBBM_STATUS_SP_BUSY__SHIFT 26
1867 static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)
1868 {
1869 return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK;
1870 }
1871 #define A5XX_RBBM_STATUS_UCHE_BUSY__MASK 0x02000000
1872 #define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT 25
1873 static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)
1874 {
1875 return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK;
1876 }
1877 #define A5XX_RBBM_STATUS_VPC_BUSY__MASK 0x01000000
1878 #define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT 24
1879 static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)
1880 {
1881 return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK;
1882 }
1883 #define A5XX_RBBM_STATUS_VFDP_BUSY__MASK 0x00800000
1884 #define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT 23
1885 static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)
1886 {
1887 return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK;
1888 }
1889 #define A5XX_RBBM_STATUS_VFD_BUSY__MASK 0x00400000
1890 #define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT 22
1891 static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)
1892 {
1893 return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK;
1894 }
1895 #define A5XX_RBBM_STATUS_TESS_BUSY__MASK 0x00200000
1896 #define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT 21
1897 static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)
1898 {
1899 return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK;
1900 }
1901 #define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK 0x00100000
1902 #define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT 20
1903 static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)
1904 {
1905 return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK;
1906 }
1907 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK 0x00080000
1908 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT 19
1909 static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)
1910 {
1911 return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK;
1912 }
1913 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK 0x00040000
1914 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT 18
1915 static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)
1916 {
1917 return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK;
1918 }
1919 #define A5XX_RBBM_STATUS_DCOM_BUSY__MASK 0x00020000
1920 #define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT 17
1921 static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)
1922 {
1923 return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK;
1924 }
1925 #define A5XX_RBBM_STATUS_COM_BUSY__MASK 0x00010000
1926 #define A5XX_RBBM_STATUS_COM_BUSY__SHIFT 16
1927 static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)
1928 {
1929 return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK;
1930 }
1931 #define A5XX_RBBM_STATUS_LRZ_BUZY__MASK 0x00008000
1932 #define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT 15
1933 static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)
1934 {
1935 return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK;
1936 }
1937 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK 0x00004000
1938 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT 14
1939 static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)
1940 {
1941 return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK;
1942 }
1943 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK 0x00002000
1944 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT 13
1945 static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)
1946 {
1947 return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK;
1948 }
1949 #define A5XX_RBBM_STATUS_RB_BUSY__MASK 0x00001000
1950 #define A5XX_RBBM_STATUS_RB_BUSY__SHIFT 12
1951 static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)
1952 {
1953 return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK;
1954 }
1955 #define A5XX_RBBM_STATUS_RAS_BUSY__MASK 0x00000800
1956 #define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT 11
1957 static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)
1958 {
1959 return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK;
1960 }
1961 #define A5XX_RBBM_STATUS_TSE_BUSY__MASK 0x00000400
1962 #define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT 10
1963 static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)
1964 {
1965 return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK;
1966 }
1967 #define A5XX_RBBM_STATUS_VBIF_BUSY__MASK 0x00000200
1968 #define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT 9
1969 static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)
1970 {
1971 return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK;
1972 }
1973 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK 0x00000100
1974 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT 8
1975 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)
1976 {
1977 return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK;
1978 }
1979 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK 0x00000080
1980 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT 7
1981 static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)
1982 {
1983 return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK;
1984 }
1985 #define A5XX_RBBM_STATUS_CP_BUSY__MASK 0x00000040
1986 #define A5XX_RBBM_STATUS_CP_BUSY__SHIFT 6
1987 static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)
1988 {
1989 return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK;
1990 }
1991 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK 0x00000020
1992 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT 5
1993 static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)
1994 {
1995 return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK;
1996 }
1997 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK 0x00000010
1998 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT 4
1999 static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)
2000 {
2001 return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK;
2002 }
2003 #define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK 0x00000008
2004 #define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT 3
2005 static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)
2006 {
2007 return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK;
2008 }
2009 #define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK 0x00000004
2010 #define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT 2
2011 static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)
2012 {
2013 return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK;
2014 }
2015 #define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK 0x00000002
2016 #define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1
2017 static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
2018 {
2019 return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
2020 }
2021 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
2022
2023 #define REG_A5XX_RBBM_STATUS3 0x00000530
2024
2025 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
2026
2027 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
2028
2029 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
2030
2031 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
2032
2033 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
2034
2035 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
2036
2037 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
2038
2039 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
2040
2041 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
2042
2043 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
2044
2045 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
2046
2047 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
2048
2049 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
2050
2051 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
2052
2053 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
2054
2055 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
2056
2057 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
2058
2059 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
2060
2061 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
2062
2063 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
2064
2065 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
2066
2067 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
2068
2069 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
2070
2071 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
2072
2073 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
2074
2075 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
2076
2077 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
2078
2079 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
2080
2081 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
2082
2083 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
2084
2085 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533
2086
2087 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
2088
2089 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
2090
2091 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
2092
2093 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
2094
2095 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
2096
2097 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
2098
2099 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
2100
2101 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
2102
2103 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
2104
2105 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
2106
2107 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
2108
2109 #define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
2110 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2111 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2112 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2113 {
2114 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
2115 }
2116 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
2117 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
2118 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2119 {
2120 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
2121 }
2122
2123 #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
2124
2125 #define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
2126
2127 #define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
2128
2129 #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
2130
2131 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
2132
2133 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
2134 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2135 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
2136 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2137 {
2138 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
2139 }
2140 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2141 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
2142 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2143 {
2144 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2145 }
2146 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
2147 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
2148 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2149 {
2150 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
2151 }
2152 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
2153 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
2154 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2155 {
2156 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
2157 }
2158
2159 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2160
2161 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2162
2163 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
2164
2165 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2166
2167 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2168
2169 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
2170
2171 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
2172
2173 #define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
2174 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
2175 #define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
2176 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
2177 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
2178 {
2179 return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
2180 }
2181 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
2182 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
2183 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
2184 {
2185 return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
2186 }
2187
2188 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
2189
2190 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
2191
2192 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
2193
2194 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
2195
2196 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
2197
2198 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
2199
2200 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
2201
2202 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
2203
2204 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
2205
2206 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
2207
2208 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
2209
2210 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
2211
2212 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
2213
2214 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
2215
2216 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
2217
2218 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6
2219
2220 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7
2221
2222 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
2223
2224 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
2225
2226 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
2227
2228 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
2229
2230 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
2231
2232 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
2233
2234 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
2235
2236 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
2237
2238 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
2239
2240 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
2241
2242 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
2243
2244 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
2245
2246 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
2247
2248 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
2249
2250 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
2251
2252 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
2253
2254 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
2255
2256 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
2257
2258 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
2259
2260 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
2261
2262 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
2263
2264 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
2265
2266 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
2267 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
2268
2269 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
2270
2271 #define REG_A5XX_PC_MODE_CNTL 0x00000d02
2272
2273 #define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04
2274
2275 #define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05
2276
2277 #define REG_A5XX_PC_START_INDEX 0x00000d06
2278
2279 #define REG_A5XX_PC_MAX_INDEX 0x00000d07
2280
2281 #define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08
2282
2283 #define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09
2284
2285 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2286
2287 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
2288
2289 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
2290
2291 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
2292
2293 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
2294
2295 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
2296
2297 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
2298
2299 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2300
2301 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
2302
2303 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
2304
2305 #define REG_A5XX_HLSQ_DBG_ECO_CNTL 0x00000e04
2306
2307 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
2308
2309 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
2310
2311 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
2312
2313 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
2314
2315 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
2316
2317 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
2318
2319 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
2320
2321 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
2322
2323 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
2324
2325 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
2326
2327 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
2328
2329 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
2330
2331 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
2332
2333 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
2334
2335 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42
2336
2337 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
2338
2339 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
2340
2341 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
2342
2343 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
2344
2345 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
2346
2347 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
2348
2349 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
2350
2351 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
2352
2353 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2354
2355 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
2356
2357 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62
2358 #define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
2359
2360 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
2361
2362 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
2363
2364 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
2365
2366 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
2367
2368 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
2369
2370 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
2371
2372 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
2373
2374 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
2375
2376 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
2377
2378 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
2379
2380 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
2381
2382 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
2383
2384 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
2385
2386 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
2387
2388 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
2389
2390 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
2391
2392 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
2393
2394 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
2395
2396 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
2397
2398 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
2399
2400 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
2401
2402 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
2403
2404 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
2405
2406 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
2407
2408 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
2409
2410 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
2411
2412 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
2413
2414 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
2415
2416 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
2417
2418 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
2419
2420 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
2421
2422 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
2423
2424 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
2425
2426 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
2427
2428 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
2429
2430 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
2431
2432 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
2433
2434 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
2435
2436 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2
2437
2438 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
2439
2440 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
2441
2442 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
2443
2444 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
2445
2446 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
2447
2448 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
2449
2450 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
2451
2452 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
2453
2454 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
2455
2456 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
2457
2458 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
2459
2460 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
2461
2462 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
2463
2464 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
2465
2466 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
2467
2468 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
2469
2470 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
2471
2472 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
2473
2474 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
2475
2476 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
2477
2478 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
2479
2480 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
2481
2482 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
2483
2484 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
2485
2486 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
2487
2488 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
2489
2490 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
2491
2492 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
2493
2494 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
2495
2496 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
2497
2498 #define REG_A5XX_VBIF_VERSION 0x00003000
2499
2500 #define REG_A5XX_VBIF_CLKON 0x00003001
2501
2502 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028
2503
2504 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
2505
2506 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2507
2508 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2509
2510 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2511
2512 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2513
2514 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
2515
2516 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
2517
2518 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
2519
2520 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
2521
2522 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
2523
2524 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
2525
2526 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
2527
2528 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
2529
2530 #define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0
2531
2532 #define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1
2533
2534 #define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2
2535
2536 #define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
2537
2538 #define REG_A5XX_VBIF_PERF_CNT_CLR0 0x000030c8
2539
2540 #define REG_A5XX_VBIF_PERF_CNT_CLR1 0x000030c9
2541
2542 #define REG_A5XX_VBIF_PERF_CNT_CLR2 0x000030ca
2543
2544 #define REG_A5XX_VBIF_PERF_CNT_CLR3 0x000030cb
2545
2546 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
2547
2548 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
2549
2550 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
2551
2552 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
2553
2554 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
2555
2556 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
2557
2558 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
2559
2560 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
2561
2562 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
2563
2564 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
2565
2566 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
2567
2568 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
2569
2570 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
2571
2572 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
2573
2574 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
2575
2576 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
2577
2578 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
2579
2580 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2581
2582 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2583
2584 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2585
2586 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2587
2588 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
2589
2590 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
2591
2592 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
2593
2594 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
2595
2596 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
2597
2598 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
2599 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
2600
2601 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
2602 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
2603
2604 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
2605
2606 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
2607
2608 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
2609
2610 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
2611
2612 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
2613
2614 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
2615
2616 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
2617
2618 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
2619
2620 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
2621
2622 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
2623
2624 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
2625
2626 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
2627
2628 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
2629
2630 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
2631
2632 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
2633
2634 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
2635
2636 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
2637
2638 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
2639
2640 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
2641
2642 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
2643
2644 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
2645
2646 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
2647
2648 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
2649
2650 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
2651
2652 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
2653
2654 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
2655
2656 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
2657
2658 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
2659
2660 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
2661
2662 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
2663
2664 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
2665
2666 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
2667
2668 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
2669
2670 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
2671
2672 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
2673
2674 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
2675
2676 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
2677
2678 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
2679
2680 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
2681
2682 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
2683
2684 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
2685
2686 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
2687
2688 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
2689
2690 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
2691
2692 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
2693
2694 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
2695
2696 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
2697
2698 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
2699
2700 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
2701
2702 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
2703
2704 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
2705
2706 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
2707
2708 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
2709
2710 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
2711
2712 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
2713
2714 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
2715
2716 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
2717
2718 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
2719
2720 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
2721
2722 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
2723
2724 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
2725
2726 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
2727
2728 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
2729
2730 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
2731
2732 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
2733
2734 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
2735
2736 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
2737
2738 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
2739
2740 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
2741
2742 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
2743
2744 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
2745
2746 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
2747
2748 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
2749
2750 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
2751
2752 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
2753
2754 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
2755
2756 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
2757
2758 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
2759
2760 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
2761
2762 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
2763
2764 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
2765
2766 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
2767
2768 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
2769
2770 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
2771
2772 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
2773
2774 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
2775
2776 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
2777
2778 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
2779
2780 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
2781
2782 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
2783
2784 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c
2785
2786 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d
2787
2788 #define REG_A5XX_GDPM_INT_EN 0x0000b80f
2789
2790 #define REG_A5XX_GDPM_INT_MASK 0x0000b811
2791
2792 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
2793
2794 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
2795
2796 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
2797
2798 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
2799
2800 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
2801
2802 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
2803
2804 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
2805
2806 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2807 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2808
2809 #define REG_A5XX_UNKNOWN_E001 0x0000e001
2810
2811 #define REG_A5XX_UNKNOWN_E004 0x0000e004
2812
2813 #define REG_A5XX_GRAS_CNTL 0x0000e005
2814 #define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2815 #define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2816 #define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2817 #define A5XX_GRAS_CNTL_SIZE 0x00000008
2818 #define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
2819 #define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6
2820 static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2821 {
2822 return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
2823 }
2824
2825 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
2826 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
2827 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
2828 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2829 {
2830 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2831 }
2832 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
2833 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
2834 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2835 {
2836 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2837 }
2838
2839 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
2840 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2841 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2842 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2843 {
2844 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2845 }
2846
2847 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
2848 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2849 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2850 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
2851 {
2852 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2853 }
2854
2855 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
2856 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2857 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2858 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2859 {
2860 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2861 }
2862
2863 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
2864 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2865 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2866 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
2867 {
2868 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2869 }
2870
2871 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
2872 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2873 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2874 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2875 {
2876 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2877 }
2878
2879 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
2880 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2881 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2882 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2883 {
2884 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2885 }
2886
2887 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090
2888 #define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2889 #define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2890 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2891 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2892 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2893 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2894 {
2895 return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2896 }
2897 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2898 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2899
2900 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
2901 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2902 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2903 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2904 {
2905 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2906 }
2907 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2908 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2909 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2910 {
2911 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2912 }
2913
2914 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2915 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2916 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
2917 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2918 {
2919 return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2920 }
2921
2922 #define REG_A5XX_GRAS_SU_LAYERED 0x0000e093
2923
2924 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2925 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2926 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
2927
2928 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2929 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2930 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2931 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2932 {
2933 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2934 }
2935
2936 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2937 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2938 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2939 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2940 {
2941 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2942 }
2943
2944 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2945 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2946 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2947 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2948 {
2949 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2950 }
2951
2952 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2953 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2954 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2955 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2956 {
2957 return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2958 }
2959
2960 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2961
2962 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2963 #define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
2964 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2965
2966 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2967
2968 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2969 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2970 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2971 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2972 {
2973 return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2974 }
2975
2976 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2977 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2978 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2979 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2980 {
2981 return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
2982 }
2983 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2984
2985 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
2986
2987 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
2988 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2989 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2990 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2991 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2992 {
2993 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2994 }
2995 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2996 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2997 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2998 {
2999 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
3000 }
3001
3002 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
3003 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
3004 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
3005 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
3006 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
3007 {
3008 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
3009 }
3010 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
3011 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
3012 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
3013 {
3014 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
3015 }
3016
3017 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
3018 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
3019 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
3020 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
3021 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
3022 {
3023 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
3024 }
3025 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
3026 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
3027 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
3028 {
3029 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
3030 }
3031
3032 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
3033 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
3034 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
3035 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
3036 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
3037 {
3038 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
3039 }
3040 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
3041 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
3042 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
3043 {
3044 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
3045 }
3046
3047 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
3048 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3049 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
3050 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
3051 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3052 {
3053 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3054 }
3055 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
3056 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
3057 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3058 {
3059 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3060 }
3061
3062 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
3063 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3064 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
3065 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
3066 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3067 {
3068 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3069 }
3070 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
3071 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
3072 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3073 {
3074 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3075 }
3076
3077 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
3078 #define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
3079 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
3080 #define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004
3081
3082 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
3083
3084 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
3085
3086 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
3087 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff
3088 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
3089 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
3090 {
3091 return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
3092 }
3093
3094 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
3095
3096 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
3097
3098 #define REG_A5XX_RB_CNTL 0x0000e140
3099 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
3100 #define A5XX_RB_CNTL_WIDTH__SHIFT 0
3101 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
3102 {
3103 return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
3104 }
3105 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
3106 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9
3107 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
3108 {
3109 return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
3110 }
3111 #define A5XX_RB_CNTL_BYPASS 0x00020000
3112
3113 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141
3114 #define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
3115 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
3116 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
3117 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
3118 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
3119 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
3120 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
3121 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3122 {
3123 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3124 }
3125 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
3126 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
3127 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
3128 {
3129 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
3130 }
3131
3132 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
3133 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3134 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
3135 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3136 {
3137 return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3138 }
3139
3140 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
3141 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3142 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
3143 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3144 {
3145 return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3146 }
3147 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3148
3149 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
3150 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
3151 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
3152 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
3153 #define A5XX_RB_RENDER_CONTROL0_SIZE 0x00000008
3154 #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
3155 #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
3156 static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3157 {
3158 return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3159 }
3160
3161 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
3162 #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
3163 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
3164 #define A5XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000004
3165
3166 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
3167 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
3168 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
3169 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
3170 {
3171 return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
3172 }
3173 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
3174
3175 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
3176 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
3177 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
3178 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3179 {
3180 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
3181 }
3182 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3183 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
3184 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3185 {
3186 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
3187 }
3188 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3189 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
3190 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3191 {
3192 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
3193 }
3194 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3195 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
3196 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3197 {
3198 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
3199 }
3200 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3201 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
3202 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3203 {
3204 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
3205 }
3206 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3207 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
3208 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3209 {
3210 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
3211 }
3212 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3213 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
3214 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3215 {
3216 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
3217 }
3218 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3219 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
3220 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3221 {
3222 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
3223 }
3224
3225 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3226
3227 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3228 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
3229 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
3230 #define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3231 #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3232 #define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
3233 static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3234 {
3235 return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3236 }
3237 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3238 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
3239 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3240 {
3241 return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3242 }
3243
3244 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
3245 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3246 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
3247 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3248 {
3249 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3250 }
3251 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3252 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
3253 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3254 {
3255 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3256 }
3257 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3258 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
3259 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3260 {
3261 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3262 }
3263 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3264 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
3265 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3266 {
3267 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3268 }
3269 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3270 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
3271 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3272 {
3273 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3274 }
3275 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3276 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
3277 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3278 {
3279 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3280 }
3281
3282 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
3283 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3284 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
3285 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3286 {
3287 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3288 }
3289 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3290 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
3291 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
3292 {
3293 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3294 }
3295 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00001800
3296 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 11
3297 static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
3298 {
3299 return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
3300 }
3301 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3302 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
3303 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3304 {
3305 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3306 }
3307 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
3308
3309 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
3310 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff
3311 #define A5XX_RB_MRT_PITCH__SHIFT 0
3312 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
3313 {
3314 return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
3315 }
3316
3317 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
3318 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
3319 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
3320 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3321 {
3322 return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
3323 }
3324
3325 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
3326
3327 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
3328
3329 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0
3330 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
3331 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0
3332 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
3333 {
3334 return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
3335 }
3336 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
3337 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8
3338 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3339 {
3340 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3341 }
3342 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
3343 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
3344 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3345 {
3346 return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3347 }
3348
3349 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
3350 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
3351 #define A5XX_RB_BLEND_RED_F32__SHIFT 0
3352 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3353 {
3354 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
3355 }
3356
3357 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
3358 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
3359 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
3360 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
3361 {
3362 return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
3363 }
3364 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
3365 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
3366 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3367 {
3368 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3369 }
3370 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
3371 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
3372 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3373 {
3374 return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3375 }
3376
3377 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
3378 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3379 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
3380 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3381 {
3382 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
3383 }
3384
3385 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
3386 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
3387 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
3388 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
3389 {
3390 return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
3391 }
3392 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
3393 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
3394 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3395 {
3396 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3397 }
3398 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
3399 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
3400 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3401 {
3402 return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3403 }
3404
3405 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
3406 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3407 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
3408 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3409 {
3410 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
3411 }
3412
3413 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
3414 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
3415 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
3416 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
3417 {
3418 return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
3419 }
3420 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
3421 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
3422 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3423 {
3424 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3425 }
3426 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
3427 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
3428 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3429 {
3430 return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3431 }
3432
3433 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
3434 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3435 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
3436 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3437 {
3438 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
3439 }
3440
3441 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
3442 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3443 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
3444 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3445 {
3446 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3447 }
3448 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3449 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3450 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
3451 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3452 {
3453 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3454 }
3455
3456 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
3457 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3458 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
3459 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3460 {
3461 return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3462 }
3463 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3464 #define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3465 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3466 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
3467 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3468 {
3469 return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3470 }
3471
3472 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
3473 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
3474 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
3475
3476 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
3477 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
3478 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3479 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3480 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
3481 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3482 {
3483 return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3484 }
3485 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
3486
3487 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
3488 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3489 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
3490 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
3491 {
3492 return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3493 }
3494
3495 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
3496
3497 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
3498
3499 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
3500 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
3501 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
3502 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3503 {
3504 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
3505 }
3506
3507 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
3508 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3509 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
3510 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3511 {
3512 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3513 }
3514
3515 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
3516 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3517 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3518 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3519 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3520 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
3521 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3522 {
3523 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
3524 }
3525 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3526 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
3527 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3528 {
3529 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
3530 }
3531 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3532 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
3533 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3534 {
3535 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3536 }
3537 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3538 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
3539 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3540 {
3541 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3542 }
3543 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3544 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
3545 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3546 {
3547 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3548 }
3549 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3550 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
3551 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3552 {
3553 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3554 }
3555 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3556 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
3557 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3558 {
3559 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3560 }
3561 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3562 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
3563 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3564 {
3565 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3566 }
3567
3568 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
3569 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3570
3571 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
3572
3573 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
3574
3575 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
3576 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
3577 #define A5XX_RB_STENCIL_PITCH__SHIFT 0
3578 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
3579 {
3580 return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
3581 }
3582
3583 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
3584 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
3585 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
3586 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
3587 {
3588 return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
3589 }
3590
3591 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
3592 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
3593 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
3594 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
3595 {
3596 return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
3597 }
3598 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
3599 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
3600 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
3601 {
3602 return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
3603 }
3604 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
3605 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
3606 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
3607 {
3608 return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
3609 }
3610
3611 #define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7
3612 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
3613 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
3614 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
3615 {
3616 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
3617 }
3618 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
3619 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
3620 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
3621 {
3622 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
3623 }
3624 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
3625 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
3626 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
3627 {
3628 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
3629 }
3630
3631 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
3632 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
3633 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
3634 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
3635 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
3636 {
3637 return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
3638 }
3639 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
3640 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
3641 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3642 {
3643 return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
3644 }
3645
3646 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
3647 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3648
3649 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210
3650 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
3651 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
3652 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
3653 {
3654 return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
3655 }
3656
3657 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
3658 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
3659 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
3660 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
3661 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
3662 {
3663 return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
3664 }
3665 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
3666 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
3667 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
3668 {
3669 return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
3670 }
3671
3672 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
3673 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
3674 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
3675 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
3676 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
3677 {
3678 return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
3679 }
3680 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
3681 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
3682 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
3683 {
3684 return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
3685 }
3686
3687 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
3688 #define A5XX_RB_RESOLVE_CNTL_3_TILED 0x00000001
3689
3690 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
3691
3692 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
3693
3694 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
3695 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
3696 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
3697 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
3698 {
3699 return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
3700 }
3701
3702 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
3703 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
3704 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
3705 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3706 {
3707 return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3708 }
3709
3710 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
3711
3712 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
3713
3714 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
3715
3716 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
3717
3718 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
3719 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
3720 #define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE 0x00000004
3721 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
3722 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
3723 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
3724 {
3725 return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
3726 }
3727
3728 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
3729
3730 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
3731
3732 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
3733
3734 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3735
3736 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3737
3738 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
3739
3740 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
3741 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
3742 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
3743 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
3744 {
3745 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
3746 }
3747
3748 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
3749 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3750 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
3751 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
3752 {
3753 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
3754 }
3755
3756 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
3757
3758 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
3759
3760 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
3761 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
3762 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
3763 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
3764 {
3765 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
3766 }
3767
3768 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
3769 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
3770 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
3771 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
3772 {
3773 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
3774 }
3775
3776 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
3777
3778 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
3779
3780 #define REG_A5XX_VPC_CNTL_0 0x0000e280
3781 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
3782 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
3783 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
3784 {
3785 return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
3786 }
3787 #define A5XX_VPC_CNTL_0_VARYING 0x00000800
3788
3789 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3790
3791 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3792
3793 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3794
3795 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3796
3797 #define REG_A5XX_UNKNOWN_E292 0x0000e292
3798
3799 #define REG_A5XX_UNKNOWN_E293 0x0000e293
3800
3801 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3802
3803 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3804
3805 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
3806
3807 #define REG_A5XX_UNKNOWN_E29A 0x0000e29a
3808
3809 #define REG_A5XX_VPC_PACK 0x0000e29d
3810 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
3811 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
3812 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3813 {
3814 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3815 }
3816 #define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
3817 #define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
3818 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
3819 {
3820 return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
3821 }
3822
3823 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
3824
3825 #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
3826 #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
3827 #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
3828 #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
3829 #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
3830 #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
3831
3832 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
3833 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
3834
3835 #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
3836 #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
3837
3838 #define REG_A5XX_VPC_SO_PROG 0x0000e2a4
3839 #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
3840 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
3841 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
3842 {
3843 return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
3844 }
3845 #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
3846 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
3847 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
3848 {
3849 return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
3850 }
3851 #define A5XX_VPC_SO_PROG_A_EN 0x00000800
3852 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
3853 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
3854 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
3855 {
3856 return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
3857 }
3858 #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
3859 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
3860 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
3861 {
3862 return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
3863 }
3864 #define A5XX_VPC_SO_PROG_B_EN 0x00800000
3865
3866 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3867
3868 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3869
3870 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
3871
3872 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
3873
3874 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
3875
3876 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
3877
3878 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
3879
3880 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
3881
3882 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
3883 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
3884 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
3885 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3886 {
3887 return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3888 }
3889 #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100
3890 #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200
3891 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
3892
3893 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
3894 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
3895
3896 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388
3897 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3898 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0
3899 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3900 {
3901 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK;
3902 }
3903 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038
3904 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3
3905 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3906 {
3907 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
3908 }
3909 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
3910
3911 #define REG_A5XX_UNKNOWN_E389 0x0000e389
3912
3913 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3914
3915 #define REG_A5XX_PC_GS_LAYERED 0x0000e38d
3916
3917 #define REG_A5XX_PC_GS_PARAM 0x0000e38e
3918 #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3919 #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
3920 static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3921 {
3922 return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3923 }
3924 #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
3925 #define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
3926 static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3927 {
3928 return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK;
3929 }
3930 #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
3931 #define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
3932 static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3933 {
3934 return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK;
3935 }
3936
3937 #define REG_A5XX_PC_HS_PARAM 0x0000e38f
3938 #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
3939 #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
3940 static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3941 {
3942 return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3943 }
3944 #define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000
3945 #define A5XX_PC_HS_PARAM_SPACING__SHIFT 21
3946 static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3947 {
3948 return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK;
3949 }
3950 #define A5XX_PC_HS_PARAM_CW 0x00800000
3951 #define A5XX_PC_HS_PARAM_CONNECTED 0x01000000
3952
3953 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
3954
3955 #define REG_A5XX_VFD_CONTROL_0 0x0000e400
3956 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
3957 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
3958 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
3959 {
3960 return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
3961 }
3962
3963 #define REG_A5XX_VFD_CONTROL_1 0x0000e401
3964 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
3965 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
3966 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
3967 {
3968 return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
3969 }
3970 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
3971 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
3972 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
3973 {
3974 return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
3975 }
3976 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
3977 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
3978 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
3979 {
3980 return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
3981 }
3982
3983 #define REG_A5XX_VFD_CONTROL_2 0x0000e402
3984 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
3985 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
3986 static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
3987 {
3988 return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
3989 }
3990
3991 #define REG_A5XX_VFD_CONTROL_3 0x0000e403
3992 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
3993 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
3994 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
3995 {
3996 return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
3997 }
3998 #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
3999 #define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
4000 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4001 {
4002 return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4003 }
4004 #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
4005 #define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
4006 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4007 {
4008 return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4009 }
4010
4011 #define REG_A5XX_VFD_CONTROL_4 0x0000e404
4012
4013 #define REG_A5XX_VFD_CONTROL_5 0x0000e405
4014
4015 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
4016
4017 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
4018
4019 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
4020
4021 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
4022
4023 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
4024
4025 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
4026
4027 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
4028
4029 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
4030
4031 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
4032 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
4033 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
4034 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
4035 {
4036 return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
4037 }
4038 #define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
4039 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
4040 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
4041 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
4042 {
4043 return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
4044 }
4045 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
4046 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
4047 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
4048 {
4049 return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
4050 }
4051 #define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
4052 #define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
4053
4054 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
4055
4056 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
4057
4058 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
4059 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
4060 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
4061 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
4062 {
4063 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
4064 }
4065 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
4066 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
4067 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
4068 {
4069 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
4070 }
4071
4072 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
4073
4074 #define REG_A5XX_SP_SP_CNTL 0x0000e580
4075
4076 #define REG_A5XX_SP_VS_CONFIG 0x0000e584
4077 #define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
4078 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4079 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4080 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4081 {
4082 return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4083 }
4084 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4085 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4086 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4087 {
4088 return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
4089 }
4090
4091 #define REG_A5XX_SP_FS_CONFIG 0x0000e585
4092 #define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
4093 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4094 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4095 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4096 {
4097 return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4098 }
4099 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4100 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4101 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4102 {
4103 return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
4104 }
4105
4106 #define REG_A5XX_SP_HS_CONFIG 0x0000e586
4107 #define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
4108 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4109 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4110 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4111 {
4112 return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4113 }
4114 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4115 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4116 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4117 {
4118 return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
4119 }
4120
4121 #define REG_A5XX_SP_DS_CONFIG 0x0000e587
4122 #define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
4123 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4124 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4125 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4126 {
4127 return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4128 }
4129 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4130 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4131 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4132 {
4133 return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
4134 }
4135
4136 #define REG_A5XX_SP_GS_CONFIG 0x0000e588
4137 #define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
4138 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4139 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4140 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4141 {
4142 return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4143 }
4144 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4145 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4146 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4147 {
4148 return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
4149 }
4150
4151 #define REG_A5XX_SP_CS_CONFIG 0x0000e589
4152 #define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
4153 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4154 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4155 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4156 {
4157 return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4158 }
4159 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4160 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4161 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4162 {
4163 return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
4164 }
4165
4166 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
4167
4168 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
4169
4170 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
4171 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4172 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
4173 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4174 {
4175 return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4176 }
4177 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4178 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4179 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4180 {
4181 return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4182 }
4183 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4184 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4185 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4186 {
4187 return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4188 }
4189 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
4190 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
4191 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4192 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4193 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4194 {
4195 return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4196 }
4197
4198 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
4199 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
4200 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
4201 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
4202 {
4203 return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
4204 }
4205
4206 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4207
4208 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4209 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
4210 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
4211 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4212 {
4213 return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
4214 }
4215 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
4216 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
4217 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4218 {
4219 return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4220 }
4221 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
4222 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
4223 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4224 {
4225 return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
4226 }
4227 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
4228 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
4229 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4230 {
4231 return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4232 }
4233
4234 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4235
4236 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4237 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
4238 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
4239 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
4240 {
4241 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4242 }
4243 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
4244 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
4245 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4246 {
4247 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4248 }
4249 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
4250 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
4251 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4252 {
4253 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4254 }
4255 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
4256 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
4257 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4258 {
4259 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4260 }
4261
4262 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
4263
4264 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
4265
4266 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
4267
4268 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
4269 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4270 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
4271 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4272 {
4273 return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4274 }
4275 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4276 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4277 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4278 {
4279 return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4280 }
4281 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4282 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4283 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4284 {
4285 return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4286 }
4287 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
4288 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
4289 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4290 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4291 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4292 {
4293 return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4294 }
4295
4296 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
4297
4298 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
4299
4300 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
4301
4302 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
4303 #define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
4304 #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
4305 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
4306
4307 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
4308 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
4309 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
4310 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4311 {
4312 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
4313 }
4314 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
4315 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
4316 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
4317 {
4318 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
4319 }
4320 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
4321 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
4322 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
4323 {
4324 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
4325 }
4326
4327 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4328
4329 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4330 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
4331 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
4332 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4333 {
4334 return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
4335 }
4336 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
4337
4338 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4339
4340 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4341 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
4342 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
4343 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
4344 {
4345 return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4346 }
4347 #define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
4348 #define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
4349 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
4350
4351 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
4352
4353 #define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
4354 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4355 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
4356 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4357 {
4358 return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4359 }
4360 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4361 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4362 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4363 {
4364 return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4365 }
4366 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4367 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4368 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4369 {
4370 return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4371 }
4372 #define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
4373 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
4374 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4375 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4376 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4377 {
4378 return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4379 }
4380
4381 #define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
4382
4383 #define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
4384
4385 #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
4386
4387 #define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600
4388 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4389 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 3
4390 static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4391 {
4392 return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
4393 }
4394 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4395 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4396 static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4397 {
4398 return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4399 }
4400 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4401 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4402 static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4403 {
4404 return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4405 }
4406 #define A5XX_SP_HS_CTRL_REG0_VARYING 0x00010000
4407 #define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x00100000
4408 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4409 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4410 static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4411 {
4412 return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
4413 }
4414
4415 #define REG_A5XX_UNKNOWN_E602 0x0000e602
4416
4417 #define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
4418
4419 #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
4420
4421 #define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610
4422 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4423 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 3
4424 static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4425 {
4426 return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
4427 }
4428 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4429 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4430 static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4431 {
4432 return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4433 }
4434 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4435 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4436 static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4437 {
4438 return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4439 }
4440 #define A5XX_SP_DS_CTRL_REG0_VARYING 0x00010000
4441 #define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x00100000
4442 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4443 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4444 static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4445 {
4446 return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
4447 }
4448
4449 #define REG_A5XX_UNKNOWN_E62B 0x0000e62b
4450
4451 #define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
4452
4453 #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
4454
4455 #define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640
4456 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4457 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 3
4458 static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4459 {
4460 return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
4461 }
4462 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4463 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4464 static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4465 {
4466 return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4467 }
4468 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4469 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4470 static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4471 {
4472 return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4473 }
4474 #define A5XX_SP_GS_CTRL_REG0_VARYING 0x00010000
4475 #define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x00100000
4476 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4477 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4478 static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4479 {
4480 return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
4481 }
4482
4483 #define REG_A5XX_UNKNOWN_E65B 0x0000e65b
4484
4485 #define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
4486
4487 #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
4488
4489 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
4490 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
4491 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
4492 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4493 {
4494 return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4495 }
4496
4497 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
4498 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
4499 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
4500 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4501 {
4502 return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4503 }
4504 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
4505
4506 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
4507
4508 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
4509
4510 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
4511
4512 #define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
4513
4514 #define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
4515
4516 #define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
4517
4518 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
4519
4520 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
4521
4522 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
4523
4524 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
4525
4526 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
4527
4528 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
4529
4530 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
4531
4532 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
4533
4534 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
4535
4536 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
4537
4538 #define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
4539
4540 #define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
4541
4542 #define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
4543
4544 #define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
4545
4546 #define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
4547
4548 #define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
4549
4550 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
4551
4552 #define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
4553
4554 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
4555
4556 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
4557
4558 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
4559
4560 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
4561
4562 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
4563
4564 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
4565
4566 #define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
4567
4568 #define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
4569
4570 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
4571
4572 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
4573 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
4574 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
4575 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
4576 {
4577 return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
4578 }
4579 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
4580 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
4581 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
4582 {
4583 return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
4584 }
4585
4586 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
4587 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
4588 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
4589 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
4590 {
4591 return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
4592 }
4593
4594 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
4595 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
4596 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
4597 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4598 {
4599 return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4600 }
4601 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
4602 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
4603 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
4604 {
4605 return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
4606 }
4607 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
4608 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
4609 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
4610 {
4611 return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
4612 }
4613 #define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
4614 #define A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
4615 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
4616 {
4617 return ((val) << A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
4618 }
4619
4620 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
4621 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
4622 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
4623 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
4624 {
4625 return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
4626 }
4627 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
4628 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
4629 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
4630 {
4631 return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
4632 }
4633 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
4634 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
4635 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
4636 {
4637 return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
4638 }
4639 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
4640 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
4641 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
4642 {
4643 return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
4644 }
4645
4646 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
4647 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
4648 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
4649 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
4650 {
4651 return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
4652 }
4653 #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
4654 #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
4655 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
4656 {
4657 return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
4658 }
4659 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
4660 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
4661 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4662 {
4663 return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4664 }
4665 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
4666 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
4667 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4668 {
4669 return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4670 }
4671
4672 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
4673
4674 #define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
4675 #define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
4676 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4677 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4678 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4679 {
4680 return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4681 }
4682 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4683 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4684 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4685 {
4686 return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
4687 }
4688
4689 #define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
4690 #define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
4691 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4692 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4693 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4694 {
4695 return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4696 }
4697 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4698 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4699 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4700 {
4701 return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
4702 }
4703
4704 #define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
4705 #define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
4706 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4707 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4708 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4709 {
4710 return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4711 }
4712 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4713 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4714 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4715 {
4716 return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
4717 }
4718
4719 #define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
4720 #define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
4721 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4722 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4723 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4724 {
4725 return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4726 }
4727 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4728 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4729 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4730 {
4731 return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
4732 }
4733
4734 #define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
4735 #define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
4736 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4737 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4738 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4739 {
4740 return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4741 }
4742 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4743 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4744 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4745 {
4746 return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
4747 }
4748
4749 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
4750 #define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
4751 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4752 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4753 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4754 {
4755 return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4756 }
4757 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4758 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4759 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4760 {
4761 return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
4762 }
4763
4764 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
4765 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
4766 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
4767 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
4768 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
4769 {
4770 return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
4771 }
4772
4773 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
4774 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
4775 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
4776 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
4777 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
4778 {
4779 return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
4780 }
4781
4782 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
4783 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
4784 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
4785 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
4786 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
4787 {
4788 return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
4789 }
4790
4791 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
4792 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
4793 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
4794 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
4795 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
4796 {
4797 return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
4798 }
4799
4800 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
4801 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
4802 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
4803 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
4804 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
4805 {
4806 return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
4807 }
4808
4809 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
4810 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
4811 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
4812 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
4813 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
4814 {
4815 return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
4816 }
4817
4818 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
4819
4820 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
4821
4822 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
4823
4824 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
4825 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
4826 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
4827 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4828 {
4829 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4830 }
4831 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
4832 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
4833 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4834 {
4835 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4836 }
4837 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
4838 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
4839 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4840 {
4841 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4842 }
4843 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
4844 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
4845 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4846 {
4847 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4848 }
4849
4850 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
4851 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
4852 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
4853 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
4854 {
4855 return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
4856 }
4857
4858 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
4859 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
4860 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
4861 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
4862 {
4863 return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
4864 }
4865
4866 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
4867 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
4868 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
4869 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
4870 {
4871 return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
4872 }
4873
4874 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
4875 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
4876 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
4877 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
4878 {
4879 return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
4880 }
4881
4882 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
4883 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
4884 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
4885 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
4886 {
4887 return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
4888 }
4889
4890 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
4891 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
4892 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
4893 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
4894 {
4895 return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
4896 }
4897
4898 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
4899 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
4900 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
4901 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4902 {
4903 return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4904 }
4905 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
4906 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
4907 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4908 {
4909 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4910 }
4911 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
4912 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
4913 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4914 {
4915 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4916 }
4917 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
4918 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
4919 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4920 {
4921 return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4922 }
4923
4924 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
4925
4926 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
4927
4928 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
4929
4930 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
4931
4932 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
4933
4934 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
4935
4936 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
4937
4938 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
4939
4940 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
4941
4942 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
4943
4944 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
4945
4946 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
4947
4948 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
4949
4950 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
4951
4952 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
4953
4954 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
4955
4956 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
4957
4958 #define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
4959
4960 #define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
4961
4962 #define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100
4963
4964 #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
4965
4966 #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
4967
4968 #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
4969
4970 #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
4971
4972 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107
4973 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
4974 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
4975 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4976 {
4977 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
4978 }
4979 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
4980 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8
4981 static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
4982 {
4983 return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK;
4984 }
4985 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
4986 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
4987 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4988 {
4989 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
4990 }
4991 #define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000
4992
4993 #define REG_A5XX_RB_2D_SRC_LO 0x00002108
4994
4995 #define REG_A5XX_RB_2D_SRC_HI 0x00002109
4996
4997 #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
4998 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
4999 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
5000 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
5001 {
5002 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
5003 }
5004 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
5005 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
5006 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
5007 {
5008 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
5009 }
5010
5011 #define REG_A5XX_RB_2D_DST_INFO 0x00002110
5012 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
5013 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
5014 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5015 {
5016 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
5017 }
5018 #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
5019 #define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
5020 static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
5021 {
5022 return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK;
5023 }
5024 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
5025 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
5026 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5027 {
5028 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
5029 }
5030 #define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000
5031
5032 #define REG_A5XX_RB_2D_DST_LO 0x00002111
5033
5034 #define REG_A5XX_RB_2D_DST_HI 0x00002112
5035
5036 #define REG_A5XX_RB_2D_DST_SIZE 0x00002113
5037 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
5038 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
5039 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
5040 {
5041 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
5042 }
5043 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
5044 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
5045 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
5046 {
5047 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
5048 }
5049
5050 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
5051
5052 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
5053
5054 #define REG_A5XX_RB_2D_SRC_FLAGS_PITCH 0x00002142
5055 #define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK 0xffffffff
5056 #define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0
5057 static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
5058 {
5059 return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
5060 }
5061
5062 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
5063
5064 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
5065
5066 #define REG_A5XX_RB_2D_DST_FLAGS_PITCH 0x00002145
5067 #define A5XX_RB_2D_DST_FLAGS_PITCH__MASK 0xffffffff
5068 #define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
5069 static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
5070 {
5071 return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
5072 }
5073
5074 #define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
5075
5076 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
5077 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
5078 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
5079 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5080 {
5081 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
5082 }
5083 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
5084 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8
5085 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
5086 {
5087 return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK;
5088 }
5089 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
5090 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
5091 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5092 {
5093 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
5094 }
5095 #define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000
5096
5097 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
5098 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
5099 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
5100 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5101 {
5102 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
5103 }
5104 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300
5105 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8
5106 static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
5107 {
5108 return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK;
5109 }
5110 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
5111 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
5112 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5113 {
5114 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
5115 }
5116 #define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000
5117
5118 #define REG_A5XX_UNKNOWN_2100 0x00002100
5119
5120 #define REG_A5XX_UNKNOWN_2180 0x00002180
5121
5122 #define REG_A5XX_UNKNOWN_2184 0x00002184
5123
5124 #define REG_A5XX_TEX_SAMP_0 0x00000000
5125 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
5126 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
5127 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
5128 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
5129 {
5130 return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
5131 }
5132 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
5133 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
5134 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
5135 {
5136 return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
5137 }
5138 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
5139 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
5140 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
5141 {
5142 return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
5143 }
5144 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
5145 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
5146 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
5147 {
5148 return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
5149 }
5150 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
5151 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
5152 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
5153 {
5154 return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
5155 }
5156 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
5157 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
5158 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
5159 {
5160 return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
5161 }
5162 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
5163 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
5164 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
5165 {
5166 return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
5167 }
5168
5169 #define REG_A5XX_TEX_SAMP_1 0x00000001
5170 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
5171 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
5172 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
5173 {
5174 return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
5175 }
5176 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
5177 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
5178 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
5179 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
5180 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
5181 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
5182 {
5183 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
5184 }
5185 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
5186 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
5187 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
5188 {
5189 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
5190 }
5191
5192 #define REG_A5XX_TEX_SAMP_2 0x00000002
5193 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
5194 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
5195 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5196 {
5197 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
5198 }
5199
5200 #define REG_A5XX_TEX_SAMP_3 0x00000003
5201
5202 #define REG_A5XX_TEX_CONST_0 0x00000000
5203 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
5204 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
5205 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
5206 {
5207 return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
5208 }
5209 #define A5XX_TEX_CONST_0_SRGB 0x00000004
5210 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
5211 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
5212 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
5213 {
5214 return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
5215 }
5216 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
5217 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
5218 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
5219 {
5220 return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
5221 }
5222 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
5223 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
5224 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
5225 {
5226 return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
5227 }
5228 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
5229 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
5230 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
5231 {
5232 return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
5233 }
5234 #define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
5235 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
5236 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5237 {
5238 return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
5239 }
5240 #define A5XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
5241 #define A5XX_TEX_CONST_0_SAMPLES__SHIFT 20
5242 static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
5243 {
5244 return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK;
5245 }
5246 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
5247 #define A5XX_TEX_CONST_0_FMT__SHIFT 22
5248 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
5249 {
5250 return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
5251 }
5252 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
5253 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30
5254 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
5255 {
5256 return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
5257 }
5258
5259 #define REG_A5XX_TEX_CONST_1 0x00000001
5260 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
5261 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
5262 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
5263 {
5264 return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
5265 }
5266 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
5267 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
5268 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
5269 {
5270 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
5271 }
5272
5273 #define REG_A5XX_TEX_CONST_2 0x00000002
5274 #define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
5275 #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
5276 static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
5277 {
5278 return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
5279 }
5280 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
5281 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7
5282 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
5283 {
5284 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
5285 }
5286 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
5287 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29
5288 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
5289 {
5290 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
5291 }
5292
5293 #define REG_A5XX_TEX_CONST_3 0x00000003
5294 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
5295 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
5296 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5297 {
5298 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5299 }
5300 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
5301 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
5302 static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
5303 {
5304 return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
5305 }
5306 #define A5XX_TEX_CONST_3_TILE_ALL 0x08000000
5307 #define A5XX_TEX_CONST_3_FLAG 0x10000000
5308
5309 #define REG_A5XX_TEX_CONST_4 0x00000004
5310 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
5311 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
5312 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
5313 {
5314 return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
5315 }
5316
5317 #define REG_A5XX_TEX_CONST_5 0x00000005
5318 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
5319 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
5320 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
5321 {
5322 return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
5323 }
5324 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
5325 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
5326 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
5327 {
5328 return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
5329 }
5330
5331 #define REG_A5XX_TEX_CONST_6 0x00000006
5332
5333 #define REG_A5XX_TEX_CONST_7 0x00000007
5334
5335 #define REG_A5XX_TEX_CONST_8 0x00000008
5336
5337 #define REG_A5XX_TEX_CONST_9 0x00000009
5338
5339 #define REG_A5XX_TEX_CONST_10 0x0000000a
5340
5341 #define REG_A5XX_TEX_CONST_11 0x0000000b
5342
5343 #define REG_A5XX_SSBO_0_0 0x00000000
5344 #define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0
5345 #define A5XX_SSBO_0_0_BASE_LO__SHIFT 5
5346 static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
5347 {
5348 return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
5349 }
5350
5351 #define REG_A5XX_SSBO_0_1 0x00000001
5352 #define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff
5353 #define A5XX_SSBO_0_1_PITCH__SHIFT 0
5354 static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
5355 {
5356 return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK;
5357 }
5358
5359 #define REG_A5XX_SSBO_0_2 0x00000002
5360 #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
5361 #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
5362 static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
5363 {
5364 return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
5365 }
5366
5367 #define REG_A5XX_SSBO_0_3 0x00000003
5368 #define A5XX_SSBO_0_3_CPP__MASK 0x0000003f
5369 #define A5XX_SSBO_0_3_CPP__SHIFT 0
5370 static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
5371 {
5372 return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK;
5373 }
5374
5375 #define REG_A5XX_SSBO_1_0 0x00000000
5376 #define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00
5377 #define A5XX_SSBO_1_0_FMT__SHIFT 8
5378 static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
5379 {
5380 return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK;
5381 }
5382 #define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000
5383 #define A5XX_SSBO_1_0_WIDTH__SHIFT 16
5384 static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
5385 {
5386 return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK;
5387 }
5388
5389 #define REG_A5XX_SSBO_1_1 0x00000001
5390 #define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
5391 #define A5XX_SSBO_1_1_HEIGHT__SHIFT 0
5392 static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
5393 {
5394 return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK;
5395 }
5396 #define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000
5397 #define A5XX_SSBO_1_1_DEPTH__SHIFT 16
5398 static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
5399 {
5400 return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK;
5401 }
5402
5403 #define REG_A5XX_SSBO_2_0 0x00000000
5404 #define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff
5405 #define A5XX_SSBO_2_0_BASE_LO__SHIFT 0
5406 static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
5407 {
5408 return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK;
5409 }
5410
5411 #define REG_A5XX_SSBO_2_1 0x00000001
5412 #define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff
5413 #define A5XX_SSBO_2_1_BASE_HI__SHIFT 0
5414 static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
5415 {
5416 return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
5417 }
5418
5419 #define REG_A5XX_UBO_0 0x00000000
5420 #define A5XX_UBO_0_BASE_LO__MASK 0xffffffff
5421 #define A5XX_UBO_0_BASE_LO__SHIFT 0
5422 static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
5423 {
5424 return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
5425 }
5426
5427 #define REG_A5XX_UBO_1 0x00000001
5428 #define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff
5429 #define A5XX_UBO_1_BASE_HI__SHIFT 0
5430 static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
5431 {
5432 return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
5433 }
5434
5435
5436 #endif /* A5XX_XML */
Linux with added FPC-III support