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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / msm / adreno / a6xx_gmu.c
blobe6703ae98760885f2afbce2e53d1ce8d3f9874c5
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4 #include <linux/clk.h>
5 #include <linux/interconnect.h>
6 #include <linux/pm_domain.h>
7 #include <linux/pm_opp.h>
8 #include <soc/qcom/cmd-db.h>
9 #include <drm/drm_gem.h>
10
11 #include "a6xx_gpu.h"
12 #include "a6xx_gmu.xml.h"
13 #include "msm_gem.h"
14 #include "msm_gpu_trace.h"
15 #include "msm_mmu.h"
16
17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
18 {
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
20 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
21 struct msm_gpu *gpu = &adreno_gpu->base;
22
23 /* FIXME: add a banner here */
24 gmu->hung = true;
25
26 /* Turn off the hangcheck timer while we are resetting */
27 del_timer(&gpu->hangcheck_timer);
28
29 /* Queue the GPU handler because we need to treat this as a recovery */
30 kthread_queue_work(gpu->worker, &gpu->recover_work);
31 }
32
33 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
34 {
35 struct a6xx_gmu *gmu = data;
36 u32 status;
37
38 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
39 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
40
41 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
42 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
43
44 a6xx_gmu_fault(gmu);
45 }
46
47 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
48 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
49
50 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
51 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
52 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
53
54 return IRQ_HANDLED;
55 }
56
57 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
58 {
59 struct a6xx_gmu *gmu = data;
60 u32 status;
61
62 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
63 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
64
65 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
66 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
67
68 a6xx_gmu_fault(gmu);
69 }
70
71 return IRQ_HANDLED;
72 }
73
74 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
75 {
76 u32 val;
77
78 /* This can be called from gpu state code so make sure GMU is valid */
79 if (!gmu->initialized)
80 return false;
81
82 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
83
84 return !(val &
85 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
86 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
87 }
88
89 /* Check to see if the GX rail is still powered */
90 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
91 {
92 u32 val;
93
94 /* This can be called from gpu state code so make sure GMU is valid */
95 if (!gmu->initialized)
96 return false;
97
98 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
99
100 return !(val &
101 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
102 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
103 }
104
105 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
106 {
107 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
108 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
109 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
110 u32 perf_index;
111 unsigned long gpu_freq;
112 int ret = 0;
113
114 gpu_freq = dev_pm_opp_get_freq(opp);
115
116 if (gpu_freq == gmu->freq)
117 return;
118
119 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
120 if (gpu_freq == gmu->gpu_freqs[perf_index])
121 break;
122
123 gmu->current_perf_index = perf_index;
124 gmu->freq = gmu->gpu_freqs[perf_index];
125
126 trace_msm_gmu_freq_change(gmu->freq, perf_index);
127
128 /*
129 * This can get called from devfreq while the hardware is idle. Don't
130 * bring up the power if it isn't already active
131 */
132 if (pm_runtime_get_if_in_use(gmu->dev) == 0)
133 return;
134
135 if (!gmu->legacy) {
136 a6xx_hfi_set_freq(gmu, perf_index);
137 dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
138 pm_runtime_put(gmu->dev);
139 return;
140 }
141
142 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
143
144 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
145 ((3 & 0xf) << 28) | perf_index);
146
147 /*
148 * Send an invalid index as a vote for the bus bandwidth and let the
149 * firmware decide on the right vote
150 */
151 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
152
153 /* Set and clear the OOB for DCVS to trigger the GMU */
154 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
155 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
156
157 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
158 if (ret)
159 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
160
161 dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
162 pm_runtime_put(gmu->dev);
163 }
164
165 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
166 {
167 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
168 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
169 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
170
171 return gmu->freq;
172 }
173
174 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
175 {
176 u32 val;
177 int local = gmu->idle_level;
178
179 /* SPTP and IFPC both report as IFPC */
180 if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
181 local = GMU_IDLE_STATE_IFPC;
182
183 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
184
185 if (val == local) {
186 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
187 !a6xx_gmu_gx_is_on(gmu))
188 return true;
189 }
190
191 return false;
192 }
193
194 /* Wait for the GMU to get to its most idle state */
195 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
196 {
197 return spin_until(a6xx_gmu_check_idle_level(gmu));
198 }
199
200 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
201 {
202 int ret;
203 u32 val;
204 u32 mask, reset_val;
205
206 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
207 if (val <= 0x20010004) {
208 mask = 0xffffffff;
209 reset_val = 0xbabeface;
210 } else {
211 mask = 0x1ff;
212 reset_val = 0x100;
213 }
214
215 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
216
217 /* Set the log wptr index
218 * note: downstream saves the value in poweroff and restores it here
219 */
220 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
221
222 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
223
224 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
225 (val & mask) == reset_val, 100, 10000);
226
227 if (ret)
228 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
229
230 return ret;
231 }
232
233 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
234 {
235 u32 val;
236 int ret;
237
238 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
239
240 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
241 val & 1, 100, 10000);
242 if (ret)
243 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
244
245 return ret;
246 }
247
248 /* Trigger a OOB (out of band) request to the GMU */
249 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
250 {
251 int ret;
252 u32 val;
253 int request, ack;
254 const char *name;
255
256 switch (state) {
257 case GMU_OOB_GPU_SET:
258 if (gmu->legacy) {
259 request = GMU_OOB_GPU_SET_REQUEST;
260 ack = GMU_OOB_GPU_SET_ACK;
261 } else {
262 request = GMU_OOB_GPU_SET_REQUEST_NEW;
263 ack = GMU_OOB_GPU_SET_ACK_NEW;
264 }
265 name = "GPU_SET";
266 break;
267 case GMU_OOB_BOOT_SLUMBER:
268 request = GMU_OOB_BOOT_SLUMBER_REQUEST;
269 ack = GMU_OOB_BOOT_SLUMBER_ACK;
270 name = "BOOT_SLUMBER";
271 break;
272 case GMU_OOB_DCVS_SET:
273 request = GMU_OOB_DCVS_REQUEST;
274 ack = GMU_OOB_DCVS_ACK;
275 name = "GPU_DCVS";
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 /* Trigger the equested OOB operation */
282 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
283
284 /* Wait for the acknowledge interrupt */
285 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
286 val & (1 << ack), 100, 10000);
287
288 if (ret)
289 DRM_DEV_ERROR(gmu->dev,
290 "Timeout waiting for GMU OOB set %s: 0x%x\n",
291 name,
292 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
293
294 /* Clear the acknowledge interrupt */
295 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
296
297 return ret;
298 }
299
300 /* Clear a pending OOB state in the GMU */
301 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
302 {
303 if (!gmu->legacy) {
304 WARN_ON(state != GMU_OOB_GPU_SET);
305 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
306 1 << GMU_OOB_GPU_SET_CLEAR_NEW);
307 return;
308 }
309
310 switch (state) {
311 case GMU_OOB_GPU_SET:
312 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
313 1 << GMU_OOB_GPU_SET_CLEAR);
314 break;
315 case GMU_OOB_BOOT_SLUMBER:
316 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
317 1 << GMU_OOB_BOOT_SLUMBER_CLEAR);
318 break;
319 case GMU_OOB_DCVS_SET:
320 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
321 1 << GMU_OOB_DCVS_CLEAR);
322 break;
323 }
324 }
325
326 /* Enable CPU control of SPTP power power collapse */
327 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
328 {
329 int ret;
330 u32 val;
331
332 if (!gmu->legacy)
333 return 0;
334
335 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
336
337 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
338 (val & 0x38) == 0x28, 1, 100);
339
340 if (ret) {
341 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
342 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
343 }
344
345 return 0;
346 }
347
348 /* Disable CPU control of SPTP power power collapse */
349 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
350 {
351 u32 val;
352 int ret;
353
354 if (!gmu->legacy)
355 return;
356
357 /* Make sure retention is on */
358 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
359
360 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
361
362 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
363 (val & 0x04), 100, 10000);
364
365 if (ret)
366 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
367 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
368 }
369
370 /* Let the GMU know we are starting a boot sequence */
371 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
372 {
373 u32 vote;
374
375 /* Let the GMU know we are getting ready for boot */
376 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
377
378 /* Choose the "default" power level as the highest available */
379 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
380
381 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
382 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
383
384 /* Let the GMU know the boot sequence has started */
385 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
386 }
387
388 /* Let the GMU know that we are about to go into slumber */
389 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
390 {
391 int ret;
392
393 /* Disable the power counter so the GMU isn't busy */
394 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
395
396 /* Disable SPTP_PC if the CPU is responsible for it */
397 if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
398 a6xx_sptprac_disable(gmu);
399
400 if (!gmu->legacy) {
401 ret = a6xx_hfi_send_prep_slumber(gmu);
402 goto out;
403 }
404
405 /* Tell the GMU to get ready to slumber */
406 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
407
408 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
409 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
410
411 if (!ret) {
412 /* Check to see if the GMU really did slumber */
413 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
414 != 0x0f) {
415 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
416 ret = -ETIMEDOUT;
417 }
418 }
419
420 out:
421 /* Put fence into allow mode */
422 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
423 return ret;
424 }
425
426 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
427 {
428 int ret;
429 u32 val;
430
431 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
432 /* Wait for the register to finish posting */
433 wmb();
434
435 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
436 val & (1 << 1), 100, 10000);
437 if (ret) {
438 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
439 return ret;
440 }
441
442 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
443 !val, 100, 10000);
444
445 if (ret) {
446 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
447 return ret;
448 }
449
450 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
451
452 /* Set up CX GMU counter 0 to count busy ticks */
453 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
454 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
455
456 /* Enable the power counter */
457 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
458 return 0;
459 }
460
461 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
462 {
463 int ret;
464 u32 val;
465
466 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
467
468 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
469 val, val & (1 << 16), 100, 10000);
470 if (ret)
471 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
472
473 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
474 }
475
476 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
477 {
478 return msm_writel(value, ptr + (offset << 2));
479 }
480
481 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
482 const char *name);
483
484 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
485 {
486 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
487 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
488 struct platform_device *pdev = to_platform_device(gmu->dev);
489 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
490 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
491 uint32_t pdc_address_offset;
492
493 if (!pdcptr || !seqptr)
494 goto err;
495
496 if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
497 pdc_address_offset = 0x30090;
498 else if (adreno_is_a650(adreno_gpu))
499 pdc_address_offset = 0x300a0;
500 else
501 pdc_address_offset = 0x30080;
502
503 /* Disable SDE clock gating */
504 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
505
506 /* Setup RSC PDC handshake for sleep and wakeup */
507 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
508 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
509 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
510 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
511 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
512 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
513 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
514 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
515 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
516 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
517 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
518
519 /* Load RSC sequencer uCode for sleep and wakeup */
520 if (adreno_is_a650(adreno_gpu)) {
521 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
522 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
523 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
524 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
525 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
526 } else {
527 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
528 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
529 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
530 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
531 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
532 }
533
534 /* Load PDC sequencer uCode for power up and power down sequence */
535 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
536 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
537 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
538 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
539 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
540
541 /* Set TCS commands used by PDC sequence for low power modes */
542 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
543 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
544 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
545 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
546 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
547 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
548 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
549 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
550 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
551
552 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
553 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
554 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
555
556 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
557 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
558 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
559 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
560 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
561 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
562
563 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
564 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
565 if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
566 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
567 else
568 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
569 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
570 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
571 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
572
573 /* Setup GPU PDC */
574 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
575 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
576
577 /* ensure no writes happen before the uCode is fully written */
578 wmb();
579
580 err:
581 if (!IS_ERR_OR_NULL(pdcptr))
582 iounmap(pdcptr);
583 if (!IS_ERR_OR_NULL(seqptr))
584 iounmap(seqptr);
585 }
586
587 /*
588 * The lowest 16 bits of this value are the number of XO clock cycles for main
589 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
590 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
591 */
592
593 #define GMU_PWR_COL_HYST 0x000a1680
594
595 /* Set up the idle state for the GMU */
596 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
597 {
598 /* Disable GMU WB/RB buffer */
599 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
600 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
601 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
602
603 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
604
605 switch (gmu->idle_level) {
606 case GMU_IDLE_STATE_IFPC:
607 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
608 GMU_PWR_COL_HYST);
609 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
610 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
611 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
612 fallthrough;
613 case GMU_IDLE_STATE_SPTP:
614 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
615 GMU_PWR_COL_HYST);
616 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
617 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
618 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
619 }
620
621 /* Enable RPMh GPU client */
622 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
623 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
624 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
625 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
626 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
627 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
628 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
629 }
630
631 struct block_header {
632 u32 addr;
633 u32 size;
634 u32 type;
635 u32 value;
636 u32 data[];
637 };
638
639 /* this should be a general kernel helper */
640 static int in_range(u32 addr, u32 start, u32 size)
641 {
642 return addr >= start && addr < start + size;
643 }
644
645 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
646 {
647 if (!in_range(blk->addr, bo->iova, bo->size))
648 return false;
649
650 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
651 return true;
652 }
653
654 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
655 {
656 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
657 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
658 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
659 const struct block_header *blk;
660 u32 reg_offset;
661
662 u32 itcm_base = 0x00000000;
663 u32 dtcm_base = 0x00040000;
664
665 if (adreno_is_a650(adreno_gpu))
666 dtcm_base = 0x10004000;
667
668 if (gmu->legacy) {
669 /* Sanity check the size of the firmware that was loaded */
670 if (fw_image->size > 0x8000) {
671 DRM_DEV_ERROR(gmu->dev,
672 "GMU firmware is bigger than the available region\n");
673 return -EINVAL;
674 }
675
676 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
677 (u32*) fw_image->data, fw_image->size);
678 return 0;
679 }
680
681
682 for (blk = (const struct block_header *) fw_image->data;
683 (const u8*) blk < fw_image->data + fw_image->size;
684 blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
685 if (blk->size == 0)
686 continue;
687
688 if (in_range(blk->addr, itcm_base, SZ_16K)) {
689 reg_offset = (blk->addr - itcm_base) >> 2;
690 gmu_write_bulk(gmu,
691 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
692 blk->data, blk->size);
693 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
694 reg_offset = (blk->addr - dtcm_base) >> 2;
695 gmu_write_bulk(gmu,
696 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
697 blk->data, blk->size);
698 } else if (!fw_block_mem(&gmu->icache, blk) &&
699 !fw_block_mem(&gmu->dcache, blk) &&
700 !fw_block_mem(&gmu->dummy, blk)) {
701 DRM_DEV_ERROR(gmu->dev,
702 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
703 blk->addr, blk->size, blk->data[0]);
704 }
705 }
706
707 return 0;
708 }
709
710 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
711 {
712 static bool rpmh_init;
713 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
714 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
715 int ret;
716 u32 chipid;
717
718 if (adreno_is_a650(adreno_gpu))
719 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
720
721 if (state == GMU_WARM_BOOT) {
722 ret = a6xx_rpmh_start(gmu);
723 if (ret)
724 return ret;
725 } else {
726 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
727 "GMU firmware is not loaded\n"))
728 return -ENOENT;
729
730 /* Turn on register retention */
731 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
732
733 /* We only need to load the RPMh microcode once */
734 if (!rpmh_init) {
735 a6xx_gmu_rpmh_init(gmu);
736 rpmh_init = true;
737 } else {
738 ret = a6xx_rpmh_start(gmu);
739 if (ret)
740 return ret;
741 }
742
743 ret = a6xx_gmu_fw_load(gmu);
744 if (ret)
745 return ret;
746 }
747
748 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
749 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
750
751 /* Write the iova of the HFI table */
752 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
753 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
754
755 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
756 (1 << 31) | (0xa << 18) | (0xa0));
757
758 chipid = adreno_gpu->rev.core << 24;
759 chipid |= adreno_gpu->rev.major << 16;
760 chipid |= adreno_gpu->rev.minor << 12;
761 chipid |= adreno_gpu->rev.patchid << 8;
762
763 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
764
765 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
766 gmu->log.iova | (gmu->log.size / SZ_4K - 1));
767
768 /* Set up the lowest idle level on the GMU */
769 a6xx_gmu_power_config(gmu);
770
771 ret = a6xx_gmu_start(gmu);
772 if (ret)
773 return ret;
774
775 if (gmu->legacy) {
776 ret = a6xx_gmu_gfx_rail_on(gmu);
777 if (ret)
778 return ret;
779 }
780
781 /* Enable SPTP_PC if the CPU is responsible for it */
782 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
783 ret = a6xx_sptprac_enable(gmu);
784 if (ret)
785 return ret;
786 }
787
788 ret = a6xx_gmu_hfi_start(gmu);
789 if (ret)
790 return ret;
791
792 /* FIXME: Do we need this wmb() here? */
793 wmb();
794
795 return 0;
796 }
797
798 #define A6XX_HFI_IRQ_MASK \
799 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
800
801 #define A6XX_GMU_IRQ_MASK \
802 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
803 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
804 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
805
806 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
807 {
808 disable_irq(gmu->gmu_irq);
809 disable_irq(gmu->hfi_irq);
810
811 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
812 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
813 }
814
815 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
816 {
817 u32 val;
818
819 /* Make sure there are no outstanding RPMh votes */
820 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
821 (val & 1), 100, 10000);
822 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
823 (val & 1), 100, 10000);
824 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
825 (val & 1), 100, 10000);
826 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
827 (val & 1), 100, 1000);
828 }
829
830 /* Force the GMU off in case it isn't responsive */
831 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
832 {
833 /* Flush all the queues */
834 a6xx_hfi_stop(gmu);
835
836 /* Stop the interrupts */
837 a6xx_gmu_irq_disable(gmu);
838
839 /* Force off SPTP in case the GMU is managing it */
840 a6xx_sptprac_disable(gmu);
841
842 /* Make sure there are no outstanding RPMh votes */
843 a6xx_gmu_rpmh_off(gmu);
844 }
845
846 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
847 {
848 struct dev_pm_opp *gpu_opp;
849 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
850
851 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
852 if (IS_ERR_OR_NULL(gpu_opp))
853 return;
854
855 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
856 a6xx_gmu_set_freq(gpu, gpu_opp);
857 dev_pm_opp_put(gpu_opp);
858 }
859
860 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
861 {
862 struct dev_pm_opp *gpu_opp;
863 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
864
865 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
866 if (IS_ERR_OR_NULL(gpu_opp))
867 return;
868
869 dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp);
870 dev_pm_opp_put(gpu_opp);
871 }
872
873 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
874 {
875 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
876 struct msm_gpu *gpu = &adreno_gpu->base;
877 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
878 int status, ret;
879
880 if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
881 return 0;
882
883 gmu->hung = false;
884
885 /* Turn on the resources */
886 pm_runtime_get_sync(gmu->dev);
887
888 /*
889 * "enable" the GX power domain which won't actually do anything but it
890 * will make sure that the refcounting is correct in case we need to
891 * bring down the GX after a GMU failure
892 */
893 if (!IS_ERR_OR_NULL(gmu->gxpd))
894 pm_runtime_get_sync(gmu->gxpd);
895
896 /* Use a known rate to bring up the GMU */
897 clk_set_rate(gmu->core_clk, 200000000);
898 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
899 if (ret) {
900 pm_runtime_put(gmu->gxpd);
901 pm_runtime_put(gmu->dev);
902 return ret;
903 }
904
905 /* Set the bus quota to a reasonable value for boot */
906 a6xx_gmu_set_initial_bw(gpu, gmu);
907
908 /* Enable the GMU interrupt */
909 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
910 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
911 enable_irq(gmu->gmu_irq);
912
913 /* Check to see if we are doing a cold or warm boot */
914 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
915 GMU_WARM_BOOT : GMU_COLD_BOOT;
916
917 /*
918 * Warm boot path does not work on newer GPUs
919 * Presumably this is because icache/dcache regions must be restored
920 */
921 if (!gmu->legacy)
922 status = GMU_COLD_BOOT;
923
924 ret = a6xx_gmu_fw_start(gmu, status);
925 if (ret)
926 goto out;
927
928 ret = a6xx_hfi_start(gmu, status);
929 if (ret)
930 goto out;
931
932 /*
933 * Turn on the GMU firmware fault interrupt after we know the boot
934 * sequence is successful
935 */
936 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
937 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
938 enable_irq(gmu->hfi_irq);
939
940 /* Set the GPU to the current freq */
941 a6xx_gmu_set_initial_freq(gpu, gmu);
942
943 out:
944 /* On failure, shut down the GMU to leave it in a good state */
945 if (ret) {
946 disable_irq(gmu->gmu_irq);
947 a6xx_rpmh_stop(gmu);
948 pm_runtime_put(gmu->gxpd);
949 pm_runtime_put(gmu->dev);
950 }
951
952 return ret;
953 }
954
955 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
956 {
957 u32 reg;
958
959 if (!gmu->initialized)
960 return true;
961
962 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
963
964 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
965 return false;
966
967 return true;
968 }
969
970 #define GBIF_CLIENT_HALT_MASK BIT(0)
971 #define GBIF_ARB_HALT_MASK BIT(1)
972
973 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
974 {
975 struct msm_gpu *gpu = &adreno_gpu->base;
976
977 if (!a6xx_has_gbif(adreno_gpu)) {
978 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
979 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
980 0xf) == 0xf);
981 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
982
983 return;
984 }
985
986 /* Halt new client requests on GBIF */
987 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
988 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
989 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
990
991 /* Halt all AXI requests on GBIF */
992 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
993 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
994 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
995
996 /* The GBIF halt needs to be explicitly cleared */
997 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
998 }
999
1000 /* Gracefully try to shut down the GMU and by extension the GPU */
1001 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1002 {
1003 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1004 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1005 u32 val;
1006
1007 /*
1008 * The GMU may still be in slumber unless the GPU started so check and
1009 * skip putting it back into slumber if so
1010 */
1011 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1012
1013 if (val != 0xf) {
1014 int ret = a6xx_gmu_wait_for_idle(gmu);
1015
1016 /* If the GMU isn't responding assume it is hung */
1017 if (ret) {
1018 a6xx_gmu_force_off(gmu);
1019 return;
1020 }
1021
1022 a6xx_bus_clear_pending_transactions(adreno_gpu);
1023
1024 /* tell the GMU we want to slumber */
1025 a6xx_gmu_notify_slumber(gmu);
1026
1027 ret = gmu_poll_timeout(gmu,
1028 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1029 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1030 100, 10000);
1031
1032 /*
1033 * Let the user know we failed to slumber but don't worry too
1034 * much because we are powering down anyway
1035 */
1036
1037 if (ret)
1038 DRM_DEV_ERROR(gmu->dev,
1039 "Unable to slumber GMU: status = 0%x/0%x\n",
1040 gmu_read(gmu,
1041 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1042 gmu_read(gmu,
1043 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1044 }
1045
1046 /* Turn off HFI */
1047 a6xx_hfi_stop(gmu);
1048
1049 /* Stop the interrupts and mask the hardware */
1050 a6xx_gmu_irq_disable(gmu);
1051
1052 /* Tell RPMh to power off the GPU */
1053 a6xx_rpmh_stop(gmu);
1054 }
1055
1056
1057 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1058 {
1059 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1060 struct msm_gpu *gpu = &a6xx_gpu->base.base;
1061
1062 if (!pm_runtime_active(gmu->dev))
1063 return 0;
1064
1065 /*
1066 * Force the GMU off if we detected a hang, otherwise try to shut it
1067 * down gracefully
1068 */
1069 if (gmu->hung)
1070 a6xx_gmu_force_off(gmu);
1071 else
1072 a6xx_gmu_shutdown(gmu);
1073
1074 /* Remove the bus vote */
1075 dev_pm_opp_set_bw(&gpu->pdev->dev, NULL);
1076
1077 /*
1078 * Make sure the GX domain is off before turning off the GMU (CX)
1079 * domain. Usually the GMU does this but only if the shutdown sequence
1080 * was successful
1081 */
1082 if (!IS_ERR_OR_NULL(gmu->gxpd))
1083 pm_runtime_put_sync(gmu->gxpd);
1084
1085 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1086
1087 pm_runtime_put_sync(gmu->dev);
1088
1089 return 0;
1090 }
1091
1092 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1093 {
1094 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false);
1095 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false);
1096 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false);
1097 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false);
1098 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false);
1099 msm_gem_kernel_put(gmu->log.obj, gmu->aspace, false);
1100
1101 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1102 msm_gem_address_space_put(gmu->aspace);
1103 }
1104
1105 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1106 size_t size, u64 iova)
1107 {
1108 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1109 struct drm_device *dev = a6xx_gpu->base.base.dev;
1110 uint32_t flags = MSM_BO_WC;
1111 u64 range_start, range_end;
1112 int ret;
1113
1114 size = PAGE_ALIGN(size);
1115 if (!iova) {
1116 /* no fixed address - use GMU's uncached range */
1117 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1118 range_end = 0x80000000;
1119 } else {
1120 /* range for fixed address */
1121 range_start = iova;
1122 range_end = iova + size;
1123 /* use IOMMU_PRIV for icache/dcache */
1124 flags |= MSM_BO_MAP_PRIV;
1125 }
1126
1127 bo->obj = msm_gem_new(dev, size, flags);
1128 if (IS_ERR(bo->obj))
1129 return PTR_ERR(bo->obj);
1130
1131 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1132 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT);
1133 if (ret) {
1134 drm_gem_object_put(bo->obj);
1135 return ret;
1136 }
1137
1138 bo->virt = msm_gem_get_vaddr(bo->obj);
1139 bo->size = size;
1140
1141 return 0;
1142 }
1143
1144 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1145 {
1146 struct iommu_domain *domain;
1147 struct msm_mmu *mmu;
1148
1149 domain = iommu_domain_alloc(&platform_bus_type);
1150 if (!domain)
1151 return -ENODEV;
1152
1153 mmu = msm_iommu_new(gmu->dev, domain);
1154 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1155 if (IS_ERR(gmu->aspace)) {
1156 iommu_domain_free(domain);
1157 return PTR_ERR(gmu->aspace);
1158 }
1159
1160 return 0;
1161 }
1162
1163 /* Return the 'arc-level' for the given frequency */
1164 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1165 unsigned long freq)
1166 {
1167 struct dev_pm_opp *opp;
1168 unsigned int val;
1169
1170 if (!freq)
1171 return 0;
1172
1173 opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1174 if (IS_ERR(opp))
1175 return 0;
1176
1177 val = dev_pm_opp_get_level(opp);
1178
1179 dev_pm_opp_put(opp);
1180
1181 return val;
1182 }
1183
1184 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1185 unsigned long *freqs, int freqs_count, const char *id)
1186 {
1187 int i, j;
1188 const u16 *pri, *sec;
1189 size_t pri_count, sec_count;
1190
1191 pri = cmd_db_read_aux_data(id, &pri_count);
1192 if (IS_ERR(pri))
1193 return PTR_ERR(pri);
1194 /*
1195 * The data comes back as an array of unsigned shorts so adjust the
1196 * count accordingly
1197 */
1198 pri_count >>= 1;
1199 if (!pri_count)
1200 return -EINVAL;
1201
1202 sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1203 if (IS_ERR(sec))
1204 return PTR_ERR(sec);
1205
1206 sec_count >>= 1;
1207 if (!sec_count)
1208 return -EINVAL;
1209
1210 /* Construct a vote for each frequency */
1211 for (i = 0; i < freqs_count; i++) {
1212 u8 pindex = 0, sindex = 0;
1213 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1214
1215 /* Get the primary index that matches the arc level */
1216 for (j = 0; j < pri_count; j++) {
1217 if (pri[j] >= level) {
1218 pindex = j;
1219 break;
1220 }
1221 }
1222
1223 if (j == pri_count) {
1224 DRM_DEV_ERROR(dev,
1225 "Level %u not found in the RPMh list\n",
1226 level);
1227 DRM_DEV_ERROR(dev, "Available levels:\n");
1228 for (j = 0; j < pri_count; j++)
1229 DRM_DEV_ERROR(dev, " %u\n", pri[j]);
1230
1231 return -EINVAL;
1232 }
1233
1234 /*
1235 * Look for a level in in the secondary list that matches. If
1236 * nothing fits, use the maximum non zero vote
1237 */
1238
1239 for (j = 0; j < sec_count; j++) {
1240 if (sec[j] >= level) {
1241 sindex = j;
1242 break;
1243 } else if (sec[j]) {
1244 sindex = j;
1245 }
1246 }
1247
1248 /* Construct the vote */
1249 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1250 (sindex << 8) | pindex;
1251 }
1252
1253 return 0;
1254 }
1255
1256 /*
1257 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1258 * to construct the list of votes on the CPU and send it over. Query the RPMh
1259 * voltage levels and build the votes
1260 */
1261
1262 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1263 {
1264 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1265 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1266 struct msm_gpu *gpu = &adreno_gpu->base;
1267 int ret;
1268
1269 /* Build the GX votes */
1270 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1271 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1272
1273 /* Build the CX votes */
1274 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1275 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1276
1277 return ret;
1278 }
1279
1280 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1281 u32 size)
1282 {
1283 int count = dev_pm_opp_get_opp_count(dev);
1284 struct dev_pm_opp *opp;
1285 int i, index = 0;
1286 unsigned long freq = 1;
1287
1288 /*
1289 * The OPP table doesn't contain the "off" frequency level so we need to
1290 * add 1 to the table size to account for it
1291 */
1292
1293 if (WARN(count + 1 > size,
1294 "The GMU frequency table is being truncated\n"))
1295 count = size - 1;
1296
1297 /* Set the "off" frequency */
1298 freqs[index++] = 0;
1299
1300 for (i = 0; i < count; i++) {
1301 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1302 if (IS_ERR(opp))
1303 break;
1304
1305 dev_pm_opp_put(opp);
1306 freqs[index++] = freq++;
1307 }
1308
1309 return index;
1310 }
1311
1312 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1313 {
1314 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1315 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1316 struct msm_gpu *gpu = &adreno_gpu->base;
1317
1318 int ret = 0;
1319
1320 /*
1321 * The GMU handles its own frequency switching so build a list of
1322 * available frequencies to send during initialization
1323 */
1324 ret = dev_pm_opp_of_add_table(gmu->dev);
1325 if (ret) {
1326 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1327 return ret;
1328 }
1329
1330 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1331 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1332
1333 /*
1334 * The GMU also handles GPU frequency switching so build a list
1335 * from the GPU OPP table
1336 */
1337 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1338 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1339
1340 gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1341
1342 /* Build the list of RPMh votes that we'll send to the GMU */
1343 return a6xx_gmu_rpmh_votes_init(gmu);
1344 }
1345
1346 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1347 {
1348 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1349
1350 if (ret < 1)
1351 return ret;
1352
1353 gmu->nr_clocks = ret;
1354
1355 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1356 gmu->nr_clocks, "gmu");
1357
1358 return 0;
1359 }
1360
1361 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1362 const char *name)
1363 {
1364 void __iomem *ret;
1365 struct resource *res = platform_get_resource_byname(pdev,
1366 IORESOURCE_MEM, name);
1367
1368 if (!res) {
1369 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1370 return ERR_PTR(-EINVAL);
1371 }
1372
1373 ret = ioremap(res->start, resource_size(res));
1374 if (!ret) {
1375 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1376 return ERR_PTR(-EINVAL);
1377 }
1378
1379 return ret;
1380 }
1381
1382 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1383 const char *name, irq_handler_t handler)
1384 {
1385 int irq, ret;
1386
1387 irq = platform_get_irq_byname(pdev, name);
1388
1389 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1390 if (ret) {
1391 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1392 name, ret);
1393 return ret;
1394 }
1395
1396 disable_irq(irq);
1397
1398 return irq;
1399 }
1400
1401 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1402 {
1403 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1404 struct platform_device *pdev = to_platform_device(gmu->dev);
1405
1406 if (!gmu->initialized)
1407 return;
1408
1409 pm_runtime_force_suspend(gmu->dev);
1410
1411 if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1412 pm_runtime_disable(gmu->gxpd);
1413 dev_pm_domain_detach(gmu->gxpd, false);
1414 }
1415
1416 iounmap(gmu->mmio);
1417 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1418 iounmap(gmu->rscc);
1419 gmu->mmio = NULL;
1420 gmu->rscc = NULL;
1421
1422 a6xx_gmu_memory_free(gmu);
1423
1424 free_irq(gmu->gmu_irq, gmu);
1425 free_irq(gmu->hfi_irq, gmu);
1426
1427 /* Drop reference taken in of_find_device_by_node */
1428 put_device(gmu->dev);
1429
1430 gmu->initialized = false;
1431 }
1432
1433 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1434 {
1435 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1436 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1437 struct platform_device *pdev = of_find_device_by_node(node);
1438 int ret;
1439
1440 if (!pdev)
1441 return -ENODEV;
1442
1443 gmu->dev = &pdev->dev;
1444
1445 of_dma_configure(gmu->dev, node, true);
1446
1447 /* Fow now, don't do anything fancy until we get our feet under us */
1448 gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1449
1450 pm_runtime_enable(gmu->dev);
1451
1452 /* Get the list of clocks */
1453 ret = a6xx_gmu_clocks_probe(gmu);
1454 if (ret)
1455 goto err_put_device;
1456
1457 ret = a6xx_gmu_memory_probe(gmu);
1458 if (ret)
1459 goto err_put_device;
1460
1461 /* Allocate memory for the GMU dummy page */
1462 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
1463 if (ret)
1464 goto err_memory;
1465
1466 if (adreno_is_a650(adreno_gpu)) {
1467 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1468 SZ_16M - SZ_16K, 0x04000);
1469 if (ret)
1470 goto err_memory;
1471 } else if (adreno_is_a640(adreno_gpu)) {
1472 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1473 SZ_256K - SZ_16K, 0x04000);
1474 if (ret)
1475 goto err_memory;
1476
1477 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1478 SZ_256K - SZ_16K, 0x44000);
1479 if (ret)
1480 goto err_memory;
1481 } else {
1482 /* HFI v1, has sptprac */
1483 gmu->legacy = true;
1484
1485 /* Allocate memory for the GMU debug region */
1486 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0);
1487 if (ret)
1488 goto err_memory;
1489 }
1490
1491 /* Allocate memory for for the HFI queues */
1492 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0);
1493 if (ret)
1494 goto err_memory;
1495
1496 /* Allocate memory for the GMU log region */
1497 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0);
1498 if (ret)
1499 goto err_memory;
1500
1501 /* Map the GMU registers */
1502 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1503 if (IS_ERR(gmu->mmio)) {
1504 ret = PTR_ERR(gmu->mmio);
1505 goto err_memory;
1506 }
1507
1508 if (adreno_is_a650(adreno_gpu)) {
1509 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1510 if (IS_ERR(gmu->rscc))
1511 goto err_mmio;
1512 } else {
1513 gmu->rscc = gmu->mmio + 0x23000;
1514 }
1515
1516 /* Get the HFI and GMU interrupts */
1517 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1518 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1519
1520 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
1521 goto err_mmio;
1522
1523 /*
1524 * Get a link to the GX power domain to reset the GPU in case of GMU
1525 * crash
1526 */
1527 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1528
1529 /* Get the power levels for the GMU and GPU */
1530 a6xx_gmu_pwrlevels_probe(gmu);
1531
1532 /* Set up the HFI queues */
1533 a6xx_hfi_init(gmu);
1534
1535 gmu->initialized = true;
1536
1537 return 0;
1538
1539 err_mmio:
1540 iounmap(gmu->mmio);
1541 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1542 iounmap(gmu->rscc);
1543 free_irq(gmu->gmu_irq, gmu);
1544 free_irq(gmu->hfi_irq, gmu);
1545
1546 ret = -ENODEV;
1547
1548 err_memory:
1549 a6xx_gmu_memory_free(gmu);
1550 err_put_device:
1551 /* Drop reference taken in of_find_device_by_node */
1552 put_device(gmu->dev);
1553
1554 return ret;
1555 }
Linux with added FPC-III support