drivers/gpu/drm/msm/adreno/a6xx_gmu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
   3
   4 #ifndef _A6XX_GMU_H_
   5 #define _A6XX_GMU_H_
   6
   7 #include <linux/iopoll.h>
   8 #include <linux/interrupt.h>
   9 #include "msm_drv.h"
  10 #include "a6xx_hfi.h"
  11
  12 struct a6xx_gmu_bo {
  13         struct drm_gem_object *obj;
  14         void *virt;
  15         size_t size;
  16         u64 iova;
  17 };
  18
  19 /*
  20  * These define the different GMU wake up options - these define how both the
  21  * CPU and the GMU bring up the hardware
  22  */
  23
  24 /* THe GMU has already been booted and the rentention registers are active */
  25 #define GMU_WARM_BOOT 0
  26
  27 /* the GMU is coming up for the first time or back from a power collapse */
  28 #define GMU_COLD_BOOT 1
  29
  30 /*
  31  * These define the level of control that the GMU has - the higher the number
  32  * the more things that the GMU hardware controls on its own.
  33  */
  34
  35 /* The GMU does not do any idle state management */
  36 #define GMU_IDLE_STATE_ACTIVE 0
  37
  38 /* The GMU manages SPTP power collapse */
  39 #define GMU_IDLE_STATE_SPTP 2
  40
  41 /* The GMU does automatic IFPC (intra-frame power collapse) */
  42 #define GMU_IDLE_STATE_IFPC 3
  43
  44 struct a6xx_gmu {
  45         struct device *dev;
  46
  47         struct msm_gem_address_space *aspace;
  48
  49         void * __iomem mmio;
  50         void * __iomem rscc;
  51
  52         int hfi_irq;
  53         int gmu_irq;
  54
  55         struct device *gxpd;
  56
  57         int idle_level;
  58
  59         struct a6xx_gmu_bo hfi;
  60         struct a6xx_gmu_bo debug;
  61         struct a6xx_gmu_bo icache;
  62         struct a6xx_gmu_bo dcache;
  63         struct a6xx_gmu_bo dummy;
  64         struct a6xx_gmu_bo log;
  65
  66         int nr_clocks;
  67         struct clk_bulk_data *clocks;
  68         struct clk *core_clk;
  69
  70         /* current performance index set externally */
  71         int current_perf_index;
  72
  73         int nr_gpu_freqs;
  74         unsigned long gpu_freqs[16];
  75         u32 gx_arc_votes[16];
  76
  77         int nr_gmu_freqs;
  78         unsigned long gmu_freqs[4];
  79         u32 cx_arc_votes[4];
  80
  81         unsigned long freq;
  82
  83         struct a6xx_hfi_queue queues[2];
  84
  85         bool initialized;
  86         bool hung;
  87         bool legacy; /* a618 or a630 */
  88 };
  89
  90 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
  91 {
  92         return msm_readl(gmu->mmio + (offset << 2));
  93 }
  94
  95 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
  96 {
  97         return msm_writel(value, gmu->mmio + (offset << 2));
  98 }
  99
 100 static inline void
 101 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
 102 {
 103         memcpy_toio(gmu->mmio + (offset << 2), data, size);
 104         wmb();
 105 }
 106
 107 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
 108 {
 109         u32 val = gmu_read(gmu, reg);
 110
 111         val &= ~mask;
 112
 113         gmu_write(gmu, reg, val | or);
 114 }
 115
 116 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
 117 {
 118         u64 val;
 119
 120         val = (u64) msm_readl(gmu->mmio + (lo << 2));
 121         val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
 122
 123         return val;
 124 }
 125
 126 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
 127         readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
 128                 interval, timeout)
 129
 130 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
 131 {
 132         return msm_readl(gmu->rscc + (offset << 2));
 133 }
 134
 135 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
 136 {
 137         return msm_writel(value, gmu->rscc + (offset << 2));
 138 }
 139
 140 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
 141         readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
 142                 interval, timeout)
 143
 144 /*
 145  * These are the available OOB (out of band requests) to the GMU where "out of
 146  * band" means that the CPU talks to the GMU directly and not through HFI.
 147  * Normally this works by writing a ITCM/DTCM register and then triggering a
 148  * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
 149  * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
 150  *
 151  * These are used to force the GMU/GPU to stay on during a critical sequence or
 152  * for hardware workarounds.
 153  */
 154
 155 enum a6xx_gmu_oob_state {
 156         GMU_OOB_BOOT_SLUMBER = 0,
 157         GMU_OOB_GPU_SET,
 158         GMU_OOB_DCVS_SET,
 159 };
 160
 161 /* These are the interrupt / ack bits for each OOB request that are set
 162  * in a6xx_gmu_set_oob and a6xx_clear_oob
 163  */
 164
 165 /*
 166  * Let the GMU know that a boot or slumber operation has started. The value in
 167  * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
 168  * doing
 169  */
 170 #define GMU_OOB_BOOT_SLUMBER_REQUEST    22
 171 #define GMU_OOB_BOOT_SLUMBER_ACK        30
 172 #define GMU_OOB_BOOT_SLUMBER_CLEAR      30
 173
 174 /*
 175  * Set a new power level for the GPU when the CPU is doing frequency scaling
 176  */
 177 #define GMU_OOB_DCVS_REQUEST    23
 178 #define GMU_OOB_DCVS_ACK        31
 179 #define GMU_OOB_DCVS_CLEAR      31
 180
 181 /*
 182  * Let the GMU know to not turn off any GPU registers while the CPU is in a
 183  * critical section
 184  */
 185 #define GMU_OOB_GPU_SET_REQUEST 16
 186 #define GMU_OOB_GPU_SET_ACK     24
 187 #define GMU_OOB_GPU_SET_CLEAR   24
 188
 189 #define GMU_OOB_GPU_SET_REQUEST_NEW     30
 190 #define GMU_OOB_GPU_SET_ACK_NEW         31
 191 #define GMU_OOB_GPU_SET_CLEAR_NEW       31
 192
 193
 194 void a6xx_hfi_init(struct a6xx_gmu *gmu);
 195 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
 196 void a6xx_hfi_stop(struct a6xx_gmu *gmu);
 197 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
 198 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
 199
 200 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
 201 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
 202
 203 #endif