drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
   4  */
   5
   6 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   7 #include "dpu_encoder_phys.h"
   8 #include "dpu_hw_interrupts.h"
   9 #include "dpu_core_irq.h"
  10 #include "dpu_formats.h"
  11 #include "dpu_trace.h"
  12
  13 #define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
  14                 (e) && (e)->base.parent ? \
  15                 (e)->base.parent->base.id : -1, \
  16                 (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
  17
  18 #define DPU_ERROR_CMDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
  19                 (e) && (e)->base.parent ? \
  20                 (e)->base.parent->base.id : -1, \
  21                 (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
  22
  23 #define to_dpu_encoder_phys_cmd(x) \
  24         container_of(x, struct dpu_encoder_phys_cmd, base)
  25
  26 #define PP_TIMEOUT_MAX_TRIALS   10
  27
  28 /*
  29  * Tearcheck sync start and continue thresholds are empirically found
  30  * based on common panels In the future, may want to allow panels to override
  31  * these default values
  32  */
  33 #define DEFAULT_TEARCHECK_SYNC_THRESH_START     4
  34 #define DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE  4
  35
  36 #define DPU_ENC_WR_PTR_START_TIMEOUT_US 20000
  37
  38 static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc)
  39 {
  40         return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false;
  41 }
  42
  43 static bool dpu_encoder_phys_cmd_mode_fixup(
  44                 struct dpu_encoder_phys *phys_enc,
  45                 const struct drm_display_mode *mode,
  46                 struct drm_display_mode *adj_mode)
  47 {
  48         DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n");
  49         return true;
  50 }
  51
  52 static void _dpu_encoder_phys_cmd_update_intf_cfg(
  53                 struct dpu_encoder_phys *phys_enc)
  54 {
  55         struct dpu_encoder_phys_cmd *cmd_enc =
  56                         to_dpu_encoder_phys_cmd(phys_enc);
  57         struct dpu_hw_ctl *ctl;
  58         struct dpu_hw_intf_cfg intf_cfg = { 0 };
  59
  60         ctl = phys_enc->hw_ctl;
  61         if (!ctl->ops.setup_intf_cfg)
  62                 return;
  63
  64         intf_cfg.intf = phys_enc->intf_idx;
  65         intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
  66         intf_cfg.stream_sel = cmd_enc->stream_sel;
  67         intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
  68         ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
  69 }
  70
  71 static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
  72 {
  73         struct dpu_encoder_phys *phys_enc = arg;
  74         unsigned long lock_flags;
  75         int new_cnt;
  76         u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
  77
  78         if (!phys_enc->hw_pp)
  79                 return;
  80
  81         DPU_ATRACE_BEGIN("pp_done_irq");
  82         /* notify all synchronous clients first, then asynchronous clients */
  83         if (phys_enc->parent_ops->handle_frame_done)
  84                 phys_enc->parent_ops->handle_frame_done(phys_enc->parent,
  85                                 phys_enc, event);
  86
  87         spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  88         new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
  89         spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  90
  91         trace_dpu_enc_phys_cmd_pp_tx_done(DRMID(phys_enc->parent),
  92                                           phys_enc->hw_pp->idx - PINGPONG_0,
  93                                           new_cnt, event);
  94
  95         /* Signal any waiting atomic commit thread */
  96         wake_up_all(&phys_enc->pending_kickoff_wq);
  97         DPU_ATRACE_END("pp_done_irq");
  98 }
  99
 100 static void dpu_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx)
 101 {
 102         struct dpu_encoder_phys *phys_enc = arg;
 103         struct dpu_encoder_phys_cmd *cmd_enc;
 104
 105         if (!phys_enc->hw_pp)
 106                 return;
 107
 108         DPU_ATRACE_BEGIN("rd_ptr_irq");
 109         cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
 110
 111         if (phys_enc->parent_ops->handle_vblank_virt)
 112                 phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
 113                         phys_enc);
 114
 115         atomic_add_unless(&cmd_enc->pending_vblank_cnt, -1, 0);
 116         wake_up_all(&cmd_enc->pending_vblank_wq);
 117         DPU_ATRACE_END("rd_ptr_irq");
 118 }
 119
 120 static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx)
 121 {
 122         struct dpu_encoder_phys *phys_enc = arg;
 123
 124         DPU_ATRACE_BEGIN("ctl_start_irq");
 125
 126         atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0);
 127
 128         /* Signal any waiting ctl start interrupt */
 129         wake_up_all(&phys_enc->pending_kickoff_wq);
 130         DPU_ATRACE_END("ctl_start_irq");
 131 }
 132
 133 static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
 134 {
 135         struct dpu_encoder_phys *phys_enc = arg;
 136
 137         if (phys_enc->parent_ops->handle_underrun_virt)
 138                 phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
 139                         phys_enc);
 140 }
 141
 142 static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
 143                 struct dpu_encoder_phys *phys_enc)
 144 {
 145         struct dpu_encoder_irq *irq;
 146
 147         irq = &phys_enc->irq[INTR_IDX_CTL_START];
 148         irq->hw_idx = phys_enc->hw_ctl->idx;
 149         irq->irq_idx = -EINVAL;
 150
 151         irq = &phys_enc->irq[INTR_IDX_PINGPONG];
 152         irq->hw_idx = phys_enc->hw_pp->idx;
 153         irq->irq_idx = -EINVAL;
 154
 155         irq = &phys_enc->irq[INTR_IDX_RDPTR];
 156         irq->hw_idx = phys_enc->hw_pp->idx;
 157         irq->irq_idx = -EINVAL;
 158
 159         irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
 160         irq->hw_idx = phys_enc->intf_idx;
 161         irq->irq_idx = -EINVAL;
 162 }
 163
 164 static void dpu_encoder_phys_cmd_mode_set(
 165                 struct dpu_encoder_phys *phys_enc,
 166                 struct drm_display_mode *mode,
 167                 struct drm_display_mode *adj_mode)
 168 {
 169         struct dpu_encoder_phys_cmd *cmd_enc =
 170                 to_dpu_encoder_phys_cmd(phys_enc);
 171
 172         if (!mode || !adj_mode) {
 173                 DPU_ERROR("invalid args\n");
 174                 return;
 175         }
 176         phys_enc->cached_mode = *adj_mode;
 177         DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
 178         drm_mode_debug_printmodeline(adj_mode);
 179
 180         _dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
 181 }
 182
 183 static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
 184                 struct dpu_encoder_phys *phys_enc)
 185 {
 186         struct dpu_encoder_phys_cmd *cmd_enc =
 187                         to_dpu_encoder_phys_cmd(phys_enc);
 188         u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
 189         bool do_log = false;
 190
 191         if (!phys_enc->hw_pp)
 192                 return -EINVAL;
 193
 194         cmd_enc->pp_timeout_report_cnt++;
 195         if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) {
 196                 frame_event |= DPU_ENCODER_FRAME_EVENT_PANEL_DEAD;
 197                 do_log = true;
 198         } else if (cmd_enc->pp_timeout_report_cnt == 1) {
 199                 do_log = true;
 200         }
 201
 202         trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent),
 203                      phys_enc->hw_pp->idx - PINGPONG_0,
 204                      cmd_enc->pp_timeout_report_cnt,
 205                      atomic_read(&phys_enc->pending_kickoff_cnt),
 206                      frame_event);
 207
 208         /* to avoid flooding, only log first time, and "dead" time */
 209         if (do_log) {
 210                 DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",
 211                           DRMID(phys_enc->parent),
 212                           phys_enc->hw_pp->idx - PINGPONG_0,
 213                           phys_enc->hw_ctl->idx - CTL_0,
 214                           cmd_enc->pp_timeout_report_cnt,
 215                           atomic_read(&phys_enc->pending_kickoff_cnt));
 216
 217                 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
 218         }
 219
 220         atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
 221
 222         /* request a ctl reset before the next kickoff */
 223         phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
 224
 225         if (phys_enc->parent_ops->handle_frame_done)
 226                 phys_enc->parent_ops->handle_frame_done(
 227                                 phys_enc->parent, phys_enc, frame_event);
 228
 229         return -ETIMEDOUT;
 230 }
 231
 232 static int _dpu_encoder_phys_cmd_wait_for_idle(
 233                 struct dpu_encoder_phys *phys_enc)
 234 {
 235         struct dpu_encoder_phys_cmd *cmd_enc =
 236                         to_dpu_encoder_phys_cmd(phys_enc);
 237         struct dpu_encoder_wait_info wait_info;
 238         int ret;
 239
 240         wait_info.wq = &phys_enc->pending_kickoff_wq;
 241         wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
 242         wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 243
 244         ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_PINGPONG,
 245                         &wait_info);
 246         if (ret == -ETIMEDOUT)
 247                 _dpu_encoder_phys_cmd_handle_ppdone_timeout(phys_enc);
 248         else if (!ret)
 249                 cmd_enc->pp_timeout_report_cnt = 0;
 250
 251         return ret;
 252 }
 253
 254 static int dpu_encoder_phys_cmd_control_vblank_irq(
 255                 struct dpu_encoder_phys *phys_enc,
 256                 bool enable)
 257 {
 258         int ret = 0;
 259         int refcount;
 260
 261         if (!phys_enc->hw_pp) {
 262                 DPU_ERROR("invalid encoder\n");
 263                 return -EINVAL;
 264         }
 265
 266         refcount = atomic_read(&phys_enc->vblank_refcount);
 267
 268         /* Slave encoders don't report vblank */
 269         if (!dpu_encoder_phys_cmd_is_master(phys_enc))
 270                 goto end;
 271
 272         /* protect against negative */
 273         if (!enable && refcount == 0) {
 274                 ret = -EINVAL;
 275                 goto end;
 276         }
 277
 278         DRM_DEBUG_KMS("id:%u pp:%d enable=%s/%d\n", DRMID(phys_enc->parent),
 279                       phys_enc->hw_pp->idx - PINGPONG_0,
 280                       enable ? "true" : "false", refcount);
 281
 282         if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
 283                 ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_RDPTR);
 284         else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
 285                 ret = dpu_encoder_helper_unregister_irq(phys_enc,
 286                                 INTR_IDX_RDPTR);
 287
 288 end:
 289         if (ret) {
 290                 DRM_ERROR("vblank irq err id:%u pp:%d ret:%d, enable %s/%d\n",
 291                           DRMID(phys_enc->parent),
 292                           phys_enc->hw_pp->idx - PINGPONG_0, ret,
 293                           enable ? "true" : "false", refcount);
 294         }
 295
 296         return ret;
 297 }
 298
 299 static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
 300                 bool enable)
 301 {
 302         trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent),
 303                         phys_enc->hw_pp->idx - PINGPONG_0,
 304                         enable, atomic_read(&phys_enc->vblank_refcount));
 305
 306         if (enable) {
 307                 dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_PINGPONG);
 308                 dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
 309                 dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
 310
 311                 if (dpu_encoder_phys_cmd_is_master(phys_enc))
 312                         dpu_encoder_helper_register_irq(phys_enc,
 313                                         INTR_IDX_CTL_START);
 314         } else {
 315                 if (dpu_encoder_phys_cmd_is_master(phys_enc))
 316                         dpu_encoder_helper_unregister_irq(phys_enc,
 317                                         INTR_IDX_CTL_START);
 318
 319                 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
 320                 dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
 321                 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_PINGPONG);
 322         }
 323 }
 324
 325 static void dpu_encoder_phys_cmd_tearcheck_config(
 326                 struct dpu_encoder_phys *phys_enc)
 327 {
 328         struct dpu_encoder_phys_cmd *cmd_enc =
 329                 to_dpu_encoder_phys_cmd(phys_enc);
 330         struct dpu_hw_tear_check tc_cfg = { 0 };
 331         struct drm_display_mode *mode;
 332         bool tc_enable = true;
 333         u32 vsync_hz;
 334         struct dpu_kms *dpu_kms;
 335
 336         if (!phys_enc->hw_pp) {
 337                 DPU_ERROR("invalid encoder\n");
 338                 return;
 339         }
 340         mode = &phys_enc->cached_mode;
 341
 342         DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 343
 344         if (!phys_enc->hw_pp->ops.setup_tearcheck ||
 345                 !phys_enc->hw_pp->ops.enable_tearcheck) {
 346                 DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
 347                 return;
 348         }
 349
 350         dpu_kms = phys_enc->dpu_kms;
 351
 352         /*
 353          * TE default: dsi byte clock calculated base on 70 fps;
 354          * around 14 ms to complete a kickoff cycle if te disabled;
 355          * vclk_line base on 60 fps; write is faster than read;
 356          * init == start == rdptr;
 357          *
 358          * vsync_count is ratio of MDP VSYNC clock frequency to LCD panel
 359          * frequency divided by the no. of rows (lines) in the LCDpanel.
 360          */
 361         vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync");
 362         if (vsync_hz <= 0) {
 363                 DPU_DEBUG_CMDENC(cmd_enc, "invalid - vsync_hz %u\n",
 364                                  vsync_hz);
 365                 return;
 366         }
 367
 368         tc_cfg.vsync_count = vsync_hz /
 369                                 (mode->vtotal * drm_mode_vrefresh(mode));
 370
 371         /* enable external TE after kickoff to avoid premature autorefresh */
 372         tc_cfg.hw_vsync_mode = 0;
 373
 374         /*
 375          * By setting sync_cfg_height to near max register value, we essentially
 376          * disable dpu hw generated TE signal, since hw TE will arrive first.
 377          * Only caveat is if due to error, we hit wrap-around.
 378          */
 379         tc_cfg.sync_cfg_height = 0xFFF0;
 380         tc_cfg.vsync_init_val = mode->vdisplay;
 381         tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START;
 382         tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE;
 383         tc_cfg.start_pos = mode->vdisplay;
 384         tc_cfg.rd_ptr_irq = mode->vdisplay + 1;
 385
 386         DPU_DEBUG_CMDENC(cmd_enc,
 387                 "tc %d vsync_clk_speed_hz %u vtotal %u vrefresh %u\n",
 388                 phys_enc->hw_pp->idx - PINGPONG_0, vsync_hz,
 389                 mode->vtotal, drm_mode_vrefresh(mode));
 390         DPU_DEBUG_CMDENC(cmd_enc,
 391                 "tc %d enable %u start_pos %u rd_ptr_irq %u\n",
 392                 phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos,
 393                 tc_cfg.rd_ptr_irq);
 394         DPU_DEBUG_CMDENC(cmd_enc,
 395                 "tc %d hw_vsync_mode %u vsync_count %u vsync_init_val %u\n",
 396                 phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.hw_vsync_mode,
 397                 tc_cfg.vsync_count, tc_cfg.vsync_init_val);
 398         DPU_DEBUG_CMDENC(cmd_enc,
 399                 "tc %d cfgheight %u thresh_start %u thresh_cont %u\n",
 400                 phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height,
 401                 tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue);
 402
 403         phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg);
 404         phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable);
 405 }
 406
 407 static void _dpu_encoder_phys_cmd_pingpong_config(
 408                 struct dpu_encoder_phys *phys_enc)
 409 {
 410         struct dpu_encoder_phys_cmd *cmd_enc =
 411                 to_dpu_encoder_phys_cmd(phys_enc);
 412
 413         if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) {
 414                 DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != NULL);
 415                 return;
 416         }
 417
 418         DPU_DEBUG_CMDENC(cmd_enc, "pp %d, enabling mode:\n",
 419                         phys_enc->hw_pp->idx - PINGPONG_0);
 420         drm_mode_debug_printmodeline(&phys_enc->cached_mode);
 421
 422         _dpu_encoder_phys_cmd_update_intf_cfg(phys_enc);
 423         dpu_encoder_phys_cmd_tearcheck_config(phys_enc);
 424 }
 425
 426 static bool dpu_encoder_phys_cmd_needs_single_flush(
 427                 struct dpu_encoder_phys *phys_enc)
 428 {
 429         /**
 430          * we do separate flush for each CTL and let
 431          * CTL_START synchronize them
 432          */
 433         return false;
 434 }
 435
 436 static void dpu_encoder_phys_cmd_enable_helper(
 437                 struct dpu_encoder_phys *phys_enc)
 438 {
 439         struct dpu_hw_ctl *ctl;
 440
 441         if (!phys_enc->hw_pp) {
 442                 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
 443                 return;
 444         }
 445
 446         dpu_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);
 447
 448         _dpu_encoder_phys_cmd_pingpong_config(phys_enc);
 449
 450         if (!dpu_encoder_phys_cmd_is_master(phys_enc))
 451                 return;
 452
 453         ctl = phys_enc->hw_ctl;
 454         ctl->ops.update_pending_flush_intf(ctl, phys_enc->intf_idx);
 455 }
 456
 457 static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc)
 458 {
 459         struct dpu_encoder_phys_cmd *cmd_enc =
 460                 to_dpu_encoder_phys_cmd(phys_enc);
 461
 462         if (!phys_enc->hw_pp) {
 463                 DPU_ERROR("invalid phys encoder\n");
 464                 return;
 465         }
 466
 467         DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 468
 469         if (phys_enc->enable_state == DPU_ENC_ENABLED) {
 470                 DPU_ERROR("already enabled\n");
 471                 return;
 472         }
 473
 474         dpu_encoder_phys_cmd_enable_helper(phys_enc);
 475         phys_enc->enable_state = DPU_ENC_ENABLED;
 476 }
 477
 478 static void _dpu_encoder_phys_cmd_connect_te(
 479                 struct dpu_encoder_phys *phys_enc, bool enable)
 480 {
 481         if (!phys_enc->hw_pp || !phys_enc->hw_pp->ops.connect_external_te)
 482                 return;
 483
 484         trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable);
 485         phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable);
 486 }
 487
 488 static void dpu_encoder_phys_cmd_prepare_idle_pc(
 489                 struct dpu_encoder_phys *phys_enc)
 490 {
 491         _dpu_encoder_phys_cmd_connect_te(phys_enc, false);
 492 }
 493
 494 static int dpu_encoder_phys_cmd_get_line_count(
 495                 struct dpu_encoder_phys *phys_enc)
 496 {
 497         struct dpu_hw_pingpong *hw_pp;
 498
 499         if (!phys_enc->hw_pp)
 500                 return -EINVAL;
 501
 502         if (!dpu_encoder_phys_cmd_is_master(phys_enc))
 503                 return -EINVAL;
 504
 505         hw_pp = phys_enc->hw_pp;
 506         if (!hw_pp->ops.get_line_count)
 507                 return -EINVAL;
 508
 509         return hw_pp->ops.get_line_count(hw_pp);
 510 }
 511
 512 static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)
 513 {
 514         struct dpu_encoder_phys_cmd *cmd_enc =
 515                 to_dpu_encoder_phys_cmd(phys_enc);
 516
 517         if (!phys_enc->hw_pp) {
 518                 DPU_ERROR("invalid encoder\n");
 519                 return;
 520         }
 521         DRM_DEBUG_KMS("id:%u pp:%d state:%d\n", DRMID(phys_enc->parent),
 522                       phys_enc->hw_pp->idx - PINGPONG_0,
 523                       phys_enc->enable_state);
 524
 525         if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 526                 DPU_ERROR_CMDENC(cmd_enc, "already disabled\n");
 527                 return;
 528         }
 529
 530         if (phys_enc->hw_pp->ops.enable_tearcheck)
 531                 phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false);
 532         phys_enc->enable_state = DPU_ENC_DISABLED;
 533 }
 534
 535 static void dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc)
 536 {
 537         struct dpu_encoder_phys_cmd *cmd_enc =
 538                 to_dpu_encoder_phys_cmd(phys_enc);
 539
 540         kfree(cmd_enc);
 541 }
 542
 543 static void dpu_encoder_phys_cmd_get_hw_resources(
 544                 struct dpu_encoder_phys *phys_enc,
 545                 struct dpu_encoder_hw_resources *hw_res)
 546 {
 547         hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_CMD;
 548 }
 549
 550 static void dpu_encoder_phys_cmd_prepare_for_kickoff(
 551                 struct dpu_encoder_phys *phys_enc)
 552 {
 553         struct dpu_encoder_phys_cmd *cmd_enc =
 554                         to_dpu_encoder_phys_cmd(phys_enc);
 555         int ret;
 556
 557         if (!phys_enc->hw_pp) {
 558                 DPU_ERROR("invalid encoder\n");
 559                 return;
 560         }
 561         DRM_DEBUG_KMS("id:%u pp:%d pending_cnt:%d\n", DRMID(phys_enc->parent),
 562                       phys_enc->hw_pp->idx - PINGPONG_0,
 563                       atomic_read(&phys_enc->pending_kickoff_cnt));
 564
 565         /*
 566          * Mark kickoff request as outstanding. If there are more than one,
 567          * outstanding, then we have to wait for the previous one to complete
 568          */
 569         ret = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc);
 570         if (ret) {
 571                 /* force pending_kickoff_cnt 0 to discard failed kickoff */
 572                 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 573                 DRM_ERROR("failed wait_for_idle: id:%u ret:%d pp:%d\n",
 574                           DRMID(phys_enc->parent), ret,
 575                           phys_enc->hw_pp->idx - PINGPONG_0);
 576         }
 577
 578         DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n",
 579                         phys_enc->hw_pp->idx - PINGPONG_0,
 580                         atomic_read(&phys_enc->pending_kickoff_cnt));
 581 }
 582
 583 static int _dpu_encoder_phys_cmd_wait_for_ctl_start(
 584                 struct dpu_encoder_phys *phys_enc)
 585 {
 586         struct dpu_encoder_phys_cmd *cmd_enc =
 587                         to_dpu_encoder_phys_cmd(phys_enc);
 588         struct dpu_encoder_wait_info wait_info;
 589         int ret;
 590
 591         wait_info.wq = &phys_enc->pending_kickoff_wq;
 592         wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt;
 593         wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 594
 595         ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_CTL_START,
 596                         &wait_info);
 597         if (ret == -ETIMEDOUT) {
 598                 DPU_ERROR_CMDENC(cmd_enc, "ctl start interrupt wait failed\n");
 599                 ret = -EINVAL;
 600         } else if (!ret)
 601                 ret = 0;
 602
 603         return ret;
 604 }
 605
 606 static int dpu_encoder_phys_cmd_wait_for_tx_complete(
 607                 struct dpu_encoder_phys *phys_enc)
 608 {
 609         int rc;
 610
 611         rc = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc);
 612         if (rc) {
 613                 DRM_ERROR("failed wait_for_idle: id:%u ret:%d intf:%d\n",
 614                           DRMID(phys_enc->parent), rc,
 615                           phys_enc->intf_idx - INTF_0);
 616         }
 617
 618         return rc;
 619 }
 620
 621 static int dpu_encoder_phys_cmd_wait_for_commit_done(
 622                 struct dpu_encoder_phys *phys_enc)
 623 {
 624         int rc = 0;
 625         struct dpu_encoder_phys_cmd *cmd_enc;
 626
 627         cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
 628
 629         /* only required for master controller */
 630         if (dpu_encoder_phys_cmd_is_master(phys_enc))
 631                 rc = _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc);
 632
 633         /* required for both controllers */
 634         if (!rc && cmd_enc->serialize_wait4pp)
 635                 dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc);
 636
 637         return rc;
 638 }
 639
 640 static int dpu_encoder_phys_cmd_wait_for_vblank(
 641                 struct dpu_encoder_phys *phys_enc)
 642 {
 643         int rc = 0;
 644         struct dpu_encoder_phys_cmd *cmd_enc;
 645         struct dpu_encoder_wait_info wait_info;
 646
 647         cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
 648
 649         /* only required for master controller */
 650         if (!dpu_encoder_phys_cmd_is_master(phys_enc))
 651                 return rc;
 652
 653         wait_info.wq = &cmd_enc->pending_vblank_wq;
 654         wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt;
 655         wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 656
 657         atomic_inc(&cmd_enc->pending_vblank_cnt);
 658
 659         rc = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_RDPTR,
 660                         &wait_info);
 661
 662         return rc;
 663 }
 664
 665 static void dpu_encoder_phys_cmd_handle_post_kickoff(
 666                 struct dpu_encoder_phys *phys_enc)
 667 {
 668         /**
 669          * re-enable external TE, either for the first time after enabling
 670          * or if disabled for Autorefresh
 671          */
 672         _dpu_encoder_phys_cmd_connect_te(phys_enc, true);
 673 }
 674
 675 static void dpu_encoder_phys_cmd_trigger_start(
 676                 struct dpu_encoder_phys *phys_enc)
 677 {
 678         dpu_encoder_helper_trigger_start(phys_enc);
 679 }
 680
 681 static void dpu_encoder_phys_cmd_init_ops(
 682                 struct dpu_encoder_phys_ops *ops)
 683 {
 684         ops->is_master = dpu_encoder_phys_cmd_is_master;
 685         ops->mode_set = dpu_encoder_phys_cmd_mode_set;
 686         ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup;
 687         ops->enable = dpu_encoder_phys_cmd_enable;
 688         ops->disable = dpu_encoder_phys_cmd_disable;
 689         ops->destroy = dpu_encoder_phys_cmd_destroy;
 690         ops->get_hw_resources = dpu_encoder_phys_cmd_get_hw_resources;
 691         ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq;
 692         ops->wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done;
 693         ops->prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff;
 694         ops->wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete;
 695         ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;
 696         ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
 697         ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
 698         ops->irq_control = dpu_encoder_phys_cmd_irq_control;
 699         ops->restore = dpu_encoder_phys_cmd_enable_helper;
 700         ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
 701         ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff;
 702         ops->get_line_count = dpu_encoder_phys_cmd_get_line_count;
 703 }
 704
 705 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 706                 struct dpu_enc_phys_init_params *p)
 707 {
 708         struct dpu_encoder_phys *phys_enc = NULL;
 709         struct dpu_encoder_phys_cmd *cmd_enc = NULL;
 710         struct dpu_encoder_irq *irq;
 711         int i, ret = 0;
 712
 713         DPU_DEBUG("intf %d\n", p->intf_idx - INTF_0);
 714
 715         cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL);
 716         if (!cmd_enc) {
 717                 ret = -ENOMEM;
 718                 DPU_ERROR("failed to allocate\n");
 719                 return ERR_PTR(ret);
 720         }
 721         phys_enc = &cmd_enc->base;
 722         phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
 723         phys_enc->intf_idx = p->intf_idx;
 724
 725         dpu_encoder_phys_cmd_init_ops(&phys_enc->ops);
 726         phys_enc->parent = p->parent;
 727         phys_enc->parent_ops = p->parent_ops;
 728         phys_enc->dpu_kms = p->dpu_kms;
 729         phys_enc->split_role = p->split_role;
 730         phys_enc->intf_mode = INTF_MODE_CMD;
 731         phys_enc->enc_spinlock = p->enc_spinlock;
 732         cmd_enc->stream_sel = 0;
 733         phys_enc->enable_state = DPU_ENC_DISABLED;
 734         for (i = 0; i < INTR_IDX_MAX; i++) {
 735                 irq = &phys_enc->irq[i];
 736                 INIT_LIST_HEAD(&irq->cb.list);
 737                 irq->irq_idx = -EINVAL;
 738                 irq->hw_idx = -EINVAL;
 739                 irq->cb.arg = phys_enc;
 740         }
 741
 742         irq = &phys_enc->irq[INTR_IDX_CTL_START];
 743         irq->name = "ctl_start";
 744         irq->intr_type = DPU_IRQ_TYPE_CTL_START;
 745         irq->intr_idx = INTR_IDX_CTL_START;
 746         irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq;
 747
 748         irq = &phys_enc->irq[INTR_IDX_PINGPONG];
 749         irq->name = "pp_done";
 750         irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP;
 751         irq->intr_idx = INTR_IDX_PINGPONG;
 752         irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq;
 753
 754         irq = &phys_enc->irq[INTR_IDX_RDPTR];
 755         irq->name = "pp_rd_ptr";
 756         irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR;
 757         irq->intr_idx = INTR_IDX_RDPTR;
 758         irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq;
 759
 760         irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
 761         irq->name = "underrun";
 762         irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
 763         irq->intr_idx = INTR_IDX_UNDERRUN;
 764         irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;
 765
 766         atomic_set(&phys_enc->vblank_refcount, 0);
 767         atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 768         atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
 769         atomic_set(&cmd_enc->pending_vblank_cnt, 0);
 770         init_waitqueue_head(&phys_enc->pending_kickoff_wq);
 771         init_waitqueue_head(&cmd_enc->pending_vblank_wq);
 772
 773         DPU_DEBUG_CMDENC(cmd_enc, "created\n");
 774
 775         return phys_enc;
 776 }