WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / msm / disp / dpu1 / dpu_hw_intf.h
blob0ead64d3f63d9a7a8e96e3bb19ca3ea2af9979ae
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
5 #ifndef _DPU_HW_INTF_H
6 #define _DPU_HW_INTF_H
8 #include "dpu_hw_catalog.h"
9 #include "dpu_hw_mdss.h"
10 #include "dpu_hw_util.h"
11 #include "dpu_hw_blk.h"
13 struct dpu_hw_intf;
15 /* intf timing settings */
16 struct intf_timing_params {
17 u32 width; /* active width */
18 u32 height; /* active height */
19 u32 xres; /* Display panel width */
20 u32 yres; /* Display panel height */
22 u32 h_back_porch;
23 u32 h_front_porch;
24 u32 v_back_porch;
25 u32 v_front_porch;
26 u32 hsync_pulse_width;
27 u32 vsync_pulse_width;
28 u32 hsync_polarity;
29 u32 vsync_polarity;
30 u32 border_clr;
31 u32 underflow_clr;
32 u32 hsync_skew;
35 struct intf_prog_fetch {
36 u8 enable;
37 /* vsync counter for the front porch pixel line */
38 u32 fetch_start;
41 struct intf_status {
42 u8 is_en; /* interface timing engine is enabled or not */
43 u32 frame_count; /* frame count since timing engine enabled */
44 u32 line_count; /* current line count including blanking */
47 /**
48 * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions
49 * Assumption is these functions will be called after clocks are enabled
50 * @ setup_timing_gen : programs the timing engine
51 * @ setup_prog_fetch : enables/disables the programmable fetch logic
52 * @ enable_timing: enable/disable timing engine
53 * @ get_status: returns if timing engine is enabled or not
54 * @ get_line_count: reads current vertical line counter
55 * @bind_pingpong_blk: enable/disable the connection with pingpong which will
56 * feed pixels to this interface
58 struct dpu_hw_intf_ops {
59 void (*setup_timing_gen)(struct dpu_hw_intf *intf,
60 const struct intf_timing_params *p,
61 const struct dpu_format *fmt);
63 void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
64 const struct intf_prog_fetch *fetch);
66 void (*enable_timing)(struct dpu_hw_intf *intf,
67 u8 enable);
69 void (*get_status)(struct dpu_hw_intf *intf,
70 struct intf_status *status);
72 u32 (*get_line_count)(struct dpu_hw_intf *intf);
74 void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
75 bool enable,
76 const enum dpu_pingpong pp);
79 struct dpu_hw_intf {
80 struct dpu_hw_blk base;
81 struct dpu_hw_blk_reg_map hw;
83 /* intf */
84 enum dpu_intf idx;
85 const struct dpu_intf_cfg *cap;
86 const struct dpu_mdss_cfg *mdss;
88 /* ops */
89 struct dpu_hw_intf_ops ops;
92 /**
93 * to_dpu_hw_intf - convert base object dpu_hw_base to container
94 * @hw: Pointer to base hardware block
95 * return: Pointer to hardware block container
97 static inline struct dpu_hw_intf *to_dpu_hw_intf(struct dpu_hw_blk *hw)
99 return container_of(hw, struct dpu_hw_intf, base);
103 * dpu_hw_intf_init(): Initializes the intf driver for the passed
104 * interface idx.
105 * @idx: interface index for which driver object is required
106 * @addr: mapped register io address of MDP
107 * @m : pointer to mdss catalog data
109 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
110 void __iomem *addr,
111 const struct dpu_mdss_cfg *m);
114 * dpu_hw_intf_destroy(): Destroys INTF driver context
115 * @intf: Pointer to INTF driver context
117 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf);
119 #endif /*_DPU_HW_INTF_H */