4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13 - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14 - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15 - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16 - /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17 - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18 - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19 - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20 - /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21 - /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
23 Copyright (C) 2013-2020 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
49 enum dsi_traffic_mode
{
50 NON_BURST_SYNCH_PULSE
= 0,
51 NON_BURST_SYNCH_EVENT
= 1,
55 enum dsi_vid_dst_format
{
56 VID_DST_FORMAT_RGB565
= 0,
57 VID_DST_FORMAT_RGB666
= 1,
58 VID_DST_FORMAT_RGB666_LOOSE
= 2,
59 VID_DST_FORMAT_RGB888
= 3,
71 enum dsi_cmd_trigger
{
80 enum dsi_cmd_dst_format
{
81 CMD_DST_FORMAT_RGB111
= 0,
82 CMD_DST_FORMAT_RGB332
= 3,
83 CMD_DST_FORMAT_RGB444
= 4,
84 CMD_DST_FORMAT_RGB565
= 6,
85 CMD_DST_FORMAT_RGB666
= 7,
86 CMD_DST_FORMAT_RGB888
= 8,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
104 #define DSI_IRQ_VIDEO_DONE 0x00010000
105 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
106 #define DSI_IRQ_BTA_DONE 0x00100000
107 #define DSI_IRQ_MASK_BTA_DONE 0x00200000
108 #define DSI_IRQ_ERROR 0x01000000
109 #define DSI_IRQ_MASK_ERROR 0x02000000
110 #define REG_DSI_6G_HW_VERSION 0x00000000
111 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
112 #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28
113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val
)
115 return ((val
) << DSI_6G_HW_VERSION_MAJOR__SHIFT
) & DSI_6G_HW_VERSION_MAJOR__MASK
;
117 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
118 #define DSI_6G_HW_VERSION_MINOR__SHIFT 16
119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val
)
121 return ((val
) << DSI_6G_HW_VERSION_MINOR__SHIFT
) & DSI_6G_HW_VERSION_MINOR__MASK
;
123 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
124 #define DSI_6G_HW_VERSION_STEP__SHIFT 0
125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val
)
127 return ((val
) << DSI_6G_HW_VERSION_STEP__SHIFT
) & DSI_6G_HW_VERSION_STEP__MASK
;
130 #define REG_DSI_CTRL 0x00000000
131 #define DSI_CTRL_ENABLE 0x00000001
132 #define DSI_CTRL_VID_MODE_EN 0x00000002
133 #define DSI_CTRL_CMD_MODE_EN 0x00000004
134 #define DSI_CTRL_LANE0 0x00000010
135 #define DSI_CTRL_LANE1 0x00000020
136 #define DSI_CTRL_LANE2 0x00000040
137 #define DSI_CTRL_LANE3 0x00000080
138 #define DSI_CTRL_CLK_EN 0x00000100
139 #define DSI_CTRL_ECC_CHECK 0x00100000
140 #define DSI_CTRL_CRC_CHECK 0x01000000
142 #define REG_DSI_STATUS0 0x00000004
143 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
144 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
145 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
146 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
147 #define DSI_STATUS0_DSI_BUSY 0x00000010
148 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
150 #define REG_DSI_FIFO_STATUS 0x00000008
151 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
152 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
153 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
154 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
155 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
156 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
157 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
158 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
159 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
160 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
161 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
162 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
163 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
164 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
165 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
166 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
167 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
168 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
169 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
170 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
171 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
172 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
173 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
174 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
175 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
177 #define REG_DSI_VID_CFG0 0x0000000c
178 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
179 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
180 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val
)
182 return ((val
) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT
) & DSI_VID_CFG0_VIRT_CHANNEL__MASK
;
184 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
185 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
186 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val
)
188 return ((val
) << DSI_VID_CFG0_DST_FORMAT__SHIFT
) & DSI_VID_CFG0_DST_FORMAT__MASK
;
190 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
191 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
192 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val
)
194 return ((val
) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT
) & DSI_VID_CFG0_TRAFFIC_MODE__MASK
;
196 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
197 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
198 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
199 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
200 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
201 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
203 #define REG_DSI_VID_CFG1 0x0000001c
204 #define DSI_VID_CFG1_R_SEL 0x00000001
205 #define DSI_VID_CFG1_G_SEL 0x00000010
206 #define DSI_VID_CFG1_B_SEL 0x00000100
207 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
208 #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12
209 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val
)
211 return ((val
) << DSI_VID_CFG1_RGB_SWAP__SHIFT
) & DSI_VID_CFG1_RGB_SWAP__MASK
;
214 #define REG_DSI_ACTIVE_H 0x00000020
215 #define DSI_ACTIVE_H_START__MASK 0x00000fff
216 #define DSI_ACTIVE_H_START__SHIFT 0
217 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val
)
219 return ((val
) << DSI_ACTIVE_H_START__SHIFT
) & DSI_ACTIVE_H_START__MASK
;
221 #define DSI_ACTIVE_H_END__MASK 0x0fff0000
222 #define DSI_ACTIVE_H_END__SHIFT 16
223 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val
)
225 return ((val
) << DSI_ACTIVE_H_END__SHIFT
) & DSI_ACTIVE_H_END__MASK
;
228 #define REG_DSI_ACTIVE_V 0x00000024
229 #define DSI_ACTIVE_V_START__MASK 0x00000fff
230 #define DSI_ACTIVE_V_START__SHIFT 0
231 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val
)
233 return ((val
) << DSI_ACTIVE_V_START__SHIFT
) & DSI_ACTIVE_V_START__MASK
;
235 #define DSI_ACTIVE_V_END__MASK 0x0fff0000
236 #define DSI_ACTIVE_V_END__SHIFT 16
237 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val
)
239 return ((val
) << DSI_ACTIVE_V_END__SHIFT
) & DSI_ACTIVE_V_END__MASK
;
242 #define REG_DSI_TOTAL 0x00000028
243 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
244 #define DSI_TOTAL_H_TOTAL__SHIFT 0
245 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val
)
247 return ((val
) << DSI_TOTAL_H_TOTAL__SHIFT
) & DSI_TOTAL_H_TOTAL__MASK
;
249 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
250 #define DSI_TOTAL_V_TOTAL__SHIFT 16
251 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val
)
253 return ((val
) << DSI_TOTAL_V_TOTAL__SHIFT
) & DSI_TOTAL_V_TOTAL__MASK
;
256 #define REG_DSI_ACTIVE_HSYNC 0x0000002c
257 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
258 #define DSI_ACTIVE_HSYNC_START__SHIFT 0
259 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val
)
261 return ((val
) << DSI_ACTIVE_HSYNC_START__SHIFT
) & DSI_ACTIVE_HSYNC_START__MASK
;
263 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
264 #define DSI_ACTIVE_HSYNC_END__SHIFT 16
265 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val
)
267 return ((val
) << DSI_ACTIVE_HSYNC_END__SHIFT
) & DSI_ACTIVE_HSYNC_END__MASK
;
270 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
271 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
272 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
273 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val
)
275 return ((val
) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT
) & DSI_ACTIVE_VSYNC_HPOS_START__MASK
;
277 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
278 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16
279 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val
)
281 return ((val
) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT
) & DSI_ACTIVE_VSYNC_HPOS_END__MASK
;
284 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
285 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
286 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
287 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val
)
289 return ((val
) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT
) & DSI_ACTIVE_VSYNC_VPOS_START__MASK
;
291 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
292 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16
293 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val
)
295 return ((val
) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT
) & DSI_ACTIVE_VSYNC_VPOS_END__MASK
;
298 #define REG_DSI_CMD_DMA_CTRL 0x00000038
299 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
300 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
301 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
303 #define REG_DSI_CMD_CFG0 0x0000003c
304 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
305 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
306 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val
)
308 return ((val
) << DSI_CMD_CFG0_DST_FORMAT__SHIFT
) & DSI_CMD_CFG0_DST_FORMAT__MASK
;
310 #define DSI_CMD_CFG0_R_SEL 0x00000010
311 #define DSI_CMD_CFG0_G_SEL 0x00000100
312 #define DSI_CMD_CFG0_B_SEL 0x00001000
313 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
314 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20
315 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val
)
317 return ((val
) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT
) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK
;
319 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
320 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16
321 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val
)
323 return ((val
) << DSI_CMD_CFG0_RGB_SWAP__SHIFT
) & DSI_CMD_CFG0_RGB_SWAP__MASK
;
326 #define REG_DSI_CMD_CFG1 0x00000040
327 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
328 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
329 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val
)
331 return ((val
) << DSI_CMD_CFG1_WR_MEM_START__SHIFT
) & DSI_CMD_CFG1_WR_MEM_START__MASK
;
333 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
334 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8
335 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val
)
337 return ((val
) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT
) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK
;
339 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
341 #define REG_DSI_DMA_BASE 0x00000044
343 #define REG_DSI_DMA_LEN 0x00000048
345 #define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
346 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
347 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
348 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val
)
350 return ((val
) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT
) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK
;
352 #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
353 #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8
354 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val
)
356 return ((val
) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT
) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK
;
358 #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
359 #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16
360 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val
)
362 return ((val
) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT
) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK
;
365 #define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
366 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
367 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
368 static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val
)
370 return ((val
) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT
) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK
;
372 #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
373 #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16
374 static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val
)
376 return ((val
) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT
) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK
;
379 #define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
380 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
381 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
382 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val
)
384 return ((val
) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT
) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK
;
386 #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
387 #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8
388 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val
)
390 return ((val
) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT
) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK
;
392 #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
393 #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16
394 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val
)
396 return ((val
) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT
) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK
;
399 #define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
400 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
401 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
402 static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val
)
404 return ((val
) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT
) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK
;
406 #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
407 #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16
408 static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val
)
410 return ((val
) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT
) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK
;
413 #define REG_DSI_ACK_ERR_STATUS 0x00000064
415 static inline uint32_t REG_DSI_RDBK(uint32_t i0
) { return 0x00000068 + 0x4*i0
; }
417 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0
) { return 0x00000068 + 0x4*i0
; }
419 #define REG_DSI_TRIG_CTRL 0x00000080
420 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
421 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
422 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val
)
424 return ((val
) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT
) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK
;
426 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
427 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4
428 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val
)
430 return ((val
) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT
) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK
;
432 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
433 #define DSI_TRIG_CTRL_STREAM__SHIFT 8
434 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val
)
436 return ((val
) << DSI_TRIG_CTRL_STREAM__SHIFT
) & DSI_TRIG_CTRL_STREAM__MASK
;
438 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
439 #define DSI_TRIG_CTRL_TE 0x80000000
441 #define REG_DSI_TRIG_DMA 0x0000008c
443 #define REG_DSI_DLN0_PHY_ERR 0x000000b0
444 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
445 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
446 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
447 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
448 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
450 #define REG_DSI_LP_TIMER_CTRL 0x000000b4
451 #define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
452 #define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
453 static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val
)
455 return ((val
) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT
) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK
;
457 #define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
458 #define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16
459 static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val
)
461 return ((val
) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT
) & DSI_LP_TIMER_CTRL_BTA_TO__MASK
;
464 #define REG_DSI_HS_TIMER_CTRL 0x000000b8
465 #define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
466 #define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
467 static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val
)
469 return ((val
) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT
) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK
;
471 #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
472 #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16
473 static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val
)
475 return ((val
) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT
) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK
;
477 #define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
479 #define REG_DSI_TIMEOUT_STATUS 0x000000bc
481 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
482 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
483 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
484 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val
)
486 return ((val
) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT
) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK
;
488 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
489 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8
490 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val
)
492 return ((val
) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT
) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK
;
495 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8
496 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
497 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
499 #define REG_DSI_LANE_STATUS 0x000000a4
500 #define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
501 #define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
502 #define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
503 #define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
504 #define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
505 #define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
506 #define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
507 #define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
508 #define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
509 #define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
510 #define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
512 #define REG_DSI_LANE_CTRL 0x000000a8
513 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
515 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac
516 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
517 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
518 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val
)
520 return ((val
) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT
) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK
;
523 #define REG_DSI_ERR_INT_MASK0 0x00000108
525 #define REG_DSI_INTR_CTRL 0x0000010c
527 #define REG_DSI_RESET 0x00000114
529 #define REG_DSI_CLK_CTRL 0x00000118
530 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
531 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
532 #define DSI_CLK_CTRL_PCLK_ON 0x00000004
533 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008
534 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
535 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
536 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
538 #define REG_DSI_CLK_STATUS 0x0000011c
539 #define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
540 #define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
541 #define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
542 #define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
543 #define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
544 #define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
545 #define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
546 #define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
547 #define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
548 #define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
549 #define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
550 #define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
551 #define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
552 #define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
553 #define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
554 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
556 #define REG_DSI_PHY_RESET 0x00000128
557 #define DSI_PHY_RESET_RESET 0x00000001
559 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
560 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
562 #define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
563 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
564 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
565 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val
)
567 return ((val
) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT
) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK
;
569 #define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
570 #define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
571 #define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
572 #define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
573 #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
574 #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8
575 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val
)
577 return ((val
) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT
) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK
;
579 #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
580 #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12
581 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val
)
583 return ((val
) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT
) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK
;
585 #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
587 #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
588 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
589 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
590 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val
)
592 return ((val
) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT
) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK
;
594 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
595 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8
596 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val
)
598 return ((val
) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT
) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK
;
600 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
601 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16
602 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val
)
604 return ((val
) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT
) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK
;
607 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0
608 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
609 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
610 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val
)
612 return ((val
) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT
) & DSI_RDBK_DATA_CTRL_COUNT__MASK
;
614 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001
616 #define REG_DSI_VERSION 0x000001f0
617 #define DSI_VERSION_MAJOR__MASK 0xff000000
618 #define DSI_VERSION_MAJOR__SHIFT 24
619 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val
)
621 return ((val
) << DSI_VERSION_MAJOR__SHIFT
) & DSI_VERSION_MAJOR__MASK
;
624 #define REG_DSI_PHY_PLL_CTRL_0 0x00000200
625 #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
627 #define REG_DSI_PHY_PLL_CTRL_1 0x00000204
629 #define REG_DSI_PHY_PLL_CTRL_2 0x00000208
631 #define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
633 #define REG_DSI_PHY_PLL_CTRL_4 0x00000210
635 #define REG_DSI_PHY_PLL_CTRL_5 0x00000214
637 #define REG_DSI_PHY_PLL_CTRL_6 0x00000218
639 #define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
641 #define REG_DSI_PHY_PLL_CTRL_8 0x00000220
643 #define REG_DSI_PHY_PLL_CTRL_9 0x00000224
645 #define REG_DSI_PHY_PLL_CTRL_10 0x00000228
647 #define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
649 #define REG_DSI_PHY_PLL_CTRL_12 0x00000230
651 #define REG_DSI_PHY_PLL_CTRL_13 0x00000234
653 #define REG_DSI_PHY_PLL_CTRL_14 0x00000238
655 #define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
657 #define REG_DSI_PHY_PLL_CTRL_16 0x00000240
659 #define REG_DSI_PHY_PLL_CTRL_17 0x00000244
661 #define REG_DSI_PHY_PLL_CTRL_18 0x00000248
663 #define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
665 #define REG_DSI_PHY_PLL_CTRL_20 0x00000250
667 #define REG_DSI_PHY_PLL_STATUS 0x00000280
668 #define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
670 #define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
672 #define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
674 #define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
676 #define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
678 #define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
680 #define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
682 #define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
684 #define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
686 #define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
688 #define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
690 #define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
692 #define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
694 #define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
696 #define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
698 #define REG_DSI_8x60_PHY_CTRL_0 0x00000290
700 #define REG_DSI_8x60_PHY_CTRL_1 0x00000294
702 #define REG_DSI_8x60_PHY_CTRL_2 0x00000298
704 #define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
706 #define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
708 #define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
710 #define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
712 #define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
714 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
716 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
718 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
720 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
722 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
724 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
726 #define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
728 #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
729 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
731 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0
) { return 0x00000000 + 0x40*i0
; }
733 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0
) { return 0x00000000 + 0x40*i0
; }
735 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0
) { return 0x00000004 + 0x40*i0
; }
737 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0
) { return 0x00000008 + 0x40*i0
; }
739 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0
) { return 0x0000000c + 0x40*i0
; }
741 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0
) { return 0x00000014 + 0x40*i0
; }
743 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0
) { return 0x00000018 + 0x40*i0
; }
745 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
747 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
749 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
751 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
753 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
755 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
757 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
758 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
759 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
760 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val
)
762 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK
;
765 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
766 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
767 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
768 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val
)
770 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK
;
773 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
774 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
775 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
776 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val
)
778 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK
;
781 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
783 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
784 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
785 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
786 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val
)
788 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK
;
791 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
792 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
793 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
794 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val
)
796 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK
;
799 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
800 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
801 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
802 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val
)
804 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK
;
807 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
808 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
809 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
810 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val
)
812 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK
;
815 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
816 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
817 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
818 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val
)
820 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK
;
823 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
824 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
825 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
826 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val
)
828 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK
;
830 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
831 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
832 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val
)
834 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK
;
837 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
838 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
839 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
840 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val
)
842 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK
;
845 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
846 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
847 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
848 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val
)
850 return ((val
) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT
) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK
;
853 #define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
855 #define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
857 #define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
859 #define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
861 #define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
863 #define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
865 #define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
867 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
869 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
871 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
873 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
875 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
877 #define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
879 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
881 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
883 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
885 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
887 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
889 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
891 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
893 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
895 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
897 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
899 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
901 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
903 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
905 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
907 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
909 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
911 #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
912 #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
914 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
915 #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
917 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
919 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
921 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
923 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
925 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
927 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
929 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
931 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
933 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
935 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
937 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
939 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
941 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
943 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
945 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
947 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
949 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
951 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
953 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
955 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
957 #define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
958 #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
960 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0
) { return 0x00000000 + 0x40*i0
; }
962 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0
) { return 0x00000000 + 0x40*i0
; }
964 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0
) { return 0x00000004 + 0x40*i0
; }
966 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0
) { return 0x00000008 + 0x40*i0
; }
968 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0
) { return 0x0000000c + 0x40*i0
; }
970 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0
) { return 0x00000010 + 0x40*i0
; }
972 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0
) { return 0x00000014 + 0x40*i0
; }
974 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0
) { return 0x00000018 + 0x40*i0
; }
976 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0
) { return 0x0000001c + 0x40*i0
; }
978 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0
) { return 0x00000020 + 0x40*i0
; }
980 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
982 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
984 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
986 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
988 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
990 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
992 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
994 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
996 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
998 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
999 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1000 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1001 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val
)
1003 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK
;
1006 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
1007 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1008 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1009 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val
)
1011 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK
;
1014 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
1015 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1016 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1017 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val
)
1019 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK
;
1022 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
1023 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1025 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
1026 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1027 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1028 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val
)
1030 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK
;
1033 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
1034 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1035 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1036 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val
)
1038 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK
;
1041 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
1042 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1043 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1044 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val
)
1046 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK
;
1049 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
1050 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1051 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1052 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val
)
1054 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK
;
1057 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
1058 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1059 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1060 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val
)
1062 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK
;
1065 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
1066 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1067 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1068 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val
)
1070 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK
;
1072 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1073 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1074 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val
)
1076 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK
;
1079 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
1080 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1081 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1082 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val
)
1084 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK
;
1087 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
1088 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1089 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1090 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val
)
1092 return ((val
) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT
) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK
;
1095 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170
1097 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174
1099 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178
1101 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
1103 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180
1105 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
1107 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
1109 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
1111 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
1113 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
1115 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
1117 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
1119 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
1121 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
1122 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1124 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
1126 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
1128 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
1130 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
1132 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
1134 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
1136 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
1138 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1140 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
1141 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
1143 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
1145 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
1147 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
1149 #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
1150 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
1152 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
1154 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
1156 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
1158 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
1159 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
1160 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
1161 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
1162 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
1164 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
1166 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
1168 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
1170 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
1172 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
1174 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
1175 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
1176 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
1177 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val
)
1179 return ((val
) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT
) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK
;
1181 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
1183 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
1184 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
1185 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
1186 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val
)
1188 return ((val
) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT
) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK
;
1190 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
1191 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
1192 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val
)
1194 return ((val
) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT
) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK
;
1197 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
1198 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
1199 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
1200 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val
)
1202 return ((val
) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT
) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK
;
1205 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
1206 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
1207 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
1208 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val
)
1210 return ((val
) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT
) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK
;
1213 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
1215 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
1217 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
1219 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
1221 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
1223 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
1225 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
1227 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
1229 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
1230 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
1232 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
1234 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
1236 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
1238 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
1240 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
1242 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
1244 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
1246 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
1248 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
1250 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
1252 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
1254 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
1256 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
1258 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
1260 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
1262 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
1264 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
1266 #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
1268 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
1270 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
1272 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
1274 #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
1275 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
1277 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
1279 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
1281 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
1283 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
1285 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
1287 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0
) { return 0x00000000 + 0x40*i0
; }
1289 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0
) { return 0x00000000 + 0x40*i0
; }
1291 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0
) { return 0x00000004 + 0x40*i0
; }
1293 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0
) { return 0x00000008 + 0x40*i0
; }
1295 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0
) { return 0x0000000c + 0x40*i0
; }
1297 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0
) { return 0x00000010 + 0x40*i0
; }
1299 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0
) { return 0x00000014 + 0x40*i0
; }
1301 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0
) { return 0x00000018 + 0x40*i0
; }
1303 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0
) { return 0x0000001c + 0x40*i0
; }
1305 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0
) { return 0x00000020 + 0x40*i0
; }
1307 #define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
1309 #define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
1311 #define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
1313 #define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
1315 #define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
1317 #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
1319 #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
1321 #define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
1323 #define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
1325 #define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
1326 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1327 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1328 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val
)
1330 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK
;
1333 #define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
1334 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1335 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1336 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val
)
1338 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK
;
1341 #define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
1342 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1343 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1344 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val
)
1346 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK
;
1349 #define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
1350 #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1352 #define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
1353 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1354 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1355 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val
)
1357 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK
;
1360 #define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
1361 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1362 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1363 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val
)
1365 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK
;
1368 #define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
1369 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1370 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1371 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val
)
1373 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK
;
1376 #define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
1377 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1378 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1379 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val
)
1381 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK
;
1384 #define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
1385 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1386 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1387 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val
)
1389 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK
;
1392 #define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
1393 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1394 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1395 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val
)
1397 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK
;
1399 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1400 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1401 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val
)
1403 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK
;
1406 #define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
1407 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1408 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1409 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val
)
1411 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK
;
1414 #define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
1415 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1416 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1417 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val
)
1419 return ((val
) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT
) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK
;
1422 #define REG_DSI_20nm_PHY_CTRL_0 0x00000170
1424 #define REG_DSI_20nm_PHY_CTRL_1 0x00000174
1426 #define REG_DSI_20nm_PHY_CTRL_2 0x00000178
1428 #define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
1430 #define REG_DSI_20nm_PHY_CTRL_4 0x00000180
1432 #define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
1434 #define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
1436 #define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
1438 #define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
1440 #define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
1442 #define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
1444 #define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
1446 #define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
1448 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
1449 #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1451 #define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
1453 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
1455 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
1457 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
1459 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
1461 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
1463 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
1465 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1467 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
1469 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
1471 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
1473 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
1475 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
1476 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
1477 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
1478 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val
)
1480 return ((val
) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT
) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK
;
1482 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
1483 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
1484 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val
)
1486 return ((val
) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT
) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK
;
1489 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
1490 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
1492 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
1493 #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
1495 #define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
1497 #define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
1499 #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
1501 #define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
1503 #define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
1505 #define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
1507 #define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
1509 #define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
1511 #define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
1513 #define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
1515 #define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
1517 #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
1518 #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
1520 #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
1521 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
1522 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
1523 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val
)
1525 return ((val
) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT
) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK
;
1528 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0
) { return 0x00000000 + 0x80*i0
; }
1530 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0
) { return 0x00000000 + 0x80*i0
; }
1531 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
1532 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
1533 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val
)
1535 return ((val
) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT
) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK
;
1538 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0
) { return 0x00000004 + 0x80*i0
; }
1539 #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
1541 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0
) { return 0x00000008 + 0x80*i0
; }
1543 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0
) { return 0x0000000c + 0x80*i0
; }
1545 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0
) { return 0x00000010 + 0x80*i0
; }
1547 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0
) { return 0x00000014 + 0x80*i0
; }
1549 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0
) { return 0x00000018 + 0x80*i0
; }
1550 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1551 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1552 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val
)
1554 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK
;
1557 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0
) { return 0x0000001c + 0x80*i0
; }
1558 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1559 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1560 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val
)
1562 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK
;
1565 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0
) { return 0x00000020 + 0x80*i0
; }
1566 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1567 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1568 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val
)
1570 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK
;
1573 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0
) { return 0x00000024 + 0x80*i0
; }
1574 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1575 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1576 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val
)
1578 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK
;
1581 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0
) { return 0x00000028 + 0x80*i0
; }
1582 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1583 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
1584 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val
)
1586 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK
;
1589 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0
) { return 0x0000002c + 0x80*i0
; }
1590 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1591 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
1592 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val
)
1594 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK
;
1596 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1597 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
1598 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val
)
1600 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK
;
1603 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0
) { return 0x00000030 + 0x80*i0
; }
1604 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1605 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
1606 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val
)
1608 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK
;
1611 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0
) { return 0x00000034 + 0x80*i0
; }
1612 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1613 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1614 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val
)
1616 return ((val
) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT
) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK
;
1619 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0
) { return 0x00000038 + 0x80*i0
; }
1621 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0
) { return 0x0000003c + 0x80*i0
; }
1623 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0
) { return 0x00000064 + 0x80*i0
; }
1625 #define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
1627 #define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
1629 #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
1631 #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
1633 #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
1635 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
1637 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
1639 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
1641 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
1643 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
1645 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
1647 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
1649 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
1651 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
1653 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
1655 #define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
1657 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
1659 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
1661 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
1663 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
1665 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
1667 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
1669 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
1671 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
1673 #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
1675 #define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
1677 #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
1679 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
1681 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
1683 #define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
1685 #define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
1687 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
1689 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
1691 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
1693 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
1695 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
1697 #define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
1699 #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
1701 #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
1703 #define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
1705 #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
1707 #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
1709 #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
1711 #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
1713 #define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
1715 #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
1717 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
1719 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
1721 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
1723 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
1725 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
1727 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
1729 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
1731 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
1733 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
1735 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
1737 #define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
1739 #define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
1741 #define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
1743 #define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
1745 #define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
1747 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
1749 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
1751 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
1753 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
1755 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
1757 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
1759 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
1761 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
1763 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
1765 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
1767 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
1769 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
1771 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
1773 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
1775 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
1777 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
1779 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
1781 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
1783 #define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
1785 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
1787 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
1789 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0
) { return 0x00000000 + 0x80*i0
; }
1791 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0
) { return 0x00000000 + 0x80*i0
; }
1793 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0
) { return 0x00000004 + 0x80*i0
; }
1795 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0
) { return 0x00000008 + 0x80*i0
; }
1797 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0
) { return 0x0000000c + 0x80*i0
; }
1799 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0
) { return 0x00000010 + 0x80*i0
; }
1801 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0
) { return 0x00000014 + 0x80*i0
; }
1803 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0
) { return 0x00000018 + 0x80*i0
; }
1805 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0
) { return 0x0000001c + 0x80*i0
; }
1807 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0
) { return 0x00000020 + 0x80*i0
; }
1809 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0
) { return 0x00000024 + 0x80*i0
; }
1811 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0
) { return 0x00000028 + 0x80*i0
; }
1813 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0
) { return 0x0000002c + 0x80*i0
; }
1815 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
1817 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
1819 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
1821 #define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
1823 #define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
1825 #define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
1827 #define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
1829 #define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
1831 #define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
1833 #define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
1835 #define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
1837 #define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
1839 #define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
1841 #define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
1843 #define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
1845 #define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
1847 #define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
1849 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
1851 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
1853 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
1855 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
1857 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
1859 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
1861 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
1863 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
1865 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
1867 #define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
1869 #define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
1871 #define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
1873 #define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
1875 #define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
1877 #define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
1879 #define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
1881 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
1883 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
1885 #define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
1887 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
1889 #define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
1891 #define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
1893 #define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
1895 #define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
1897 #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
1899 #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
1901 #define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
1903 #define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
1905 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
1907 #define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
1909 #define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
1911 #define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
1913 #define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
1915 #define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
1917 #define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
1919 #define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
1921 #define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
1923 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
1925 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
1927 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
1929 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
1931 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
1933 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
1935 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
1937 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
1939 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
1941 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
1943 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
1945 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
1947 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
1949 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
1951 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
1953 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
1955 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
1957 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
1959 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
1961 #define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
1963 #define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
1965 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
1967 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
1969 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
1971 #define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
1973 #define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
1975 #define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
1977 #define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
1979 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
1981 #define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
1983 #define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
1985 #define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
1987 #define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
1989 #define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
1991 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0
) { return 0x00000000 + 0x80*i0
; }
1993 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0
) { return 0x00000000 + 0x80*i0
; }
1995 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0
) { return 0x00000004 + 0x80*i0
; }
1997 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0
) { return 0x00000008 + 0x80*i0
; }
1999 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0
) { return 0x0000000c + 0x80*i0
; }
2001 static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0
) { return 0x00000010 + 0x80*i0
; }
2003 static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0
) { return 0x00000014 + 0x80*i0
; }
2005 static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0
) { return 0x00000018 + 0x80*i0
; }
2007 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
2009 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
2011 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
2013 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
2015 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
2017 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
2019 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
2021 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
2023 #define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
2025 #define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
2027 #define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
2029 #define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
2031 #define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
2033 #define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
2035 #define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
2037 #define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
2039 #define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
2041 #define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
2043 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
2045 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
2047 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
2049 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
2051 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
2053 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
2055 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
2057 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
2059 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
2061 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
2063 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
2065 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
2067 #define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
2069 #define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
2071 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
2073 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
2075 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
2077 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
2079 #define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
2081 #define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
2083 #define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
2085 #define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
2087 #define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
2089 #define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
2091 #define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
2093 #define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
2095 #define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
2097 #define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
2099 #define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
2101 #define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
2103 #define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
2105 #define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
2107 #define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
2109 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
2111 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
2113 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
2115 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
2117 #define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
2119 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
2121 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
2123 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
2125 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
2127 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
2129 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
2131 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
2133 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
2135 #define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
2137 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
2139 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
2141 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
2143 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
2145 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
2147 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
2149 #define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
2151 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
2153 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
2155 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
2157 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
2159 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
2161 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
2163 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
2165 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
2167 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
2169 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
2171 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
2173 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
2175 #define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
2177 #define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
2179 #define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
2181 #define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
2183 #define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
2185 #define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
2187 #define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
2189 #define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
2191 #define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
2193 #define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
2195 #define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
2197 #define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
2199 #define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
2201 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
2203 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
2205 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
2207 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
2209 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
2211 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
2213 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
2215 #define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
2217 #define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
2219 #define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
2221 #define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
2223 #define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
2225 #define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
2227 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
2229 #define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
2231 #define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
2233 #define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
2235 #define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
2237 #define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
2239 #define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
2241 #define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
2243 #define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
2245 #define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
2247 #define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
2249 #define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
2251 #define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
2253 #define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
2255 #define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
2257 #define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
2259 #define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
2261 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
2263 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
2265 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
2267 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
2269 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
2271 #define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
2273 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
2275 #define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
2277 #define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
2279 #define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
2281 #define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
2283 #define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
2285 #define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
2287 #define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
2289 #define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
2291 #define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
2293 #define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
2295 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
2297 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
2299 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
2301 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
2303 #define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
2305 #define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
2307 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
2309 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
2311 #define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
2313 #endif /* DSI_XML */