drivers/gpu/drm/msm/msm_gpu.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6
   7 #ifndef __MSM_GPU_H__
   8 #define __MSM_GPU_H__
   9
  10 #include <linux/adreno-smmu-priv.h>
  11 #include <linux/clk.h>
  12 #include <linux/interconnect.h>
  13 #include <linux/pm_opp.h>
  14 #include <linux/regulator/consumer.h>
  15
  16 #include "msm_drv.h"
  17 #include "msm_fence.h"
  18 #include "msm_ringbuffer.h"
  19 #include "msm_gem.h"
  20
  21 struct msm_gem_submit;
  22 struct msm_gpu_perfcntr;
  23 struct msm_gpu_state;
  24
  25 struct msm_gpu_config {
  26         const char *ioname;
  27         unsigned int nr_rings;
  28 };
  29
  30 /* So far, with hardware that I've seen to date, we can have:
  31  *  + zero, one, or two z180 2d cores
  32  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
  33  *    for the CP seems to implement some different PM4 packet types
  34  *    but the basics of cmdstream submission are the same)
  35  *
  36  * Which means that the eventual complete "class" hierarchy, once
  37  * support for all past and present hw is in place, becomes:
  38  *  + msm_gpu
  39  *    + adreno_gpu
  40  *      + a3xx_gpu
  41  *      + a2xx_gpu
  42  *    + z180_gpu
  43  */
  44 struct msm_gpu_funcs {
  45         int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
  46         int (*hw_init)(struct msm_gpu *gpu);
  47         int (*pm_suspend)(struct msm_gpu *gpu);
  48         int (*pm_resume)(struct msm_gpu *gpu);
  49         void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
  50         void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
  51         irqreturn_t (*irq)(struct msm_gpu *irq);
  52         struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
  53         void (*recover)(struct msm_gpu *gpu);
  54         void (*destroy)(struct msm_gpu *gpu);
  55 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
  56         /* show GPU status in debugfs: */
  57         void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
  58                         struct drm_printer *p);
  59         /* for generation specific debugfs: */
  60         void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
  61 #endif
  62         unsigned long (*gpu_busy)(struct msm_gpu *gpu);
  63         struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
  64         int (*gpu_state_put)(struct msm_gpu_state *state);
  65         unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
  66         void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp);
  67         struct msm_gem_address_space *(*create_address_space)
  68                 (struct msm_gpu *gpu, struct platform_device *pdev);
  69         struct msm_gem_address_space *(*create_private_address_space)
  70                 (struct msm_gpu *gpu);
  71         uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
  72 };
  73
  74 struct msm_gpu {
  75         const char *name;
  76         struct drm_device *dev;
  77         struct platform_device *pdev;
  78         const struct msm_gpu_funcs *funcs;
  79
  80         struct adreno_smmu_priv adreno_smmu;
  81
  82         /* performance counters (hw & sw): */
  83         spinlock_t perf_lock;
  84         bool perfcntr_active;
  85         struct {
  86                 bool active;
  87                 ktime_t time;
  88         } last_sample;
  89         uint32_t totaltime, activetime;    /* sw counters */
  90         uint32_t last_cntrs[5];            /* hw counters */
  91         const struct msm_gpu_perfcntr *perfcntrs;
  92         uint32_t num_perfcntrs;
  93
  94         struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
  95         int nr_rings;
  96
  97         /*
  98          * List of GEM active objects on this gpu.  Protected by
  99          * msm_drm_private::mm_lock
 100          */
 101         struct list_head active_list;
 102
 103         /* does gpu need hw_init? */
 104         bool needs_hw_init;
 105
 106         /* number of GPU hangs (for all contexts) */
 107         int global_faults;
 108
 109         void __iomem *mmio;
 110         int irq;
 111
 112         struct msm_gem_address_space *aspace;
 113
 114         /* Power Control: */
 115         struct regulator *gpu_reg, *gpu_cx;
 116         struct clk_bulk_data *grp_clks;
 117         int nr_clocks;
 118         struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
 119         uint32_t fast_rate;
 120
 121         /* The gfx-mem interconnect path that's used by all GPU types. */
 122         struct icc_path *icc_path;
 123
 124         /*
 125          * Second interconnect path for some A3xx and all A4xx GPUs to the
 126          * On Chip MEMory (OCMEM).
 127          */
 128         struct icc_path *ocmem_icc_path;
 129
 130         /* Hang and Inactivity Detection:
 131          */
 132 #define DRM_MSM_INACTIVE_PERIOD   66 /* in ms (roughly four frames) */
 133
 134 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
 135 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
 136         struct timer_list hangcheck_timer;
 137
 138         /* work for handling GPU recovery: */
 139         struct kthread_work recover_work;
 140
 141         /* work for handling active-list retiring: */
 142         struct kthread_work retire_work;
 143
 144         /* worker for retire/recover: */
 145         struct kthread_worker *worker;
 146
 147         struct drm_gem_object *memptrs_bo;
 148
 149         struct {
 150                 struct devfreq *devfreq;
 151                 u64 busy_cycles;
 152                 ktime_t time;
 153         } devfreq;
 154
 155         struct msm_gpu_state *crashstate;
 156         /* True if the hardware supports expanded apriv (a650 and newer) */
 157         bool hw_apriv;
 158
 159         struct thermal_cooling_device *cooling;
 160 };
 161
 162 static inline struct msm_gpu *dev_to_gpu(struct device *dev)
 163 {
 164         struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
 165         return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
 166 }
 167
 168 /* It turns out that all targets use the same ringbuffer size */
 169 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
 170 #define MSM_GPU_RINGBUFFER_BLKSIZE 32
 171
 172 #define MSM_GPU_RB_CNTL_DEFAULT \
 173                 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
 174                 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
 175
 176 static inline bool msm_gpu_active(struct msm_gpu *gpu)
 177 {
 178         int i;
 179
 180         for (i = 0; i < gpu->nr_rings; i++) {
 181                 struct msm_ringbuffer *ring = gpu->rb[i];
 182
 183                 if (ring->seqno > ring->memptrs->fence)
 184                         return true;
 185         }
 186
 187         return false;
 188 }
 189
 190 /* Perf-Counters:
 191  * The select_reg and select_val are just there for the benefit of the child
 192  * class that actually enables the perf counter..  but msm_gpu base class
 193  * will handle sampling/displaying the counters.
 194  */
 195
 196 struct msm_gpu_perfcntr {
 197         uint32_t select_reg;
 198         uint32_t sample_reg;
 199         uint32_t select_val;
 200         const char *name;
 201 };
 202
 203 struct msm_gpu_submitqueue {
 204         int id;
 205         u32 flags;
 206         u32 prio;
 207         int faults;
 208         struct msm_file_private *ctx;
 209         struct list_head node;
 210         struct kref ref;
 211 };
 212
 213 struct msm_gpu_state_bo {
 214         u64 iova;
 215         size_t size;
 216         void *data;
 217         bool encoded;
 218 };
 219
 220 struct msm_gpu_state {
 221         struct kref ref;
 222         struct timespec64 time;
 223
 224         struct {
 225                 u64 iova;
 226                 u32 fence;
 227                 u32 seqno;
 228                 u32 rptr;
 229                 u32 wptr;
 230                 void *data;
 231                 int data_size;
 232                 bool encoded;
 233         } ring[MSM_GPU_MAX_RINGS];
 234
 235         int nr_registers;
 236         u32 *registers;
 237
 238         u32 rbbm_status;
 239
 240         char *comm;
 241         char *cmd;
 242
 243         int nr_bos;
 244         struct msm_gpu_state_bo *bos;
 245 };
 246
 247 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
 248 {
 249         msm_writel(data, gpu->mmio + (reg << 2));
 250 }
 251
 252 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
 253 {
 254         return msm_readl(gpu->mmio + (reg << 2));
 255 }
 256
 257 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
 258 {
 259         msm_rmw(gpu->mmio + (reg << 2), mask, or);
 260 }
 261
 262 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
 263 {
 264         u64 val;
 265
 266         /*
 267          * Why not a readq here? Two reasons: 1) many of the LO registers are
 268          * not quad word aligned and 2) the GPU hardware designers have a bit
 269          * of a history of putting registers where they fit, especially in
 270          * spins. The longer a GPU family goes the higher the chance that
 271          * we'll get burned.  We could do a series of validity checks if we
 272          * wanted to, but really is a readq() that much better? Nah.
 273          */
 274
 275         /*
 276          * For some lo/hi registers (like perfcounters), the hi value is latched
 277          * when the lo is read, so make sure to read the lo first to trigger
 278          * that
 279          */
 280         val = (u64) msm_readl(gpu->mmio + (lo << 2));
 281         val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
 282
 283         return val;
 284 }
 285
 286 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
 287 {
 288         /* Why not a writeq here? Read the screed above */
 289         msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
 290         msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
 291 }
 292
 293 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
 294 int msm_gpu_pm_resume(struct msm_gpu *gpu);
 295 void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
 296
 297 int msm_gpu_hw_init(struct msm_gpu *gpu);
 298
 299 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
 300 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
 301 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 302                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
 303
 304 void msm_gpu_retire(struct msm_gpu *gpu);
 305 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
 306
 307 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 308                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 309                 const char *name, struct msm_gpu_config *config);
 310
 311 struct msm_gem_address_space *
 312 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
 313
 314 void msm_gpu_cleanup(struct msm_gpu *gpu);
 315
 316 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
 317 void __init adreno_register(void);
 318 void __exit adreno_unregister(void);
 319
 320 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
 321 {
 322         if (queue)
 323                 kref_put(&queue->ref, msm_submitqueue_destroy);
 324 }
 325
 326 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
 327 {
 328         struct msm_gpu_state *state = NULL;
 329
 330         mutex_lock(&gpu->dev->struct_mutex);
 331
 332         if (gpu->crashstate) {
 333                 kref_get(&gpu->crashstate->ref);
 334                 state = gpu->crashstate;
 335         }
 336
 337         mutex_unlock(&gpu->dev->struct_mutex);
 338
 339         return state;
 340 }
 341
 342 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
 343 {
 344         mutex_lock(&gpu->dev->struct_mutex);
 345
 346         if (gpu->crashstate) {
 347                 if (gpu->funcs->gpu_state_put(gpu->crashstate))
 348                         gpu->crashstate = NULL;
 349         }
 350
 351         mutex_unlock(&gpu->dev->struct_mutex);
 352 }
 353
 354 /*
 355  * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
 356  * support expanded privileges
 357  */
 358 #define check_apriv(gpu, flags) \
 359         (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
 360
 361
 362 #endif /* __MSM_GPU_H__ */