drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NVBIOS_RAMCFG_H__
   3 #define __NVBIOS_RAMCFG_H__
   4 struct nvbios_ramcfg {
   5         unsigned rammap_ver;
   6         unsigned rammap_hdr;
   7         unsigned rammap_min;
   8         unsigned rammap_max;
   9         union {
  10                 struct {
  11                         unsigned rammap_00_16_20:1;
  12                         unsigned rammap_00_16_40:1;
  13                         unsigned rammap_00_17_02:1;
  14                 };
  15                 struct {
  16                         unsigned rammap_10_04_02:1;
  17                         unsigned rammap_10_04_08:1;
  18                 };
  19                 struct {
  20                         unsigned rammap_11_08_01:1;
  21                         unsigned rammap_11_08_0c:2;
  22                         unsigned rammap_11_08_10:1;
  23                         unsigned rammap_11_09_01ff:9;
  24                         unsigned rammap_11_0a_03fe:9;
  25                         unsigned rammap_11_0a_0400:1;
  26                         unsigned rammap_11_0a_0800:1;
  27                         unsigned rammap_11_0b_01f0:5;
  28                         unsigned rammap_11_0b_0200:1;
  29                         unsigned rammap_11_0b_0400:1;
  30                         unsigned rammap_11_0b_0800:1;
  31                         unsigned rammap_11_0d:8;
  32                         unsigned rammap_11_0e:8;
  33                         unsigned rammap_11_0f:8;
  34                         unsigned rammap_11_11_0c:2;
  35                 };
  36         };
  37
  38         unsigned ramcfg_ver;
  39         unsigned ramcfg_hdr;
  40         unsigned ramcfg_timing;
  41         unsigned ramcfg_DLLoff;
  42         unsigned ramcfg_RON;
  43         unsigned ramcfg_FBVDDQ;
  44         union {
  45                 struct {
  46                         unsigned ramcfg_00_03_01:1;
  47                         unsigned ramcfg_00_03_02:1;
  48                         unsigned ramcfg_00_03_08:1;
  49                         unsigned ramcfg_00_03_10:1;
  50                         unsigned ramcfg_00_04_02:1;
  51                         unsigned ramcfg_00_04_04:1;
  52                         unsigned ramcfg_00_04_20:1;
  53                         unsigned ramcfg_00_05:8;
  54                         unsigned ramcfg_00_06:8;
  55                         unsigned ramcfg_00_07:8;
  56                         unsigned ramcfg_00_08:8;
  57                         unsigned ramcfg_00_09:8;
  58                         unsigned ramcfg_00_0a_0f:4;
  59                         unsigned ramcfg_00_0a_f0:4;
  60                 };
  61                 struct {
  62                         unsigned ramcfg_10_02_01:1;
  63                         unsigned ramcfg_10_02_02:1;
  64                         unsigned ramcfg_10_02_04:1;
  65                         unsigned ramcfg_10_02_08:1;
  66                         unsigned ramcfg_10_02_10:1;
  67                         unsigned ramcfg_10_02_20:1;
  68                         unsigned ramcfg_10_03_0f:4;
  69                         unsigned ramcfg_10_04_01:1;
  70                         unsigned ramcfg_10_05:8;
  71                         unsigned ramcfg_10_06:8;
  72                         unsigned ramcfg_10_07:8;
  73                         unsigned ramcfg_10_08:8;
  74                         unsigned ramcfg_10_09_0f:4;
  75                         unsigned ramcfg_10_09_f0:4;
  76                 };
  77                 struct {
  78                         unsigned ramcfg_11_01_01:1;
  79                         unsigned ramcfg_11_01_02:1;
  80                         unsigned ramcfg_11_01_04:1;
  81                         unsigned ramcfg_11_01_08:1;
  82                         unsigned ramcfg_11_01_10:1;
  83                         unsigned ramcfg_11_01_40:1;
  84                         unsigned ramcfg_11_01_80:1;
  85                         unsigned ramcfg_11_02_03:2;
  86                         unsigned ramcfg_11_02_04:1;
  87                         unsigned ramcfg_11_02_08:1;
  88                         unsigned ramcfg_11_02_10:1;
  89                         unsigned ramcfg_11_02_40:1;
  90                         unsigned ramcfg_11_02_80:1;
  91                         unsigned ramcfg_11_03_0f:4;
  92                         unsigned ramcfg_11_03_30:2;
  93                         unsigned ramcfg_11_03_c0:2;
  94                         unsigned ramcfg_11_03_f0:4;
  95                         unsigned ramcfg_11_04:8;
  96                         unsigned ramcfg_11_06:8;
  97                         unsigned ramcfg_11_07_02:1;
  98                         unsigned ramcfg_11_07_04:1;
  99                         unsigned ramcfg_11_07_08:1;
 100                         unsigned ramcfg_11_07_10:1;
 101                         unsigned ramcfg_11_07_40:1;
 102                         unsigned ramcfg_11_07_80:1;
 103                         unsigned ramcfg_11_08_01:1;
 104                         unsigned ramcfg_11_08_02:1;
 105                         unsigned ramcfg_11_08_04:1;
 106                         unsigned ramcfg_11_08_08:1;
 107                         unsigned ramcfg_11_08_10:1;
 108                         unsigned ramcfg_11_08_20:1;
 109                         unsigned ramcfg_11_09:8;
 110                 };
 111         };
 112
 113         unsigned timing_ver;
 114         unsigned timing_hdr;
 115         unsigned timing[11];
 116         union {
 117                 struct {
 118                         unsigned timing_10_WR:8;
 119                         unsigned timing_10_WTR:8;
 120                         unsigned timing_10_CL:8;
 121                         unsigned timing_10_RC:8;
 122                         /*empty: 4 */
 123                         unsigned timing_10_RFC:8;        /* Byte 5 */
 124                         /*empty: 6 */
 125                         unsigned timing_10_RAS:8;        /* Byte 7 */
 126                         /*empty: 8 */
 127                         unsigned timing_10_RP:8;         /* Byte 9 */
 128                         unsigned timing_10_RCDRD:8;
 129                         unsigned timing_10_RCDWR:8;
 130                         unsigned timing_10_RRD:8;
 131                         unsigned timing_10_13:8;
 132                         unsigned timing_10_ODT:3;
 133                         /* empty: 15 */
 134                         unsigned timing_10_16:8;
 135                         /* empty: 17 */
 136                         unsigned timing_10_18:8;
 137                         unsigned timing_10_CWL:8;
 138                         unsigned timing_10_20:8;
 139                         unsigned timing_10_21:8;
 140                         /* empty: 22, 23 */
 141                         unsigned timing_10_24:8;
 142                 };
 143                 struct {
 144                         unsigned timing_20_2e_03:2;
 145                         unsigned timing_20_2e_30:2;
 146                         unsigned timing_20_2e_c0:2;
 147                         unsigned timing_20_2f_03:2;
 148                         unsigned timing_20_2c_003f:6;
 149                         unsigned timing_20_2c_1fc0:7;
 150                         unsigned timing_20_30_f8:5;
 151                         unsigned timing_20_30_07:3;
 152                         unsigned timing_20_31_0007:3;
 153                         unsigned timing_20_31_0078:4;
 154                         unsigned timing_20_31_0780:4;
 155                         unsigned timing_20_31_0800:1;
 156                         unsigned timing_20_31_7000:3;
 157                         unsigned timing_20_31_8000:1;
 158                 };
 159         };
 160 };
 161
 162 u8 nvbios_ramcfg_count(struct nvkm_bios *);
 163 u8 nvbios_ramcfg_index(struct nvkm_subdev *);
 164 #endif