drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25
  26 #include <subdev/bios.h>
  27 #include <subdev/bios/init.h>
  28 #include <subdev/bios/pll.h>
  29 #include <subdev/clk/pll.h>
  30
  31 int
  32 gt215_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
  33 {
  34         struct nvkm_subdev *subdev = &init->subdev;
  35         struct nvkm_device *device = subdev->device;
  36         struct nvbios_pll info;
  37         int N, fN, M, P;
  38         int ret;
  39
  40         ret = nvbios_pll_parse(device->bios, type, &info);
  41         if (ret)
  42                 return ret;
  43
  44         ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
  45         if (ret < 0)
  46                 return ret;
  47
  48         switch (info.type) {
  49         case PLL_VPLL0:
  50         case PLL_VPLL1:
  51                 nvkm_wr32(device, info.reg + 0, 0x50000610);
  52                 nvkm_mask(device, info.reg + 4, 0x003fffff,
  53                                                 (P << 16) | (M << 8) | N);
  54                 nvkm_wr32(device, info.reg + 8, fN);
  55                 break;
  56         default:
  57                 nvkm_warn(subdev, "%08x/%dKhz unimplemented\n", type, freq);
  58                 ret = -EINVAL;
  59                 break;
  60         }
  61
  62         return ret;
  63 }
  64
  65 static u64
  66 gt215_devinit_disable(struct nvkm_devinit *init)
  67 {
  68         struct nvkm_device *device = init->subdev.device;
  69         u32 r001540 = nvkm_rd32(device, 0x001540);
  70         u32 r00154c = nvkm_rd32(device, 0x00154c);
  71         u64 disable = 0ULL;
  72
  73         if (!(r001540 & 0x40000000)) {
  74                 disable |= (1ULL << NVKM_ENGINE_MSPDEC);
  75                 disable |= (1ULL << NVKM_ENGINE_MSPPP);
  76         }
  77
  78         if (!(r00154c & 0x00000004))
  79                 disable |= (1ULL << NVKM_ENGINE_DISP);
  80         if (!(r00154c & 0x00000020))
  81                 disable |= (1ULL << NVKM_ENGINE_MSVLD);
  82         if (!(r00154c & 0x00000200))
  83                 disable |= (1ULL << NVKM_ENGINE_CE0);
  84
  85         return disable;
  86 }
  87
  88 static u32
  89 gt215_devinit_mmio_part[] = {
  90         0x100720, 0x1008bc, 4,
  91         0x100a20, 0x100adc, 4,
  92         0x100d80, 0x100ddc, 4,
  93         0x110000, 0x110f9c, 4,
  94         0x111000, 0x11103c, 8,
  95         0x111080, 0x1110fc, 4,
  96         0x111120, 0x1111fc, 4,
  97         0x111300, 0x1114bc, 4,
  98         0,
  99 };
 100
 101 static u32
 102 gt215_devinit_mmio(struct nvkm_devinit *base, u32 addr)
 103 {
 104         struct nv50_devinit *init = nv50_devinit(base);
 105         struct nvkm_device *device = init->base.subdev.device;
 106         u32 *mmio = gt215_devinit_mmio_part;
 107
 108         /* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP
 109          * instructions which touch registers that may not even exist on
 110          * some configurations (Quadro 400), which causes the register
 111          * interface to screw up for some amount of time after attempting to
 112          * write to one of these, and results in all sorts of things going
 113          * horribly wrong.
 114          *
 115          * the binary driver avoids touching these registers at all, however,
 116          * the video bios doesn't care and does what the scripts say.  it's
 117          * presumed that the io-port access to init registers isn't effected
 118          * by the screw-up bug mentioned above.
 119          *
 120          * really, a new opcode should've been invented to handle these
 121          * requirements, but whatever, it's too late for that now.
 122          */
 123         while (mmio[0]) {
 124                 if (addr >= mmio[0] && addr <= mmio[1]) {
 125                         u32 part = (addr / mmio[2]) & 7;
 126                         if (!init->r001540)
 127                                 init->r001540 = nvkm_rd32(device, 0x001540);
 128                         if (part >= hweight8((init->r001540 >> 16) & 0xff))
 129                                 return ~0;
 130                         return addr;
 131                 }
 132                 mmio += 3;
 133         }
 134
 135         return addr;
 136 }
 137
 138 static const struct nvkm_devinit_func
 139 gt215_devinit = {
 140         .preinit = nv50_devinit_preinit,
 141         .init = nv50_devinit_init,
 142         .post = nv04_devinit_post,
 143         .mmio = gt215_devinit_mmio,
 144         .pll_set = gt215_devinit_pll_set,
 145         .disable = gt215_devinit_disable,
 146 };
 147
 148 int
 149 gt215_devinit_new(struct nvkm_device *device, int index,
 150                 struct nvkm_devinit **pinit)
 151 {
 152         return nv50_devinit_new_(&gt215_devinit, device, index, pinit);
 153 }