drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Lyude Paul
  23  */
  24 #include <core/device.h>
  25
  26 #include "priv.h"
  27 #include "gk104.h"
  28
  29 void
  30 gk104_clkgate_enable(struct nvkm_therm *base)
  31 {
  32         struct gk104_therm *therm = gk104_therm(base);
  33         struct nvkm_device *dev = therm->base.subdev.device;
  34         const struct gk104_clkgate_engine_info *order = therm->clkgate_order;
  35         int i;
  36
  37         /* Program ENG_MANT, ENG_FILTER */
  38         for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
  39                 if (!nvkm_device_subdev(dev, order[i].engine))
  40                         continue;
  41
  42                 nvkm_mask(dev, 0x20200 + order[i].offset, 0xff00, 0x4500);
  43         }
  44
  45         /* magic */
  46         nvkm_wr32(dev, 0x020288, therm->idle_filter->fecs);
  47         nvkm_wr32(dev, 0x02028c, therm->idle_filter->hubmmu);
  48
  49         /* Enable clockgating (ENG_CLK = RUN->AUTO) */
  50         for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
  51                 if (!nvkm_device_subdev(dev, order[i].engine))
  52                         continue;
  53
  54                 nvkm_mask(dev, 0x20200 + order[i].offset, 0x00ff, 0x0045);
  55         }
  56 }
  57
  58 void
  59 gk104_clkgate_fini(struct nvkm_therm *base, bool suspend)
  60 {
  61         struct gk104_therm *therm = gk104_therm(base);
  62         struct nvkm_device *dev = therm->base.subdev.device;
  63         const struct gk104_clkgate_engine_info *order = therm->clkgate_order;
  64         int i;
  65
  66         /* ENG_CLK = AUTO->RUN, ENG_PWR = RUN->AUTO */
  67         for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
  68                 if (!nvkm_device_subdev(dev, order[i].engine))
  69                         continue;
  70
  71                 nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54);
  72         }
  73 }
  74
  75 const struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = {
  76         { NVKM_ENGINE_GR,     0x00 },
  77         { NVKM_ENGINE_MSPDEC, 0x04 },
  78         { NVKM_ENGINE_MSPPP,  0x08 },
  79         { NVKM_ENGINE_MSVLD,  0x0c },
  80         { NVKM_ENGINE_CE0,    0x10 },
  81         { NVKM_ENGINE_CE1,    0x14 },
  82         { NVKM_ENGINE_MSENC,  0x18 },
  83         { NVKM_ENGINE_CE2,    0x1c },
  84         { NVKM_SUBDEV_NR, 0 },
  85 };
  86
  87 const struct gf100_idle_filter gk104_idle_filter = {
  88         .fecs = 0x00001000,
  89         .hubmmu = 0x00001000,
  90 };
  91
  92 static const struct nvkm_therm_func
  93 gk104_therm_func = {
  94         .init = gf119_therm_init,
  95         .fini = g84_therm_fini,
  96         .pwm_ctrl = gf119_fan_pwm_ctrl,
  97         .pwm_get = gf119_fan_pwm_get,
  98         .pwm_set = gf119_fan_pwm_set,
  99         .pwm_clock = gf119_fan_pwm_clock,
 100         .temp_get = g84_temp_get,
 101         .fan_sense = gt215_therm_fan_sense,
 102         .program_alarms = nvkm_therm_program_alarms_polling,
 103         .clkgate_init = gf100_clkgate_init,
 104         .clkgate_enable = gk104_clkgate_enable,
 105         .clkgate_fini = gk104_clkgate_fini,
 106 };
 107
 108 static int
 109 gk104_therm_new_(const struct nvkm_therm_func *func,
 110                  struct nvkm_device *device,
 111                  int index,
 112                  const struct gk104_clkgate_engine_info *clkgate_order,
 113                  const struct gf100_idle_filter *idle_filter,
 114                  struct nvkm_therm **ptherm)
 115 {
 116         struct gk104_therm *therm = kzalloc(sizeof(*therm), GFP_KERNEL);
 117
 118         if (!therm)
 119                 return -ENOMEM;
 120
 121         nvkm_therm_ctor(&therm->base, device, index, func);
 122         *ptherm = &therm->base;
 123         therm->clkgate_order = clkgate_order;
 124         therm->idle_filter = idle_filter;
 125
 126         return 0;
 127 }
 128
 129 int
 130 gk104_therm_new(struct nvkm_device *device,
 131                 int index, struct nvkm_therm **ptherm)
 132 {
 133         return gk104_therm_new_(&gk104_therm_func, device, index,
 134                                 gk104_clkgate_engine_info, &gk104_idle_filter,
 135                                 ptherm);
 136 }