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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / omapdrm / dss / dsi.c
blob735a4e9027d0c38e138fbc5c1b6941c8e8b26826
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 */
6
7 #define DSS_SUBSYS_NAME "DSI"
8
9 #include <linux/kernel.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/regmap.h>
12 #include <linux/io.h>
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/mutex.h>
19 #include <linux/module.h>
20 #include <linux/semaphore.h>
21 #include <linux/seq_file.h>
22 #include <linux/platform_device.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/wait.h>
25 #include <linux/workqueue.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/of.h>
31 #include <linux/of_graph.h>
32 #include <linux/of_platform.h>
33 #include <linux/component.h>
34 #include <linux/sys_soc.h>
35
36 #include <video/mipi_display.h>
37
38 #include "omapdss.h"
39 #include "dss.h"
40
41 #define DSI_CATCH_MISSING_TE
42
43 struct dsi_reg { u16 module; u16 idx; };
44
45 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
46
47 /* DSI Protocol Engine */
48
49 #define DSI_PROTO 0
50 #define DSI_PROTO_SZ 0x200
51
52 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
53 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
54 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
55 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
56 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
57 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
58 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
59 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
60 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
61 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
62 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
63 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
64 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
65 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
66 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
67 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
68 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
69 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
70 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
71 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
72 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
73 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
74 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
75 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
76 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
77 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
78 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
79 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
80 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
83 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
84 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
85 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
86
87 /* DSIPHY_SCP */
88
89 #define DSI_PHY 1
90 #define DSI_PHY_OFFSET 0x200
91 #define DSI_PHY_SZ 0x40
92
93 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
94 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
95 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
96 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
97 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
98
99 /* DSI_PLL_CTRL_SCP */
100
101 #define DSI_PLL 2
102 #define DSI_PLL_OFFSET 0x300
103 #define DSI_PLL_SZ 0x20
104
105 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
106 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
107 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
108 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
109 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
110
111 #define REG_GET(dsi, idx, start, end) \
112 FLD_GET(dsi_read_reg(dsi, idx), start, end)
113
114 #define REG_FLD_MOD(dsi, idx, val, start, end) \
115 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
116
117 /* Global interrupts */
118 #define DSI_IRQ_VC0 (1 << 0)
119 #define DSI_IRQ_VC1 (1 << 1)
120 #define DSI_IRQ_VC2 (1 << 2)
121 #define DSI_IRQ_VC3 (1 << 3)
122 #define DSI_IRQ_WAKEUP (1 << 4)
123 #define DSI_IRQ_RESYNC (1 << 5)
124 #define DSI_IRQ_PLL_LOCK (1 << 7)
125 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
126 #define DSI_IRQ_PLL_RECALL (1 << 9)
127 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
128 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
129 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
130 #define DSI_IRQ_TE_TRIGGER (1 << 16)
131 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
132 #define DSI_IRQ_SYNC_LOST (1 << 18)
133 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
134 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
135 #define DSI_IRQ_ERROR_MASK \
136 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
137 DSI_IRQ_TA_TIMEOUT)
138 #define DSI_IRQ_CHANNEL_MASK 0xf
139
140 /* Virtual channel interrupts */
141 #define DSI_VC_IRQ_CS (1 << 0)
142 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
143 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
144 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
145 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
146 #define DSI_VC_IRQ_BTA (1 << 5)
147 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
148 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
149 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
150 #define DSI_VC_IRQ_ERROR_MASK \
151 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
152 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
153 DSI_VC_IRQ_FIFO_TX_UDF)
154
155 /* ComplexIO interrupts */
156 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
157 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
158 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
159 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
160 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
161 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
162 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
163 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
164 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
165 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
166 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
167 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
168 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
169 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
170 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
171 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
172 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
173 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
174 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
175 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
185 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
187 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
188 #define DSI_CIO_IRQ_ERROR_MASK \
189 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
190 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
191 DSI_CIO_IRQ_ERRSYNCESC5 | \
192 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
193 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
194 DSI_CIO_IRQ_ERRESC5 | \
195 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
196 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
197 DSI_CIO_IRQ_ERRCONTROL5 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
202 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
203
204 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
205 struct dsi_data;
206
207 static int dsi_display_init_dispc(struct dsi_data *dsi);
208 static void dsi_display_uninit_dispc(struct dsi_data *dsi);
209
210 static int dsi_vc_send_null(struct dsi_data *dsi, int channel);
211
212 /* DSI PLL HSDIV indices */
213 #define HSDIV_DISPC 0
214 #define HSDIV_DSI 1
215
216 #define DSI_MAX_NR_ISRS 2
217 #define DSI_MAX_NR_LANES 5
218
219 enum dsi_model {
220 DSI_MODEL_OMAP3,
221 DSI_MODEL_OMAP4,
222 DSI_MODEL_OMAP5,
223 };
224
225 enum dsi_lane_function {
226 DSI_LANE_UNUSED = 0,
227 DSI_LANE_CLK,
228 DSI_LANE_DATA1,
229 DSI_LANE_DATA2,
230 DSI_LANE_DATA3,
231 DSI_LANE_DATA4,
232 };
233
234 struct dsi_lane_config {
235 enum dsi_lane_function function;
236 u8 polarity;
237 };
238
239 struct dsi_isr_data {
240 omap_dsi_isr_t isr;
241 void *arg;
242 u32 mask;
243 };
244
245 enum fifo_size {
246 DSI_FIFO_SIZE_0 = 0,
247 DSI_FIFO_SIZE_32 = 1,
248 DSI_FIFO_SIZE_64 = 2,
249 DSI_FIFO_SIZE_96 = 3,
250 DSI_FIFO_SIZE_128 = 4,
251 };
252
253 enum dsi_vc_source {
254 DSI_VC_SOURCE_L4 = 0,
255 DSI_VC_SOURCE_VP,
256 };
257
258 struct dsi_irq_stats {
259 unsigned long last_reset;
260 unsigned int irq_count;
261 unsigned int dsi_irqs[32];
262 unsigned int vc_irqs[4][32];
263 unsigned int cio_irqs[32];
264 };
265
266 struct dsi_isr_tables {
267 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
268 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
269 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
270 };
271
272 struct dsi_clk_calc_ctx {
273 struct dsi_data *dsi;
274 struct dss_pll *pll;
275
276 /* inputs */
277
278 const struct omap_dss_dsi_config *config;
279
280 unsigned long req_pck_min, req_pck_nom, req_pck_max;
281
282 /* outputs */
283
284 struct dss_pll_clock_info dsi_cinfo;
285 struct dispc_clock_info dispc_cinfo;
286
287 struct videomode vm;
288 struct omap_dss_dsi_videomode_timings dsi_vm;
289 };
290
291 struct dsi_lp_clock_info {
292 unsigned long lp_clk;
293 u16 lp_clk_div;
294 };
295
296 struct dsi_module_id_data {
297 u32 address;
298 int id;
299 };
300
301 enum dsi_quirks {
302 DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */
303 DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1),
304 DSI_QUIRK_VC_OCP_WIDTH = (1 << 2),
305 DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3),
306 DSI_QUIRK_GNQ = (1 << 4),
307 DSI_QUIRK_PHY_DCC = (1 << 5),
308 };
309
310 struct dsi_of_data {
311 enum dsi_model model;
312 const struct dss_pll_hw *pll_hw;
313 const struct dsi_module_id_data *modules;
314 unsigned int max_fck_freq;
315 unsigned int max_pll_lpdiv;
316 enum dsi_quirks quirks;
317 };
318
319 struct dsi_data {
320 struct device *dev;
321 void __iomem *proto_base;
322 void __iomem *phy_base;
323 void __iomem *pll_base;
324
325 const struct dsi_of_data *data;
326 int module_id;
327
328 int irq;
329
330 bool is_enabled;
331
332 struct clk *dss_clk;
333 struct regmap *syscon;
334 struct dss_device *dss;
335
336 struct dispc_clock_info user_dispc_cinfo;
337 struct dss_pll_clock_info user_dsi_cinfo;
338
339 struct dsi_lp_clock_info user_lp_cinfo;
340 struct dsi_lp_clock_info current_lp_cinfo;
341
342 struct dss_pll pll;
343
344 bool vdds_dsi_enabled;
345 struct regulator *vdds_dsi_reg;
346
347 struct {
348 enum dsi_vc_source source;
349 struct omap_dss_device *dssdev;
350 enum fifo_size tx_fifo_size;
351 enum fifo_size rx_fifo_size;
352 int vc_id;
353 } vc[4];
354
355 struct mutex lock;
356 struct semaphore bus_lock;
357
358 spinlock_t irq_lock;
359 struct dsi_isr_tables isr_tables;
360 /* space for a copy used by the interrupt handler */
361 struct dsi_isr_tables isr_tables_copy;
362
363 int update_channel;
364 #ifdef DSI_PERF_MEASURE
365 unsigned int update_bytes;
366 #endif
367
368 bool te_enabled;
369 bool ulps_enabled;
370
371 void (*framedone_callback)(int, void *);
372 void *framedone_data;
373
374 struct delayed_work framedone_timeout_work;
375
376 #ifdef DSI_CATCH_MISSING_TE
377 struct timer_list te_timer;
378 #endif
379
380 unsigned long cache_req_pck;
381 unsigned long cache_clk_freq;
382 struct dss_pll_clock_info cache_cinfo;
383
384 u32 errors;
385 spinlock_t errors_lock;
386 #ifdef DSI_PERF_MEASURE
387 ktime_t perf_setup_time;
388 ktime_t perf_start_time;
389 #endif
390 int debug_read;
391 int debug_write;
392 struct {
393 struct dss_debugfs_entry *irqs;
394 struct dss_debugfs_entry *regs;
395 struct dss_debugfs_entry *clks;
396 } debugfs;
397
398 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
399 spinlock_t irq_stats_lock;
400 struct dsi_irq_stats irq_stats;
401 #endif
402
403 unsigned int num_lanes_supported;
404 unsigned int line_buffer_size;
405
406 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
407 unsigned int num_lanes_used;
408
409 unsigned int scp_clk_refcount;
410
411 struct dss_lcd_mgr_config mgr_config;
412 struct videomode vm;
413 enum omap_dss_dsi_pixel_format pix_fmt;
414 enum omap_dss_dsi_mode mode;
415 struct omap_dss_dsi_videomode_timings vm_timings;
416
417 struct omap_dss_device output;
418 };
419
420 struct dsi_packet_sent_handler_data {
421 struct dsi_data *dsi;
422 struct completion *completion;
423 };
424
425 #ifdef DSI_PERF_MEASURE
426 static bool dsi_perf;
427 module_param(dsi_perf, bool, 0644);
428 #endif
429
430 static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev)
431 {
432 return dev_get_drvdata(dssdev->dev);
433 }
434
435 static inline void dsi_write_reg(struct dsi_data *dsi,
436 const struct dsi_reg idx, u32 val)
437 {
438 void __iomem *base;
439
440 switch(idx.module) {
441 case DSI_PROTO: base = dsi->proto_base; break;
442 case DSI_PHY: base = dsi->phy_base; break;
443 case DSI_PLL: base = dsi->pll_base; break;
444 default: return;
445 }
446
447 __raw_writel(val, base + idx.idx);
448 }
449
450 static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx)
451 {
452 void __iomem *base;
453
454 switch(idx.module) {
455 case DSI_PROTO: base = dsi->proto_base; break;
456 case DSI_PHY: base = dsi->phy_base; break;
457 case DSI_PLL: base = dsi->pll_base; break;
458 default: return 0;
459 }
460
461 return __raw_readl(base + idx.idx);
462 }
463
464 static void dsi_bus_lock(struct omap_dss_device *dssdev)
465 {
466 struct dsi_data *dsi = to_dsi_data(dssdev);
467
468 down(&dsi->bus_lock);
469 }
470
471 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
472 {
473 struct dsi_data *dsi = to_dsi_data(dssdev);
474
475 up(&dsi->bus_lock);
476 }
477
478 static bool dsi_bus_is_locked(struct dsi_data *dsi)
479 {
480 return dsi->bus_lock.count == 0;
481 }
482
483 static void dsi_completion_handler(void *data, u32 mask)
484 {
485 complete((struct completion *)data);
486 }
487
488 static inline bool wait_for_bit_change(struct dsi_data *dsi,
489 const struct dsi_reg idx,
490 int bitnum, int value)
491 {
492 unsigned long timeout;
493 ktime_t wait;
494 int t;
495
496 /* first busyloop to see if the bit changes right away */
497 t = 100;
498 while (t-- > 0) {
499 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
500 return true;
501 }
502
503 /* then loop for 500ms, sleeping for 1ms in between */
504 timeout = jiffies + msecs_to_jiffies(500);
505 while (time_before(jiffies, timeout)) {
506 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
507 return true;
508
509 wait = ns_to_ktime(1000 * 1000);
510 set_current_state(TASK_UNINTERRUPTIBLE);
511 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
512 }
513
514 return false;
515 }
516
517 static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
518 {
519 switch (fmt) {
520 case OMAP_DSS_DSI_FMT_RGB888:
521 case OMAP_DSS_DSI_FMT_RGB666:
522 return 24;
523 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
524 return 18;
525 case OMAP_DSS_DSI_FMT_RGB565:
526 return 16;
527 default:
528 BUG();
529 return 0;
530 }
531 }
532
533 #ifdef DSI_PERF_MEASURE
534 static void dsi_perf_mark_setup(struct dsi_data *dsi)
535 {
536 dsi->perf_setup_time = ktime_get();
537 }
538
539 static void dsi_perf_mark_start(struct dsi_data *dsi)
540 {
541 dsi->perf_start_time = ktime_get();
542 }
543
544 static void dsi_perf_show(struct dsi_data *dsi, const char *name)
545 {
546 ktime_t t, setup_time, trans_time;
547 u32 total_bytes;
548 u32 setup_us, trans_us, total_us;
549
550 if (!dsi_perf)
551 return;
552
553 t = ktime_get();
554
555 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
556 setup_us = (u32)ktime_to_us(setup_time);
557 if (setup_us == 0)
558 setup_us = 1;
559
560 trans_time = ktime_sub(t, dsi->perf_start_time);
561 trans_us = (u32)ktime_to_us(trans_time);
562 if (trans_us == 0)
563 trans_us = 1;
564
565 total_us = setup_us + trans_us;
566
567 total_bytes = dsi->update_bytes;
568
569 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n",
570 name,
571 setup_us,
572 trans_us,
573 total_us,
574 1000 * 1000 / total_us,
575 total_bytes,
576 total_bytes * 1000 / total_us);
577 }
578 #else
579 static inline void dsi_perf_mark_setup(struct dsi_data *dsi)
580 {
581 }
582
583 static inline void dsi_perf_mark_start(struct dsi_data *dsi)
584 {
585 }
586
587 static inline void dsi_perf_show(struct dsi_data *dsi, const char *name)
588 {
589 }
590 #endif
591
592 static int verbose_irq;
593
594 static void print_irq_status(u32 status)
595 {
596 if (status == 0)
597 return;
598
599 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
600 return;
601
602 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
603
604 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
605 status,
606 verbose_irq ? PIS(VC0) : "",
607 verbose_irq ? PIS(VC1) : "",
608 verbose_irq ? PIS(VC2) : "",
609 verbose_irq ? PIS(VC3) : "",
610 PIS(WAKEUP),
611 PIS(RESYNC),
612 PIS(PLL_LOCK),
613 PIS(PLL_UNLOCK),
614 PIS(PLL_RECALL),
615 PIS(COMPLEXIO_ERR),
616 PIS(HS_TX_TIMEOUT),
617 PIS(LP_RX_TIMEOUT),
618 PIS(TE_TRIGGER),
619 PIS(ACK_TRIGGER),
620 PIS(SYNC_LOST),
621 PIS(LDO_POWER_GOOD),
622 PIS(TA_TIMEOUT));
623 #undef PIS
624 }
625
626 static void print_irq_status_vc(int channel, u32 status)
627 {
628 if (status == 0)
629 return;
630
631 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
632 return;
633
634 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
635
636 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
637 channel,
638 status,
639 PIS(CS),
640 PIS(ECC_CORR),
641 PIS(ECC_NO_CORR),
642 verbose_irq ? PIS(PACKET_SENT) : "",
643 PIS(BTA),
644 PIS(FIFO_TX_OVF),
645 PIS(FIFO_RX_OVF),
646 PIS(FIFO_TX_UDF),
647 PIS(PP_BUSY_CHANGE));
648 #undef PIS
649 }
650
651 static void print_irq_status_cio(u32 status)
652 {
653 if (status == 0)
654 return;
655
656 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
657
658 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
659 status,
660 PIS(ERRSYNCESC1),
661 PIS(ERRSYNCESC2),
662 PIS(ERRSYNCESC3),
663 PIS(ERRESC1),
664 PIS(ERRESC2),
665 PIS(ERRESC3),
666 PIS(ERRCONTROL1),
667 PIS(ERRCONTROL2),
668 PIS(ERRCONTROL3),
669 PIS(STATEULPS1),
670 PIS(STATEULPS2),
671 PIS(STATEULPS3),
672 PIS(ERRCONTENTIONLP0_1),
673 PIS(ERRCONTENTIONLP1_1),
674 PIS(ERRCONTENTIONLP0_2),
675 PIS(ERRCONTENTIONLP1_2),
676 PIS(ERRCONTENTIONLP0_3),
677 PIS(ERRCONTENTIONLP1_3),
678 PIS(ULPSACTIVENOT_ALL0),
679 PIS(ULPSACTIVENOT_ALL1));
680 #undef PIS
681 }
682
683 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
684 static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus,
685 u32 *vcstatus, u32 ciostatus)
686 {
687 int i;
688
689 spin_lock(&dsi->irq_stats_lock);
690
691 dsi->irq_stats.irq_count++;
692 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
693
694 for (i = 0; i < 4; ++i)
695 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
696
697 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
698
699 spin_unlock(&dsi->irq_stats_lock);
700 }
701 #else
702 #define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus)
703 #endif
704
705 static int debug_irq;
706
707 static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus,
708 u32 *vcstatus, u32 ciostatus)
709 {
710 int i;
711
712 if (irqstatus & DSI_IRQ_ERROR_MASK) {
713 DSSERR("DSI error, irqstatus %x\n", irqstatus);
714 print_irq_status(irqstatus);
715 spin_lock(&dsi->errors_lock);
716 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
717 spin_unlock(&dsi->errors_lock);
718 } else if (debug_irq) {
719 print_irq_status(irqstatus);
720 }
721
722 for (i = 0; i < 4; ++i) {
723 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
724 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
725 i, vcstatus[i]);
726 print_irq_status_vc(i, vcstatus[i]);
727 } else if (debug_irq) {
728 print_irq_status_vc(i, vcstatus[i]);
729 }
730 }
731
732 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
733 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
734 print_irq_status_cio(ciostatus);
735 } else if (debug_irq) {
736 print_irq_status_cio(ciostatus);
737 }
738 }
739
740 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
741 unsigned int isr_array_size, u32 irqstatus)
742 {
743 struct dsi_isr_data *isr_data;
744 int i;
745
746 for (i = 0; i < isr_array_size; i++) {
747 isr_data = &isr_array[i];
748 if (isr_data->isr && isr_data->mask & irqstatus)
749 isr_data->isr(isr_data->arg, irqstatus);
750 }
751 }
752
753 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
754 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
755 {
756 int i;
757
758 dsi_call_isrs(isr_tables->isr_table,
759 ARRAY_SIZE(isr_tables->isr_table),
760 irqstatus);
761
762 for (i = 0; i < 4; ++i) {
763 if (vcstatus[i] == 0)
764 continue;
765 dsi_call_isrs(isr_tables->isr_table_vc[i],
766 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
767 vcstatus[i]);
768 }
769
770 if (ciostatus != 0)
771 dsi_call_isrs(isr_tables->isr_table_cio,
772 ARRAY_SIZE(isr_tables->isr_table_cio),
773 ciostatus);
774 }
775
776 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
777 {
778 struct dsi_data *dsi = arg;
779 u32 irqstatus, vcstatus[4], ciostatus;
780 int i;
781
782 if (!dsi->is_enabled)
783 return IRQ_NONE;
784
785 spin_lock(&dsi->irq_lock);
786
787 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS);
788
789 /* IRQ is not for us */
790 if (!irqstatus) {
791 spin_unlock(&dsi->irq_lock);
792 return IRQ_NONE;
793 }
794
795 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
796 /* flush posted write */
797 dsi_read_reg(dsi, DSI_IRQSTATUS);
798
799 for (i = 0; i < 4; ++i) {
800 if ((irqstatus & (1 << i)) == 0) {
801 vcstatus[i] = 0;
802 continue;
803 }
804
805 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
806
807 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]);
808 /* flush posted write */
809 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
810 }
811
812 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
813 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
814
815 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
816 /* flush posted write */
817 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
818 } else {
819 ciostatus = 0;
820 }
821
822 #ifdef DSI_CATCH_MISSING_TE
823 if (irqstatus & DSI_IRQ_TE_TRIGGER)
824 del_timer(&dsi->te_timer);
825 #endif
826
827 /* make a copy and unlock, so that isrs can unregister
828 * themselves */
829 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
830 sizeof(dsi->isr_tables));
831
832 spin_unlock(&dsi->irq_lock);
833
834 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
835
836 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus);
837
838 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus);
839
840 return IRQ_HANDLED;
841 }
842
843 /* dsi->irq_lock has to be locked by the caller */
844 static void _omap_dsi_configure_irqs(struct dsi_data *dsi,
845 struct dsi_isr_data *isr_array,
846 unsigned int isr_array_size,
847 u32 default_mask,
848 const struct dsi_reg enable_reg,
849 const struct dsi_reg status_reg)
850 {
851 struct dsi_isr_data *isr_data;
852 u32 mask;
853 u32 old_mask;
854 int i;
855
856 mask = default_mask;
857
858 for (i = 0; i < isr_array_size; i++) {
859 isr_data = &isr_array[i];
860
861 if (isr_data->isr == NULL)
862 continue;
863
864 mask |= isr_data->mask;
865 }
866
867 old_mask = dsi_read_reg(dsi, enable_reg);
868 /* clear the irqstatus for newly enabled irqs */
869 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask);
870 dsi_write_reg(dsi, enable_reg, mask);
871
872 /* flush posted writes */
873 dsi_read_reg(dsi, enable_reg);
874 dsi_read_reg(dsi, status_reg);
875 }
876
877 /* dsi->irq_lock has to be locked by the caller */
878 static void _omap_dsi_set_irqs(struct dsi_data *dsi)
879 {
880 u32 mask = DSI_IRQ_ERROR_MASK;
881 #ifdef DSI_CATCH_MISSING_TE
882 mask |= DSI_IRQ_TE_TRIGGER;
883 #endif
884 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table,
885 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
886 DSI_IRQENABLE, DSI_IRQSTATUS);
887 }
888
889 /* dsi->irq_lock has to be locked by the caller */
890 static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc)
891 {
892 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc],
893 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
894 DSI_VC_IRQ_ERROR_MASK,
895 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
896 }
897
898 /* dsi->irq_lock has to be locked by the caller */
899 static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi)
900 {
901 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio,
902 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
903 DSI_CIO_IRQ_ERROR_MASK,
904 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
905 }
906
907 static void _dsi_initialize_irq(struct dsi_data *dsi)
908 {
909 unsigned long flags;
910 int vc;
911
912 spin_lock_irqsave(&dsi->irq_lock, flags);
913
914 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
915
916 _omap_dsi_set_irqs(dsi);
917 for (vc = 0; vc < 4; ++vc)
918 _omap_dsi_set_irqs_vc(dsi, vc);
919 _omap_dsi_set_irqs_cio(dsi);
920
921 spin_unlock_irqrestore(&dsi->irq_lock, flags);
922 }
923
924 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
925 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
926 {
927 struct dsi_isr_data *isr_data;
928 int free_idx;
929 int i;
930
931 BUG_ON(isr == NULL);
932
933 /* check for duplicate entry and find a free slot */
934 free_idx = -1;
935 for (i = 0; i < isr_array_size; i++) {
936 isr_data = &isr_array[i];
937
938 if (isr_data->isr == isr && isr_data->arg == arg &&
939 isr_data->mask == mask) {
940 return -EINVAL;
941 }
942
943 if (isr_data->isr == NULL && free_idx == -1)
944 free_idx = i;
945 }
946
947 if (free_idx == -1)
948 return -EBUSY;
949
950 isr_data = &isr_array[free_idx];
951 isr_data->isr = isr;
952 isr_data->arg = arg;
953 isr_data->mask = mask;
954
955 return 0;
956 }
957
958 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
959 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
960 {
961 struct dsi_isr_data *isr_data;
962 int i;
963
964 for (i = 0; i < isr_array_size; i++) {
965 isr_data = &isr_array[i];
966 if (isr_data->isr != isr || isr_data->arg != arg ||
967 isr_data->mask != mask)
968 continue;
969
970 isr_data->isr = NULL;
971 isr_data->arg = NULL;
972 isr_data->mask = 0;
973
974 return 0;
975 }
976
977 return -EINVAL;
978 }
979
980 static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
981 void *arg, u32 mask)
982 {
983 unsigned long flags;
984 int r;
985
986 spin_lock_irqsave(&dsi->irq_lock, flags);
987
988 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
989 ARRAY_SIZE(dsi->isr_tables.isr_table));
990
991 if (r == 0)
992 _omap_dsi_set_irqs(dsi);
993
994 spin_unlock_irqrestore(&dsi->irq_lock, flags);
995
996 return r;
997 }
998
999 static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
1000 void *arg, u32 mask)
1001 {
1002 unsigned long flags;
1003 int r;
1004
1005 spin_lock_irqsave(&dsi->irq_lock, flags);
1006
1007 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1008 ARRAY_SIZE(dsi->isr_tables.isr_table));
1009
1010 if (r == 0)
1011 _omap_dsi_set_irqs(dsi);
1012
1013 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1014
1015 return r;
1016 }
1017
1018 static int dsi_register_isr_vc(struct dsi_data *dsi, int channel,
1019 omap_dsi_isr_t isr, void *arg, u32 mask)
1020 {
1021 unsigned long flags;
1022 int r;
1023
1024 spin_lock_irqsave(&dsi->irq_lock, flags);
1025
1026 r = _dsi_register_isr(isr, arg, mask,
1027 dsi->isr_tables.isr_table_vc[channel],
1028 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1029
1030 if (r == 0)
1031 _omap_dsi_set_irqs_vc(dsi, channel);
1032
1033 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1034
1035 return r;
1036 }
1037
1038 static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel,
1039 omap_dsi_isr_t isr, void *arg, u32 mask)
1040 {
1041 unsigned long flags;
1042 int r;
1043
1044 spin_lock_irqsave(&dsi->irq_lock, flags);
1045
1046 r = _dsi_unregister_isr(isr, arg, mask,
1047 dsi->isr_tables.isr_table_vc[channel],
1048 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1049
1050 if (r == 0)
1051 _omap_dsi_set_irqs_vc(dsi, channel);
1052
1053 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1054
1055 return r;
1056 }
1057
1058 static int dsi_register_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1059 void *arg, u32 mask)
1060 {
1061 unsigned long flags;
1062 int r;
1063
1064 spin_lock_irqsave(&dsi->irq_lock, flags);
1065
1066 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1067 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1068
1069 if (r == 0)
1070 _omap_dsi_set_irqs_cio(dsi);
1071
1072 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1073
1074 return r;
1075 }
1076
1077 static int dsi_unregister_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1078 void *arg, u32 mask)
1079 {
1080 unsigned long flags;
1081 int r;
1082
1083 spin_lock_irqsave(&dsi->irq_lock, flags);
1084
1085 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1086 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1087
1088 if (r == 0)
1089 _omap_dsi_set_irqs_cio(dsi);
1090
1091 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1092
1093 return r;
1094 }
1095
1096 static u32 dsi_get_errors(struct dsi_data *dsi)
1097 {
1098 unsigned long flags;
1099 u32 e;
1100
1101 spin_lock_irqsave(&dsi->errors_lock, flags);
1102 e = dsi->errors;
1103 dsi->errors = 0;
1104 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1105 return e;
1106 }
1107
1108 static int dsi_runtime_get(struct dsi_data *dsi)
1109 {
1110 int r;
1111
1112 DSSDBG("dsi_runtime_get\n");
1113
1114 r = pm_runtime_get_sync(dsi->dev);
1115 if (WARN_ON(r < 0)) {
1116 pm_runtime_put_noidle(dsi->dev);
1117 return r;
1118 }
1119 return 0;
1120 }
1121
1122 static void dsi_runtime_put(struct dsi_data *dsi)
1123 {
1124 int r;
1125
1126 DSSDBG("dsi_runtime_put\n");
1127
1128 r = pm_runtime_put_sync(dsi->dev);
1129 WARN_ON(r < 0 && r != -ENOSYS);
1130 }
1131
1132 static void _dsi_print_reset_status(struct dsi_data *dsi)
1133 {
1134 int b0, b1, b2;
1135
1136 /* A dummy read using the SCP interface to any DSIPHY register is
1137 * required after DSIPHY reset to complete the reset of the DSI complex
1138 * I/O. */
1139 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1140
1141 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
1142 b0 = 28;
1143 b1 = 27;
1144 b2 = 26;
1145 } else {
1146 b0 = 24;
1147 b1 = 25;
1148 b2 = 26;
1149 }
1150
1151 #define DSI_FLD_GET(fld, start, end)\
1152 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end)
1153
1154 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1155 DSI_FLD_GET(PLL_STATUS, 0, 0),
1156 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1157 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1158 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1159 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1160 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1161 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1162 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1163
1164 #undef DSI_FLD_GET
1165 }
1166
1167 static inline int dsi_if_enable(struct dsi_data *dsi, bool enable)
1168 {
1169 DSSDBG("dsi_if_enable(%d)\n", enable);
1170
1171 enable = enable ? 1 : 0;
1172 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */
1173
1174 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) {
1175 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1176 return -EIO;
1177 }
1178
1179 return 0;
1180 }
1181
1182 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi)
1183 {
1184 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1185 }
1186
1187 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi)
1188 {
1189 return dsi->pll.cinfo.clkout[HSDIV_DSI];
1190 }
1191
1192 static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi)
1193 {
1194 return dsi->pll.cinfo.clkdco / 16;
1195 }
1196
1197 static unsigned long dsi_fclk_rate(struct dsi_data *dsi)
1198 {
1199 unsigned long r;
1200 enum dss_clk_source source;
1201
1202 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id);
1203 if (source == DSS_CLK_SRC_FCK) {
1204 /* DSI FCLK source is DSS_CLK_FCK */
1205 r = clk_get_rate(dsi->dss_clk);
1206 } else {
1207 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1208 r = dsi_get_pll_hsdiv_dsi_rate(dsi);
1209 }
1210
1211 return r;
1212 }
1213
1214 static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1215 unsigned long lp_clk_min, unsigned long lp_clk_max,
1216 struct dsi_lp_clock_info *lp_cinfo)
1217 {
1218 unsigned int lp_clk_div;
1219 unsigned long lp_clk;
1220
1221 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1222 lp_clk = dsi_fclk / 2 / lp_clk_div;
1223
1224 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1225 return -EINVAL;
1226
1227 lp_cinfo->lp_clk_div = lp_clk_div;
1228 lp_cinfo->lp_clk = lp_clk;
1229
1230 return 0;
1231 }
1232
1233 static int dsi_set_lp_clk_divisor(struct dsi_data *dsi)
1234 {
1235 unsigned long dsi_fclk;
1236 unsigned int lp_clk_div;
1237 unsigned long lp_clk;
1238 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
1239
1240
1241 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1242
1243 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1244 return -EINVAL;
1245
1246 dsi_fclk = dsi_fclk_rate(dsi);
1247
1248 lp_clk = dsi_fclk / 2 / lp_clk_div;
1249
1250 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1251 dsi->current_lp_cinfo.lp_clk = lp_clk;
1252 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1253
1254 /* LP_CLK_DIVISOR */
1255 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1256
1257 /* LP_RX_SYNCHRO_ENABLE */
1258 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1259
1260 return 0;
1261 }
1262
1263 static void dsi_enable_scp_clk(struct dsi_data *dsi)
1264 {
1265 if (dsi->scp_clk_refcount++ == 0)
1266 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1267 }
1268
1269 static void dsi_disable_scp_clk(struct dsi_data *dsi)
1270 {
1271 WARN_ON(dsi->scp_clk_refcount == 0);
1272 if (--dsi->scp_clk_refcount == 0)
1273 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1274 }
1275
1276 enum dsi_pll_power_state {
1277 DSI_PLL_POWER_OFF = 0x0,
1278 DSI_PLL_POWER_ON_HSCLK = 0x1,
1279 DSI_PLL_POWER_ON_ALL = 0x2,
1280 DSI_PLL_POWER_ON_DIV = 0x3,
1281 };
1282
1283 static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state)
1284 {
1285 int t = 0;
1286
1287 /* DSI-PLL power command 0x3 is not working */
1288 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
1289 state == DSI_PLL_POWER_ON_DIV)
1290 state = DSI_PLL_POWER_ON_ALL;
1291
1292 /* PLL_PWR_CMD */
1293 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30);
1294
1295 /* PLL_PWR_STATUS */
1296 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) {
1297 if (++t > 1000) {
1298 DSSERR("Failed to set DSI PLL power mode to %d\n",
1299 state);
1300 return -ENODEV;
1301 }
1302 udelay(1);
1303 }
1304
1305 return 0;
1306 }
1307
1308
1309 static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi,
1310 struct dss_pll_clock_info *cinfo)
1311 {
1312 unsigned long max_dsi_fck;
1313
1314 max_dsi_fck = dsi->data->max_fck_freq;
1315
1316 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1317 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1318 }
1319
1320 static int dsi_pll_enable(struct dss_pll *pll)
1321 {
1322 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1323 int r = 0;
1324
1325 DSSDBG("PLL init\n");
1326
1327 r = dsi_runtime_get(dsi);
1328 if (r)
1329 return r;
1330
1331 /*
1332 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1333 */
1334 dsi_enable_scp_clk(dsi);
1335
1336 r = regulator_enable(dsi->vdds_dsi_reg);
1337 if (r)
1338 goto err0;
1339
1340 /* XXX PLL does not come out of reset without this... */
1341 dispc_pck_free_enable(dsi->dss->dispc, 1);
1342
1343 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) {
1344 DSSERR("PLL not coming out of reset.\n");
1345 r = -ENODEV;
1346 dispc_pck_free_enable(dsi->dss->dispc, 0);
1347 goto err1;
1348 }
1349
1350 /* XXX ... but if left on, we get problems when planes do not
1351 * fill the whole display. No idea about this */
1352 dispc_pck_free_enable(dsi->dss->dispc, 0);
1353
1354 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL);
1355
1356 if (r)
1357 goto err1;
1358
1359 DSSDBG("PLL init done\n");
1360
1361 return 0;
1362 err1:
1363 regulator_disable(dsi->vdds_dsi_reg);
1364 err0:
1365 dsi_disable_scp_clk(dsi);
1366 dsi_runtime_put(dsi);
1367 return r;
1368 }
1369
1370 static void dsi_pll_disable(struct dss_pll *pll)
1371 {
1372 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1373
1374 dsi_pll_power(dsi, DSI_PLL_POWER_OFF);
1375
1376 regulator_disable(dsi->vdds_dsi_reg);
1377
1378 dsi_disable_scp_clk(dsi);
1379 dsi_runtime_put(dsi);
1380
1381 DSSDBG("PLL disable done\n");
1382 }
1383
1384 static int dsi_dump_dsi_clocks(struct seq_file *s, void *p)
1385 {
1386 struct dsi_data *dsi = s->private;
1387 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1388 enum dss_clk_source dispc_clk_src, dsi_clk_src;
1389 int dsi_module = dsi->module_id;
1390 struct dss_pll *pll = &dsi->pll;
1391
1392 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss);
1393 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module);
1394
1395 if (dsi_runtime_get(dsi))
1396 return 0;
1397
1398 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1399
1400 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1401
1402 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1403
1404 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n",
1405 cinfo->clkdco, cinfo->m);
1406
1407 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1408 dss_get_clk_source_name(dsi_module == 0 ?
1409 DSS_CLK_SRC_PLL1_1 :
1410 DSS_CLK_SRC_PLL2_1),
1411 cinfo->clkout[HSDIV_DISPC],
1412 cinfo->mX[HSDIV_DISPC],
1413 dispc_clk_src == DSS_CLK_SRC_FCK ?
1414 "off" : "on");
1415
1416 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1417 dss_get_clk_source_name(dsi_module == 0 ?
1418 DSS_CLK_SRC_PLL1_2 :
1419 DSS_CLK_SRC_PLL2_2),
1420 cinfo->clkout[HSDIV_DSI],
1421 cinfo->mX[HSDIV_DSI],
1422 dsi_clk_src == DSS_CLK_SRC_FCK ?
1423 "off" : "on");
1424
1425 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1426
1427 seq_printf(s, "dsi fclk source = %s\n",
1428 dss_get_clk_source_name(dsi_clk_src));
1429
1430 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi));
1431
1432 seq_printf(s, "DDR_CLK\t\t%lu\n",
1433 cinfo->clkdco / 4);
1434
1435 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi));
1436
1437 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1438
1439 dsi_runtime_put(dsi);
1440
1441 return 0;
1442 }
1443
1444 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1445 static int dsi_dump_dsi_irqs(struct seq_file *s, void *p)
1446 {
1447 struct dsi_data *dsi = s->private;
1448 unsigned long flags;
1449 struct dsi_irq_stats stats;
1450
1451 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1452
1453 stats = dsi->irq_stats;
1454 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1455 dsi->irq_stats.last_reset = jiffies;
1456
1457 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1458
1459 seq_printf(s, "period %u ms\n",
1460 jiffies_to_msecs(jiffies - stats.last_reset));
1461
1462 seq_printf(s, "irqs %d\n", stats.irq_count);
1463 #define PIS(x) \
1464 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1465
1466 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1467 PIS(VC0);
1468 PIS(VC1);
1469 PIS(VC2);
1470 PIS(VC3);
1471 PIS(WAKEUP);
1472 PIS(RESYNC);
1473 PIS(PLL_LOCK);
1474 PIS(PLL_UNLOCK);
1475 PIS(PLL_RECALL);
1476 PIS(COMPLEXIO_ERR);
1477 PIS(HS_TX_TIMEOUT);
1478 PIS(LP_RX_TIMEOUT);
1479 PIS(TE_TRIGGER);
1480 PIS(ACK_TRIGGER);
1481 PIS(SYNC_LOST);
1482 PIS(LDO_POWER_GOOD);
1483 PIS(TA_TIMEOUT);
1484 #undef PIS
1485
1486 #define PIS(x) \
1487 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1488 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1489 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1490 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1491 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1492
1493 seq_printf(s, "-- VC interrupts --\n");
1494 PIS(CS);
1495 PIS(ECC_CORR);
1496 PIS(PACKET_SENT);
1497 PIS(FIFO_TX_OVF);
1498 PIS(FIFO_RX_OVF);
1499 PIS(BTA);
1500 PIS(ECC_NO_CORR);
1501 PIS(FIFO_TX_UDF);
1502 PIS(PP_BUSY_CHANGE);
1503 #undef PIS
1504
1505 #define PIS(x) \
1506 seq_printf(s, "%-20s %10d\n", #x, \
1507 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1508
1509 seq_printf(s, "-- CIO interrupts --\n");
1510 PIS(ERRSYNCESC1);
1511 PIS(ERRSYNCESC2);
1512 PIS(ERRSYNCESC3);
1513 PIS(ERRESC1);
1514 PIS(ERRESC2);
1515 PIS(ERRESC3);
1516 PIS(ERRCONTROL1);
1517 PIS(ERRCONTROL2);
1518 PIS(ERRCONTROL3);
1519 PIS(STATEULPS1);
1520 PIS(STATEULPS2);
1521 PIS(STATEULPS3);
1522 PIS(ERRCONTENTIONLP0_1);
1523 PIS(ERRCONTENTIONLP1_1);
1524 PIS(ERRCONTENTIONLP0_2);
1525 PIS(ERRCONTENTIONLP1_2);
1526 PIS(ERRCONTENTIONLP0_3);
1527 PIS(ERRCONTENTIONLP1_3);
1528 PIS(ULPSACTIVENOT_ALL0);
1529 PIS(ULPSACTIVENOT_ALL1);
1530 #undef PIS
1531
1532 return 0;
1533 }
1534 #endif
1535
1536 static int dsi_dump_dsi_regs(struct seq_file *s, void *p)
1537 {
1538 struct dsi_data *dsi = s->private;
1539
1540 if (dsi_runtime_get(dsi))
1541 return 0;
1542 dsi_enable_scp_clk(dsi);
1543
1544 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r))
1545 DUMPREG(DSI_REVISION);
1546 DUMPREG(DSI_SYSCONFIG);
1547 DUMPREG(DSI_SYSSTATUS);
1548 DUMPREG(DSI_IRQSTATUS);
1549 DUMPREG(DSI_IRQENABLE);
1550 DUMPREG(DSI_CTRL);
1551 DUMPREG(DSI_COMPLEXIO_CFG1);
1552 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1553 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1554 DUMPREG(DSI_CLK_CTRL);
1555 DUMPREG(DSI_TIMING1);
1556 DUMPREG(DSI_TIMING2);
1557 DUMPREG(DSI_VM_TIMING1);
1558 DUMPREG(DSI_VM_TIMING2);
1559 DUMPREG(DSI_VM_TIMING3);
1560 DUMPREG(DSI_CLK_TIMING);
1561 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1562 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1563 DUMPREG(DSI_COMPLEXIO_CFG2);
1564 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1565 DUMPREG(DSI_VM_TIMING4);
1566 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1567 DUMPREG(DSI_VM_TIMING5);
1568 DUMPREG(DSI_VM_TIMING6);
1569 DUMPREG(DSI_VM_TIMING7);
1570 DUMPREG(DSI_STOPCLK_TIMING);
1571
1572 DUMPREG(DSI_VC_CTRL(0));
1573 DUMPREG(DSI_VC_TE(0));
1574 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1575 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1576 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1577 DUMPREG(DSI_VC_IRQSTATUS(0));
1578 DUMPREG(DSI_VC_IRQENABLE(0));
1579
1580 DUMPREG(DSI_VC_CTRL(1));
1581 DUMPREG(DSI_VC_TE(1));
1582 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1583 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1584 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1585 DUMPREG(DSI_VC_IRQSTATUS(1));
1586 DUMPREG(DSI_VC_IRQENABLE(1));
1587
1588 DUMPREG(DSI_VC_CTRL(2));
1589 DUMPREG(DSI_VC_TE(2));
1590 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1591 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1592 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1593 DUMPREG(DSI_VC_IRQSTATUS(2));
1594 DUMPREG(DSI_VC_IRQENABLE(2));
1595
1596 DUMPREG(DSI_VC_CTRL(3));
1597 DUMPREG(DSI_VC_TE(3));
1598 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1599 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1600 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1601 DUMPREG(DSI_VC_IRQSTATUS(3));
1602 DUMPREG(DSI_VC_IRQENABLE(3));
1603
1604 DUMPREG(DSI_DSIPHY_CFG0);
1605 DUMPREG(DSI_DSIPHY_CFG1);
1606 DUMPREG(DSI_DSIPHY_CFG2);
1607 DUMPREG(DSI_DSIPHY_CFG5);
1608
1609 DUMPREG(DSI_PLL_CONTROL);
1610 DUMPREG(DSI_PLL_STATUS);
1611 DUMPREG(DSI_PLL_GO);
1612 DUMPREG(DSI_PLL_CONFIGURATION1);
1613 DUMPREG(DSI_PLL_CONFIGURATION2);
1614 #undef DUMPREG
1615
1616 dsi_disable_scp_clk(dsi);
1617 dsi_runtime_put(dsi);
1618
1619 return 0;
1620 }
1621
1622 enum dsi_cio_power_state {
1623 DSI_COMPLEXIO_POWER_OFF = 0x0,
1624 DSI_COMPLEXIO_POWER_ON = 0x1,
1625 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1626 };
1627
1628 static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state)
1629 {
1630 int t = 0;
1631
1632 /* PWR_CMD */
1633 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27);
1634
1635 /* PWR_STATUS */
1636 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1),
1637 26, 25) != state) {
1638 if (++t > 1000) {
1639 DSSERR("failed to set complexio power state to "
1640 "%d\n", state);
1641 return -ENODEV;
1642 }
1643 udelay(1);
1644 }
1645
1646 return 0;
1647 }
1648
1649 static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi)
1650 {
1651 int val;
1652
1653 /* line buffer on OMAP3 is 1024 x 24bits */
1654 /* XXX: for some reason using full buffer size causes
1655 * considerable TX slowdown with update sizes that fill the
1656 * whole buffer */
1657 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1658 return 1023 * 3;
1659
1660 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1661
1662 switch (val) {
1663 case 1:
1664 return 512 * 3; /* 512x24 bits */
1665 case 2:
1666 return 682 * 3; /* 682x24 bits */
1667 case 3:
1668 return 853 * 3; /* 853x24 bits */
1669 case 4:
1670 return 1024 * 3; /* 1024x24 bits */
1671 case 5:
1672 return 1194 * 3; /* 1194x24 bits */
1673 case 6:
1674 return 1365 * 3; /* 1365x24 bits */
1675 case 7:
1676 return 1920 * 3; /* 1920x24 bits */
1677 default:
1678 BUG();
1679 return 0;
1680 }
1681 }
1682
1683 static int dsi_set_lane_config(struct dsi_data *dsi)
1684 {
1685 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1686 static const enum dsi_lane_function functions[] = {
1687 DSI_LANE_CLK,
1688 DSI_LANE_DATA1,
1689 DSI_LANE_DATA2,
1690 DSI_LANE_DATA3,
1691 DSI_LANE_DATA4,
1692 };
1693 u32 r;
1694 int i;
1695
1696 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1);
1697
1698 for (i = 0; i < dsi->num_lanes_used; ++i) {
1699 unsigned int offset = offsets[i];
1700 unsigned int polarity, lane_number;
1701 unsigned int t;
1702
1703 for (t = 0; t < dsi->num_lanes_supported; ++t)
1704 if (dsi->lanes[t].function == functions[i])
1705 break;
1706
1707 if (t == dsi->num_lanes_supported)
1708 return -EINVAL;
1709
1710 lane_number = t;
1711 polarity = dsi->lanes[t].polarity;
1712
1713 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1714 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1715 }
1716
1717 /* clear the unused lanes */
1718 for (; i < dsi->num_lanes_supported; ++i) {
1719 unsigned int offset = offsets[i];
1720
1721 r = FLD_MOD(r, 0, offset + 2, offset);
1722 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1723 }
1724
1725 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r);
1726
1727 return 0;
1728 }
1729
1730 static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns)
1731 {
1732 /* convert time in ns to ddr ticks, rounding up */
1733 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1734
1735 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1736 }
1737
1738 static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr)
1739 {
1740 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1741
1742 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1743 }
1744
1745 static void dsi_cio_timings(struct dsi_data *dsi)
1746 {
1747 u32 r;
1748 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1749 u32 tlpx_half, tclk_trail, tclk_zero;
1750 u32 tclk_prepare;
1751
1752 /* calculate timings */
1753
1754 /* 1 * DDR_CLK = 2 * UI */
1755
1756 /* min 40ns + 4*UI max 85ns + 6*UI */
1757 ths_prepare = ns2ddr(dsi, 70) + 2;
1758
1759 /* min 145ns + 10*UI */
1760 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2;
1761
1762 /* min max(8*UI, 60ns+4*UI) */
1763 ths_trail = ns2ddr(dsi, 60) + 5;
1764
1765 /* min 100ns */
1766 ths_exit = ns2ddr(dsi, 145);
1767
1768 /* tlpx min 50n */
1769 tlpx_half = ns2ddr(dsi, 25);
1770
1771 /* min 60ns */
1772 tclk_trail = ns2ddr(dsi, 60) + 2;
1773
1774 /* min 38ns, max 95ns */
1775 tclk_prepare = ns2ddr(dsi, 65);
1776
1777 /* min tclk-prepare + tclk-zero = 300ns */
1778 tclk_zero = ns2ddr(dsi, 260);
1779
1780 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1781 ths_prepare, ddr2ns(dsi, ths_prepare),
1782 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero));
1783 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1784 ths_trail, ddr2ns(dsi, ths_trail),
1785 ths_exit, ddr2ns(dsi, ths_exit));
1786
1787 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1788 "tclk_zero %u (%uns)\n",
1789 tlpx_half, ddr2ns(dsi, tlpx_half),
1790 tclk_trail, ddr2ns(dsi, tclk_trail),
1791 tclk_zero, ddr2ns(dsi, tclk_zero));
1792 DSSDBG("tclk_prepare %u (%uns)\n",
1793 tclk_prepare, ddr2ns(dsi, tclk_prepare));
1794
1795 /* program timings */
1796
1797 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
1798 r = FLD_MOD(r, ths_prepare, 31, 24);
1799 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1800 r = FLD_MOD(r, ths_trail, 15, 8);
1801 r = FLD_MOD(r, ths_exit, 7, 0);
1802 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r);
1803
1804 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
1805 r = FLD_MOD(r, tlpx_half, 20, 16);
1806 r = FLD_MOD(r, tclk_trail, 15, 8);
1807 r = FLD_MOD(r, tclk_zero, 7, 0);
1808
1809 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1810 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
1811 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
1812 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
1813 }
1814
1815 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r);
1816
1817 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
1818 r = FLD_MOD(r, tclk_prepare, 7, 0);
1819 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r);
1820 }
1821
1822 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1823 static void dsi_cio_enable_lane_override(struct dsi_data *dsi,
1824 unsigned int mask_p,
1825 unsigned int mask_n)
1826 {
1827 int i;
1828 u32 l;
1829 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1830
1831 l = 0;
1832
1833 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1834 unsigned int p = dsi->lanes[i].polarity;
1835
1836 if (mask_p & (1 << i))
1837 l |= 1 << (i * 2 + (p ? 0 : 1));
1838
1839 if (mask_n & (1 << i))
1840 l |= 1 << (i * 2 + (p ? 1 : 0));
1841 }
1842
1843 /*
1844 * Bits in REGLPTXSCPDAT4TO0DXDY:
1845 * 17: DY0 18: DX0
1846 * 19: DY1 20: DX1
1847 * 21: DY2 22: DX2
1848 * 23: DY3 24: DX3
1849 * 25: DY4 26: DX4
1850 */
1851
1852 /* Set the lane override configuration */
1853
1854 /* REGLPTXSCPDAT4TO0DXDY */
1855 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1856
1857 /* Enable lane override */
1858
1859 /* ENLPTXSCPDAT */
1860 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27);
1861 }
1862
1863 static void dsi_cio_disable_lane_override(struct dsi_data *dsi)
1864 {
1865 /* Disable lane override */
1866 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1867 /* Reset the lane override configuration */
1868 /* REGLPTXSCPDAT4TO0DXDY */
1869 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17);
1870 }
1871
1872 static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi)
1873 {
1874 int t, i;
1875 bool in_use[DSI_MAX_NR_LANES];
1876 static const u8 offsets_old[] = { 28, 27, 26 };
1877 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
1878 const u8 *offsets;
1879
1880 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
1881 offsets = offsets_old;
1882 else
1883 offsets = offsets_new;
1884
1885 for (i = 0; i < dsi->num_lanes_supported; ++i)
1886 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
1887
1888 t = 100000;
1889 while (true) {
1890 u32 l;
1891 int ok;
1892
1893 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1894
1895 ok = 0;
1896 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1897 if (!in_use[i] || (l & (1 << offsets[i])))
1898 ok++;
1899 }
1900
1901 if (ok == dsi->num_lanes_supported)
1902 break;
1903
1904 if (--t == 0) {
1905 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1906 if (!in_use[i] || (l & (1 << offsets[i])))
1907 continue;
1908
1909 DSSERR("CIO TXCLKESC%d domain not coming " \
1910 "out of reset\n", i);
1911 }
1912 return -EIO;
1913 }
1914 }
1915
1916 return 0;
1917 }
1918
1919 /* return bitmask of enabled lanes, lane0 being the lsb */
1920 static unsigned int dsi_get_lane_mask(struct dsi_data *dsi)
1921 {
1922 unsigned int mask = 0;
1923 int i;
1924
1925 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1926 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
1927 mask |= 1 << i;
1928 }
1929
1930 return mask;
1931 }
1932
1933 /* OMAP4 CONTROL_DSIPHY */
1934 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
1935
1936 #define OMAP4_DSI2_LANEENABLE_SHIFT 29
1937 #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
1938 #define OMAP4_DSI1_LANEENABLE_SHIFT 24
1939 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
1940 #define OMAP4_DSI1_PIPD_SHIFT 19
1941 #define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
1942 #define OMAP4_DSI2_PIPD_SHIFT 14
1943 #define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
1944
1945 static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1946 {
1947 u32 enable_mask, enable_shift;
1948 u32 pipd_mask, pipd_shift;
1949
1950 if (dsi->module_id == 0) {
1951 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
1952 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
1953 pipd_mask = OMAP4_DSI1_PIPD_MASK;
1954 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
1955 } else if (dsi->module_id == 1) {
1956 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
1957 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
1958 pipd_mask = OMAP4_DSI2_PIPD_MASK;
1959 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
1960 } else {
1961 return -ENODEV;
1962 }
1963
1964 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET,
1965 enable_mask | pipd_mask,
1966 (lanes << enable_shift) | (lanes << pipd_shift));
1967 }
1968
1969 /* OMAP5 CONTROL_DSIPHY */
1970
1971 #define OMAP5_DSIPHY_SYSCON_OFFSET 0x74
1972
1973 #define OMAP5_DSI1_LANEENABLE_SHIFT 24
1974 #define OMAP5_DSI2_LANEENABLE_SHIFT 19
1975 #define OMAP5_DSI_LANEENABLE_MASK 0x1f
1976
1977 static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1978 {
1979 u32 enable_shift;
1980
1981 if (dsi->module_id == 0)
1982 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT;
1983 else if (dsi->module_id == 1)
1984 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT;
1985 else
1986 return -ENODEV;
1987
1988 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET,
1989 OMAP5_DSI_LANEENABLE_MASK << enable_shift,
1990 lanes << enable_shift);
1991 }
1992
1993 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask)
1994 {
1995 if (dsi->data->model == DSI_MODEL_OMAP4)
1996 return dsi_omap4_mux_pads(dsi, lane_mask);
1997 if (dsi->data->model == DSI_MODEL_OMAP5)
1998 return dsi_omap5_mux_pads(dsi, lane_mask);
1999 return 0;
2000 }
2001
2002 static void dsi_disable_pads(struct dsi_data *dsi)
2003 {
2004 if (dsi->data->model == DSI_MODEL_OMAP4)
2005 dsi_omap4_mux_pads(dsi, 0);
2006 else if (dsi->data->model == DSI_MODEL_OMAP5)
2007 dsi_omap5_mux_pads(dsi, 0);
2008 }
2009
2010 static int dsi_cio_init(struct dsi_data *dsi)
2011 {
2012 int r;
2013 u32 l;
2014
2015 DSSDBG("DSI CIO init starts");
2016
2017 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi));
2018 if (r)
2019 return r;
2020
2021 dsi_enable_scp_clk(dsi);
2022
2023 /* A dummy read using the SCP interface to any DSIPHY register is
2024 * required after DSIPHY reset to complete the reset of the DSI complex
2025 * I/O. */
2026 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
2027
2028 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) {
2029 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2030 r = -EIO;
2031 goto err_scp_clk_dom;
2032 }
2033
2034 r = dsi_set_lane_config(dsi);
2035 if (r)
2036 goto err_scp_clk_dom;
2037
2038 /* set TX STOP MODE timer to maximum for this operation */
2039 l = dsi_read_reg(dsi, DSI_TIMING1);
2040 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2041 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2042 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2043 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2044 dsi_write_reg(dsi, DSI_TIMING1, l);
2045
2046 if (dsi->ulps_enabled) {
2047 unsigned int mask_p;
2048 int i;
2049
2050 DSSDBG("manual ulps exit\n");
2051
2052 /* ULPS is exited by Mark-1 state for 1ms, followed by
2053 * stop state. DSS HW cannot do this via the normal
2054 * ULPS exit sequence, as after reset the DSS HW thinks
2055 * that we are not in ULPS mode, and refuses to send the
2056 * sequence. So we need to send the ULPS exit sequence
2057 * manually by setting positive lines high and negative lines
2058 * low for 1ms.
2059 */
2060
2061 mask_p = 0;
2062
2063 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2064 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2065 continue;
2066 mask_p |= 1 << i;
2067 }
2068
2069 dsi_cio_enable_lane_override(dsi, mask_p, 0);
2070 }
2071
2072 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON);
2073 if (r)
2074 goto err_cio_pwr;
2075
2076 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) {
2077 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2078 r = -ENODEV;
2079 goto err_cio_pwr_dom;
2080 }
2081
2082 dsi_if_enable(dsi, true);
2083 dsi_if_enable(dsi, false);
2084 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2085
2086 r = dsi_cio_wait_tx_clk_esc_reset(dsi);
2087 if (r)
2088 goto err_tx_clk_esc_rst;
2089
2090 if (dsi->ulps_enabled) {
2091 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2092 ktime_t wait = ns_to_ktime(1000 * 1000);
2093 set_current_state(TASK_UNINTERRUPTIBLE);
2094 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2095
2096 /* Disable the override. The lanes should be set to Mark-11
2097 * state by the HW */
2098 dsi_cio_disable_lane_override(dsi);
2099 }
2100
2101 /* FORCE_TX_STOP_MODE_IO */
2102 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15);
2103
2104 dsi_cio_timings(dsi);
2105
2106 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2107 /* DDR_CLK_ALWAYS_ON */
2108 REG_FLD_MOD(dsi, DSI_CLK_CTRL,
2109 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2110 }
2111
2112 dsi->ulps_enabled = false;
2113
2114 DSSDBG("CIO init done\n");
2115
2116 return 0;
2117
2118 err_tx_clk_esc_rst:
2119 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2120 err_cio_pwr_dom:
2121 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2122 err_cio_pwr:
2123 if (dsi->ulps_enabled)
2124 dsi_cio_disable_lane_override(dsi);
2125 err_scp_clk_dom:
2126 dsi_disable_scp_clk(dsi);
2127 dsi_disable_pads(dsi);
2128 return r;
2129 }
2130
2131 static void dsi_cio_uninit(struct dsi_data *dsi)
2132 {
2133 /* DDR_CLK_ALWAYS_ON */
2134 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
2135
2136 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2137 dsi_disable_scp_clk(dsi);
2138 dsi_disable_pads(dsi);
2139 }
2140
2141 static void dsi_config_tx_fifo(struct dsi_data *dsi,
2142 enum fifo_size size1, enum fifo_size size2,
2143 enum fifo_size size3, enum fifo_size size4)
2144 {
2145 u32 r = 0;
2146 int add = 0;
2147 int i;
2148
2149 dsi->vc[0].tx_fifo_size = size1;
2150 dsi->vc[1].tx_fifo_size = size2;
2151 dsi->vc[2].tx_fifo_size = size3;
2152 dsi->vc[3].tx_fifo_size = size4;
2153
2154 for (i = 0; i < 4; i++) {
2155 u8 v;
2156 int size = dsi->vc[i].tx_fifo_size;
2157
2158 if (add + size > 4) {
2159 DSSERR("Illegal FIFO configuration\n");
2160 BUG();
2161 return;
2162 }
2163
2164 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2165 r |= v << (8 * i);
2166 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2167 add += size;
2168 }
2169
2170 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r);
2171 }
2172
2173 static void dsi_config_rx_fifo(struct dsi_data *dsi,
2174 enum fifo_size size1, enum fifo_size size2,
2175 enum fifo_size size3, enum fifo_size size4)
2176 {
2177 u32 r = 0;
2178 int add = 0;
2179 int i;
2180
2181 dsi->vc[0].rx_fifo_size = size1;
2182 dsi->vc[1].rx_fifo_size = size2;
2183 dsi->vc[2].rx_fifo_size = size3;
2184 dsi->vc[3].rx_fifo_size = size4;
2185
2186 for (i = 0; i < 4; i++) {
2187 u8 v;
2188 int size = dsi->vc[i].rx_fifo_size;
2189
2190 if (add + size > 4) {
2191 DSSERR("Illegal FIFO configuration\n");
2192 BUG();
2193 return;
2194 }
2195
2196 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2197 r |= v << (8 * i);
2198 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2199 add += size;
2200 }
2201
2202 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r);
2203 }
2204
2205 static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi)
2206 {
2207 u32 r;
2208
2209 r = dsi_read_reg(dsi, DSI_TIMING1);
2210 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2211 dsi_write_reg(dsi, DSI_TIMING1, r);
2212
2213 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) {
2214 DSSERR("TX_STOP bit not going down\n");
2215 return -EIO;
2216 }
2217
2218 return 0;
2219 }
2220
2221 static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel)
2222 {
2223 return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0);
2224 }
2225
2226 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2227 {
2228 struct dsi_packet_sent_handler_data *vp_data =
2229 (struct dsi_packet_sent_handler_data *) data;
2230 struct dsi_data *dsi = vp_data->dsi;
2231 const int channel = dsi->update_channel;
2232 u8 bit = dsi->te_enabled ? 30 : 31;
2233
2234 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0)
2235 complete(vp_data->completion);
2236 }
2237
2238 static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel)
2239 {
2240 DECLARE_COMPLETION_ONSTACK(completion);
2241 struct dsi_packet_sent_handler_data vp_data = {
2242 .dsi = dsi,
2243 .completion = &completion
2244 };
2245 int r = 0;
2246 u8 bit;
2247
2248 bit = dsi->te_enabled ? 30 : 31;
2249
2250 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2251 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2252 if (r)
2253 goto err0;
2254
2255 /* Wait for completion only if TE_EN/TE_START is still set */
2256 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) {
2257 if (wait_for_completion_timeout(&completion,
2258 msecs_to_jiffies(10)) == 0) {
2259 DSSERR("Failed to complete previous frame transfer\n");
2260 r = -EIO;
2261 goto err1;
2262 }
2263 }
2264
2265 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2266 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2267
2268 return 0;
2269 err1:
2270 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2271 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2272 err0:
2273 return r;
2274 }
2275
2276 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2277 {
2278 struct dsi_packet_sent_handler_data *l4_data =
2279 (struct dsi_packet_sent_handler_data *) data;
2280 struct dsi_data *dsi = l4_data->dsi;
2281 const int channel = dsi->update_channel;
2282
2283 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0)
2284 complete(l4_data->completion);
2285 }
2286
2287 static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel)
2288 {
2289 DECLARE_COMPLETION_ONSTACK(completion);
2290 struct dsi_packet_sent_handler_data l4_data = {
2291 .dsi = dsi,
2292 .completion = &completion
2293 };
2294 int r = 0;
2295
2296 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2297 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2298 if (r)
2299 goto err0;
2300
2301 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2302 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) {
2303 if (wait_for_completion_timeout(&completion,
2304 msecs_to_jiffies(10)) == 0) {
2305 DSSERR("Failed to complete previous l4 transfer\n");
2306 r = -EIO;
2307 goto err1;
2308 }
2309 }
2310
2311 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2312 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2313
2314 return 0;
2315 err1:
2316 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2317 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2318 err0:
2319 return r;
2320 }
2321
2322 static int dsi_sync_vc(struct dsi_data *dsi, int channel)
2323 {
2324 WARN_ON(!dsi_bus_is_locked(dsi));
2325
2326 WARN_ON(in_interrupt());
2327
2328 if (!dsi_vc_is_enabled(dsi, channel))
2329 return 0;
2330
2331 switch (dsi->vc[channel].source) {
2332 case DSI_VC_SOURCE_VP:
2333 return dsi_sync_vc_vp(dsi, channel);
2334 case DSI_VC_SOURCE_L4:
2335 return dsi_sync_vc_l4(dsi, channel);
2336 default:
2337 BUG();
2338 return -EINVAL;
2339 }
2340 }
2341
2342 static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable)
2343 {
2344 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2345 channel, enable);
2346
2347 enable = enable ? 1 : 0;
2348
2349 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0);
2350
2351 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) {
2352 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2353 return -EIO;
2354 }
2355
2356 return 0;
2357 }
2358
2359 static void dsi_vc_initial_config(struct dsi_data *dsi, int channel)
2360 {
2361 u32 r;
2362
2363 DSSDBG("Initial config of virtual channel %d", channel);
2364
2365 r = dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2366
2367 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2368 DSSERR("VC(%d) busy when trying to configure it!\n",
2369 channel);
2370
2371 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2372 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2373 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2374 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2375 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2376 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2377 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2378 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
2379 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2380
2381 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2382 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2383
2384 dsi_write_reg(dsi, DSI_VC_CTRL(channel), r);
2385
2386 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2387 }
2388
2389 static int dsi_vc_config_source(struct dsi_data *dsi, int channel,
2390 enum dsi_vc_source source)
2391 {
2392 if (dsi->vc[channel].source == source)
2393 return 0;
2394
2395 DSSDBG("Source config of virtual channel %d", channel);
2396
2397 dsi_sync_vc(dsi, channel);
2398
2399 dsi_vc_enable(dsi, channel, 0);
2400
2401 /* VC_BUSY */
2402 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) {
2403 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2404 return -EIO;
2405 }
2406
2407 /* SOURCE, 0 = L4, 1 = video port */
2408 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1);
2409
2410 /* DCS_CMD_ENABLE */
2411 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) {
2412 bool enable = source == DSI_VC_SOURCE_VP;
2413 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30);
2414 }
2415
2416 dsi_vc_enable(dsi, channel, 1);
2417
2418 dsi->vc[channel].source = source;
2419
2420 return 0;
2421 }
2422
2423 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2424 bool enable)
2425 {
2426 struct dsi_data *dsi = to_dsi_data(dssdev);
2427
2428 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2429
2430 WARN_ON(!dsi_bus_is_locked(dsi));
2431
2432 dsi_vc_enable(dsi, channel, 0);
2433 dsi_if_enable(dsi, 0);
2434
2435 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9);
2436
2437 dsi_vc_enable(dsi, channel, 1);
2438 dsi_if_enable(dsi, 1);
2439
2440 dsi_force_tx_stop_mode_io(dsi);
2441
2442 /* start the DDR clock by sending a NULL packet */
2443 if (dsi->vm_timings.ddr_clk_always_on && enable)
2444 dsi_vc_send_null(dsi, channel);
2445 }
2446
2447 static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel)
2448 {
2449 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2450 u32 val;
2451 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2452 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2453 (val >> 0) & 0xff,
2454 (val >> 8) & 0xff,
2455 (val >> 16) & 0xff,
2456 (val >> 24) & 0xff);
2457 }
2458 }
2459
2460 static void dsi_show_rx_ack_with_err(u16 err)
2461 {
2462 DSSERR("\tACK with ERROR (%#x):\n", err);
2463 if (err & (1 << 0))
2464 DSSERR("\t\tSoT Error\n");
2465 if (err & (1 << 1))
2466 DSSERR("\t\tSoT Sync Error\n");
2467 if (err & (1 << 2))
2468 DSSERR("\t\tEoT Sync Error\n");
2469 if (err & (1 << 3))
2470 DSSERR("\t\tEscape Mode Entry Command Error\n");
2471 if (err & (1 << 4))
2472 DSSERR("\t\tLP Transmit Sync Error\n");
2473 if (err & (1 << 5))
2474 DSSERR("\t\tHS Receive Timeout Error\n");
2475 if (err & (1 << 6))
2476 DSSERR("\t\tFalse Control Error\n");
2477 if (err & (1 << 7))
2478 DSSERR("\t\t(reserved7)\n");
2479 if (err & (1 << 8))
2480 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2481 if (err & (1 << 9))
2482 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2483 if (err & (1 << 10))
2484 DSSERR("\t\tChecksum Error\n");
2485 if (err & (1 << 11))
2486 DSSERR("\t\tData type not recognized\n");
2487 if (err & (1 << 12))
2488 DSSERR("\t\tInvalid VC ID\n");
2489 if (err & (1 << 13))
2490 DSSERR("\t\tInvalid Transmission Length\n");
2491 if (err & (1 << 14))
2492 DSSERR("\t\t(reserved14)\n");
2493 if (err & (1 << 15))
2494 DSSERR("\t\tDSI Protocol Violation\n");
2495 }
2496
2497 static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel)
2498 {
2499 /* RX_FIFO_NOT_EMPTY */
2500 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2501 u32 val;
2502 u8 dt;
2503 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2504 DSSERR("\trawval %#08x\n", val);
2505 dt = FLD_GET(val, 5, 0);
2506 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2507 u16 err = FLD_GET(val, 23, 8);
2508 dsi_show_rx_ack_with_err(err);
2509 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2510 DSSERR("\tDCS short response, 1 byte: %#x\n",
2511 FLD_GET(val, 23, 8));
2512 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2513 DSSERR("\tDCS short response, 2 byte: %#x\n",
2514 FLD_GET(val, 23, 8));
2515 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2516 DSSERR("\tDCS long response, len %d\n",
2517 FLD_GET(val, 23, 8));
2518 dsi_vc_flush_long_data(dsi, channel);
2519 } else {
2520 DSSERR("\tunknown datatype 0x%02x\n", dt);
2521 }
2522 }
2523 return 0;
2524 }
2525
2526 static int dsi_vc_send_bta(struct dsi_data *dsi, int channel)
2527 {
2528 if (dsi->debug_write || dsi->debug_read)
2529 DSSDBG("dsi_vc_send_bta %d\n", channel);
2530
2531 WARN_ON(!dsi_bus_is_locked(dsi));
2532
2533 /* RX_FIFO_NOT_EMPTY */
2534 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2535 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2536 dsi_vc_flush_receive_data(dsi, channel);
2537 }
2538
2539 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2540
2541 /* flush posted write */
2542 dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2543
2544 return 0;
2545 }
2546
2547 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2548 {
2549 struct dsi_data *dsi = to_dsi_data(dssdev);
2550 DECLARE_COMPLETION_ONSTACK(completion);
2551 int r = 0;
2552 u32 err;
2553
2554 r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler,
2555 &completion, DSI_VC_IRQ_BTA);
2556 if (r)
2557 goto err0;
2558
2559 r = dsi_register_isr(dsi, dsi_completion_handler, &completion,
2560 DSI_IRQ_ERROR_MASK);
2561 if (r)
2562 goto err1;
2563
2564 r = dsi_vc_send_bta(dsi, channel);
2565 if (r)
2566 goto err2;
2567
2568 if (wait_for_completion_timeout(&completion,
2569 msecs_to_jiffies(500)) == 0) {
2570 DSSERR("Failed to receive BTA\n");
2571 r = -EIO;
2572 goto err2;
2573 }
2574
2575 err = dsi_get_errors(dsi);
2576 if (err) {
2577 DSSERR("Error while sending BTA: %x\n", err);
2578 r = -EIO;
2579 goto err2;
2580 }
2581 err2:
2582 dsi_unregister_isr(dsi, dsi_completion_handler, &completion,
2583 DSI_IRQ_ERROR_MASK);
2584 err1:
2585 dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler,
2586 &completion, DSI_VC_IRQ_BTA);
2587 err0:
2588 return r;
2589 }
2590
2591 static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel,
2592 u8 data_type, u16 len, u8 ecc)
2593 {
2594 u32 val;
2595 u8 data_id;
2596
2597 WARN_ON(!dsi_bus_is_locked(dsi));
2598
2599 data_id = data_type | dsi->vc[channel].vc_id << 6;
2600
2601 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2602 FLD_VAL(ecc, 31, 24);
2603
2604 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val);
2605 }
2606
2607 static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel,
2608 u8 b1, u8 b2, u8 b3, u8 b4)
2609 {
2610 u32 val;
2611
2612 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2613
2614 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2615 b1, b2, b3, b4, val); */
2616
2617 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2618 }
2619
2620 static int dsi_vc_send_long(struct dsi_data *dsi, int channel, u8 data_type,
2621 u8 *data, u16 len, u8 ecc)
2622 {
2623 /*u32 val; */
2624 int i;
2625 u8 *p;
2626 int r = 0;
2627 u8 b1, b2, b3, b4;
2628
2629 if (dsi->debug_write)
2630 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2631
2632 /* len + header */
2633 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2634 DSSERR("unable to send long packet: packet too long.\n");
2635 return -EINVAL;
2636 }
2637
2638 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2639
2640 dsi_vc_write_long_header(dsi, channel, data_type, len, ecc);
2641
2642 p = data;
2643 for (i = 0; i < len >> 2; i++) {
2644 if (dsi->debug_write)
2645 DSSDBG("\tsending full packet %d\n", i);
2646
2647 b1 = *p++;
2648 b2 = *p++;
2649 b3 = *p++;
2650 b4 = *p++;
2651
2652 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, b4);
2653 }
2654
2655 i = len % 4;
2656 if (i) {
2657 b1 = 0; b2 = 0; b3 = 0;
2658
2659 if (dsi->debug_write)
2660 DSSDBG("\tsending remainder bytes %d\n", i);
2661
2662 switch (i) {
2663 case 3:
2664 b1 = *p++;
2665 b2 = *p++;
2666 b3 = *p++;
2667 break;
2668 case 2:
2669 b1 = *p++;
2670 b2 = *p++;
2671 break;
2672 case 1:
2673 b1 = *p++;
2674 break;
2675 }
2676
2677 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, 0);
2678 }
2679
2680 return r;
2681 }
2682
2683 static int dsi_vc_send_short(struct dsi_data *dsi, int channel, u8 data_type,
2684 u16 data, u8 ecc)
2685 {
2686 u32 r;
2687 u8 data_id;
2688
2689 WARN_ON(!dsi_bus_is_locked(dsi));
2690
2691 if (dsi->debug_write)
2692 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2693 channel,
2694 data_type, data & 0xff, (data >> 8) & 0xff);
2695
2696 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2697
2698 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(channel)), 16, 16)) {
2699 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2700 return -EINVAL;
2701 }
2702
2703 data_id = data_type | dsi->vc[channel].vc_id << 6;
2704
2705 r = (data_id << 0) | (data << 8) | (ecc << 24);
2706
2707 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2708
2709 return 0;
2710 }
2711
2712 static int dsi_vc_send_null(struct dsi_data *dsi, int channel)
2713 {
2714 return dsi_vc_send_long(dsi, channel, MIPI_DSI_NULL_PACKET, NULL, 0, 0);
2715 }
2716
2717 static int dsi_vc_write_nosync_common(struct dsi_data *dsi, int channel,
2718 u8 *data, int len,
2719 enum dss_dsi_content_type type)
2720 {
2721 int r;
2722
2723 if (len == 0) {
2724 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2725 r = dsi_vc_send_short(dsi, channel,
2726 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2727 } else if (len == 1) {
2728 r = dsi_vc_send_short(dsi, channel,
2729 type == DSS_DSI_CONTENT_GENERIC ?
2730 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2731 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2732 } else if (len == 2) {
2733 r = dsi_vc_send_short(dsi, channel,
2734 type == DSS_DSI_CONTENT_GENERIC ?
2735 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2736 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2737 data[0] | (data[1] << 8), 0);
2738 } else {
2739 r = dsi_vc_send_long(dsi, channel,
2740 type == DSS_DSI_CONTENT_GENERIC ?
2741 MIPI_DSI_GENERIC_LONG_WRITE :
2742 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2743 }
2744
2745 return r;
2746 }
2747
2748 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2749 u8 *data, int len)
2750 {
2751 struct dsi_data *dsi = to_dsi_data(dssdev);
2752
2753 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2754 DSS_DSI_CONTENT_DCS);
2755 }
2756
2757 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2758 u8 *data, int len)
2759 {
2760 struct dsi_data *dsi = to_dsi_data(dssdev);
2761
2762 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2763 DSS_DSI_CONTENT_GENERIC);
2764 }
2765
2766 static int dsi_vc_write_common(struct omap_dss_device *dssdev,
2767 int channel, u8 *data, int len,
2768 enum dss_dsi_content_type type)
2769 {
2770 struct dsi_data *dsi = to_dsi_data(dssdev);
2771 int r;
2772
2773 r = dsi_vc_write_nosync_common(dsi, channel, data, len, type);
2774 if (r)
2775 goto err;
2776
2777 r = dsi_vc_send_bta_sync(dssdev, channel);
2778 if (r)
2779 goto err;
2780
2781 /* RX_FIFO_NOT_EMPTY */
2782 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2783 DSSERR("rx fifo not empty after write, dumping data:\n");
2784 dsi_vc_flush_receive_data(dsi, channel);
2785 r = -EIO;
2786 goto err;
2787 }
2788
2789 return 0;
2790 err:
2791 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2792 channel, data[0], len);
2793 return r;
2794 }
2795
2796 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2797 int len)
2798 {
2799 return dsi_vc_write_common(dssdev, channel, data, len,
2800 DSS_DSI_CONTENT_DCS);
2801 }
2802
2803 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2804 int len)
2805 {
2806 return dsi_vc_write_common(dssdev, channel, data, len,
2807 DSS_DSI_CONTENT_GENERIC);
2808 }
2809
2810 static int dsi_vc_dcs_send_read_request(struct dsi_data *dsi, int channel,
2811 u8 dcs_cmd)
2812 {
2813 int r;
2814
2815 if (dsi->debug_read)
2816 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2817 channel, dcs_cmd);
2818
2819 r = dsi_vc_send_short(dsi, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2820 if (r) {
2821 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2822 " failed\n", channel, dcs_cmd);
2823 return r;
2824 }
2825
2826 return 0;
2827 }
2828
2829 static int dsi_vc_generic_send_read_request(struct dsi_data *dsi, int channel,
2830 u8 *reqdata, int reqlen)
2831 {
2832 u16 data;
2833 u8 data_type;
2834 int r;
2835
2836 if (dsi->debug_read)
2837 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2838 channel, reqlen);
2839
2840 if (reqlen == 0) {
2841 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2842 data = 0;
2843 } else if (reqlen == 1) {
2844 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2845 data = reqdata[0];
2846 } else if (reqlen == 2) {
2847 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2848 data = reqdata[0] | (reqdata[1] << 8);
2849 } else {
2850 BUG();
2851 return -EINVAL;
2852 }
2853
2854 r = dsi_vc_send_short(dsi, channel, data_type, data, 0);
2855 if (r) {
2856 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2857 " failed\n", channel, reqlen);
2858 return r;
2859 }
2860
2861 return 0;
2862 }
2863
2864 static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf,
2865 int buflen, enum dss_dsi_content_type type)
2866 {
2867 u32 val;
2868 u8 dt;
2869 int r;
2870
2871 /* RX_FIFO_NOT_EMPTY */
2872 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) {
2873 DSSERR("RX fifo empty when trying to read.\n");
2874 r = -EIO;
2875 goto err;
2876 }
2877
2878 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2879 if (dsi->debug_read)
2880 DSSDBG("\theader: %08x\n", val);
2881 dt = FLD_GET(val, 5, 0);
2882 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2883 u16 err = FLD_GET(val, 23, 8);
2884 dsi_show_rx_ack_with_err(err);
2885 r = -EIO;
2886 goto err;
2887
2888 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2889 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2890 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2891 u8 data = FLD_GET(val, 15, 8);
2892 if (dsi->debug_read)
2893 DSSDBG("\t%s short response, 1 byte: %02x\n",
2894 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2895 "DCS", data);
2896
2897 if (buflen < 1) {
2898 r = -EIO;
2899 goto err;
2900 }
2901
2902 buf[0] = data;
2903
2904 return 1;
2905 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2906 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2907 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2908 u16 data = FLD_GET(val, 23, 8);
2909 if (dsi->debug_read)
2910 DSSDBG("\t%s short response, 2 byte: %04x\n",
2911 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2912 "DCS", data);
2913
2914 if (buflen < 2) {
2915 r = -EIO;
2916 goto err;
2917 }
2918
2919 buf[0] = data & 0xff;
2920 buf[1] = (data >> 8) & 0xff;
2921
2922 return 2;
2923 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2924 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
2925 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
2926 int w;
2927 int len = FLD_GET(val, 23, 8);
2928 if (dsi->debug_read)
2929 DSSDBG("\t%s long response, len %d\n",
2930 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2931 "DCS", len);
2932
2933 if (len > buflen) {
2934 r = -EIO;
2935 goto err;
2936 }
2937
2938 /* two byte checksum ends the packet, not included in len */
2939 for (w = 0; w < len + 2;) {
2940 int b;
2941 val = dsi_read_reg(dsi,
2942 DSI_VC_SHORT_PACKET_HEADER(channel));
2943 if (dsi->debug_read)
2944 DSSDBG("\t\t%02x %02x %02x %02x\n",
2945 (val >> 0) & 0xff,
2946 (val >> 8) & 0xff,
2947 (val >> 16) & 0xff,
2948 (val >> 24) & 0xff);
2949
2950 for (b = 0; b < 4; ++b) {
2951 if (w < len)
2952 buf[w] = (val >> (b * 8)) & 0xff;
2953 /* we discard the 2 byte checksum */
2954 ++w;
2955 }
2956 }
2957
2958 return len;
2959 } else {
2960 DSSERR("\tunknown datatype 0x%02x\n", dt);
2961 r = -EIO;
2962 goto err;
2963 }
2964
2965 err:
2966 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
2967 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
2968
2969 return r;
2970 }
2971
2972 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
2973 u8 *buf, int buflen)
2974 {
2975 struct dsi_data *dsi = to_dsi_data(dssdev);
2976 int r;
2977
2978 r = dsi_vc_dcs_send_read_request(dsi, channel, dcs_cmd);
2979 if (r)
2980 goto err;
2981
2982 r = dsi_vc_send_bta_sync(dssdev, channel);
2983 if (r)
2984 goto err;
2985
2986 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
2987 DSS_DSI_CONTENT_DCS);
2988 if (r < 0)
2989 goto err;
2990
2991 if (r != buflen) {
2992 r = -EIO;
2993 goto err;
2994 }
2995
2996 return 0;
2997 err:
2998 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
2999 return r;
3000 }
3001
3002 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3003 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3004 {
3005 struct dsi_data *dsi = to_dsi_data(dssdev);
3006 int r;
3007
3008 r = dsi_vc_generic_send_read_request(dsi, channel, reqdata, reqlen);
3009 if (r)
3010 return r;
3011
3012 r = dsi_vc_send_bta_sync(dssdev, channel);
3013 if (r)
3014 return r;
3015
3016 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
3017 DSS_DSI_CONTENT_GENERIC);
3018 if (r < 0)
3019 return r;
3020
3021 if (r != buflen) {
3022 r = -EIO;
3023 return r;
3024 }
3025
3026 return 0;
3027 }
3028
3029 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3030 u16 len)
3031 {
3032 struct dsi_data *dsi = to_dsi_data(dssdev);
3033
3034 return dsi_vc_send_short(dsi, channel,
3035 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3036 }
3037
3038 static int dsi_enter_ulps(struct dsi_data *dsi)
3039 {
3040 DECLARE_COMPLETION_ONSTACK(completion);
3041 int r, i;
3042 unsigned int mask;
3043
3044 DSSDBG("Entering ULPS");
3045
3046 WARN_ON(!dsi_bus_is_locked(dsi));
3047
3048 WARN_ON(dsi->ulps_enabled);
3049
3050 if (dsi->ulps_enabled)
3051 return 0;
3052
3053 /* DDR_CLK_ALWAYS_ON */
3054 if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) {
3055 dsi_if_enable(dsi, 0);
3056 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
3057 dsi_if_enable(dsi, 1);
3058 }
3059
3060 dsi_sync_vc(dsi, 0);
3061 dsi_sync_vc(dsi, 1);
3062 dsi_sync_vc(dsi, 2);
3063 dsi_sync_vc(dsi, 3);
3064
3065 dsi_force_tx_stop_mode_io(dsi);
3066
3067 dsi_vc_enable(dsi, 0, false);
3068 dsi_vc_enable(dsi, 1, false);
3069 dsi_vc_enable(dsi, 2, false);
3070 dsi_vc_enable(dsi, 3, false);
3071
3072 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3073 DSSERR("HS busy when enabling ULPS\n");
3074 return -EIO;
3075 }
3076
3077 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3078 DSSERR("LP busy when enabling ULPS\n");
3079 return -EIO;
3080 }
3081
3082 r = dsi_register_isr_cio(dsi, dsi_completion_handler, &completion,
3083 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3084 if (r)
3085 return r;
3086
3087 mask = 0;
3088
3089 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3090 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3091 continue;
3092 mask |= 1 << i;
3093 }
3094 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3095 /* LANEx_ULPS_SIG2 */
3096 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3097
3098 /* flush posted write and wait for SCP interface to finish the write */
3099 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3100
3101 if (wait_for_completion_timeout(&completion,
3102 msecs_to_jiffies(1000)) == 0) {
3103 DSSERR("ULPS enable timeout\n");
3104 r = -EIO;
3105 goto err;
3106 }
3107
3108 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3109 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3110
3111 /* Reset LANEx_ULPS_SIG2 */
3112 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3113
3114 /* flush posted write and wait for SCP interface to finish the write */
3115 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3116
3117 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ULPS);
3118
3119 dsi_if_enable(dsi, false);
3120
3121 dsi->ulps_enabled = true;
3122
3123 return 0;
3124
3125 err:
3126 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3127 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3128 return r;
3129 }
3130
3131 static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks,
3132 bool x4, bool x16)
3133 {
3134 unsigned long fck;
3135 unsigned long total_ticks;
3136 u32 r;
3137
3138 BUG_ON(ticks > 0x1fff);
3139
3140 /* ticks in DSI_FCK */
3141 fck = dsi_fclk_rate(dsi);
3142
3143 r = dsi_read_reg(dsi, DSI_TIMING2);
3144 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3145 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3146 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3147 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3148 dsi_write_reg(dsi, DSI_TIMING2, r);
3149
3150 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3151
3152 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3153 total_ticks,
3154 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3155 (total_ticks * 1000) / (fck / 1000 / 1000));
3156 }
3157
3158 static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks,
3159 bool x8, bool x16)
3160 {
3161 unsigned long fck;
3162 unsigned long total_ticks;
3163 u32 r;
3164
3165 BUG_ON(ticks > 0x1fff);
3166
3167 /* ticks in DSI_FCK */
3168 fck = dsi_fclk_rate(dsi);
3169
3170 r = dsi_read_reg(dsi, DSI_TIMING1);
3171 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3172 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3173 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3174 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3175 dsi_write_reg(dsi, DSI_TIMING1, r);
3176
3177 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3178
3179 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3180 total_ticks,
3181 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3182 (total_ticks * 1000) / (fck / 1000 / 1000));
3183 }
3184
3185 static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks,
3186 bool x4, bool x16)
3187 {
3188 unsigned long fck;
3189 unsigned long total_ticks;
3190 u32 r;
3191
3192 BUG_ON(ticks > 0x1fff);
3193
3194 /* ticks in DSI_FCK */
3195 fck = dsi_fclk_rate(dsi);
3196
3197 r = dsi_read_reg(dsi, DSI_TIMING1);
3198 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3199 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3200 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3201 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3202 dsi_write_reg(dsi, DSI_TIMING1, r);
3203
3204 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3205
3206 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3207 total_ticks,
3208 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3209 (total_ticks * 1000) / (fck / 1000 / 1000));
3210 }
3211
3212 static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks,
3213 bool x4, bool x16)
3214 {
3215 unsigned long fck;
3216 unsigned long total_ticks;
3217 u32 r;
3218
3219 BUG_ON(ticks > 0x1fff);
3220
3221 /* ticks in TxByteClkHS */
3222 fck = dsi_get_txbyteclkhs(dsi);
3223
3224 r = dsi_read_reg(dsi, DSI_TIMING2);
3225 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3226 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3227 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3228 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3229 dsi_write_reg(dsi, DSI_TIMING2, r);
3230
3231 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3232
3233 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3234 total_ticks,
3235 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3236 (total_ticks * 1000) / (fck / 1000 / 1000));
3237 }
3238
3239 static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi)
3240 {
3241 int num_line_buffers;
3242
3243 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3244 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3245 const struct videomode *vm = &dsi->vm;
3246 /*
3247 * Don't use line buffers if width is greater than the video
3248 * port's line buffer size
3249 */
3250 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
3251 num_line_buffers = 0;
3252 else
3253 num_line_buffers = 2;
3254 } else {
3255 /* Use maximum number of line buffers in command mode */
3256 num_line_buffers = 2;
3257 }
3258
3259 /* LINE_BUFFER */
3260 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12);
3261 }
3262
3263 static void dsi_config_vp_sync_events(struct dsi_data *dsi)
3264 {
3265 bool sync_end;
3266 u32 r;
3267
3268 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3269 sync_end = true;
3270 else
3271 sync_end = false;
3272
3273 r = dsi_read_reg(dsi, DSI_CTRL);
3274 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3275 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3276 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3277 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3278 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3279 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3280 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3281 dsi_write_reg(dsi, DSI_CTRL, r);
3282 }
3283
3284 static void dsi_config_blanking_modes(struct dsi_data *dsi)
3285 {
3286 int blanking_mode = dsi->vm_timings.blanking_mode;
3287 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3288 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3289 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3290 u32 r;
3291
3292 /*
3293 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3294 * 1 = Long blanking packets are sent in corresponding blanking periods
3295 */
3296 r = dsi_read_reg(dsi, DSI_CTRL);
3297 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3298 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3299 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3300 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3301 dsi_write_reg(dsi, DSI_CTRL, r);
3302 }
3303
3304 /*
3305 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3306 * results in maximum transition time for data and clock lanes to enter and
3307 * exit HS mode. Hence, this is the scenario where the least amount of command
3308 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3309 * clock cycles that can be used to interleave command mode data in HS so that
3310 * all scenarios are satisfied.
3311 */
3312 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3313 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3314 {
3315 int transition;
3316
3317 /*
3318 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3319 * time of data lanes only, if it isn't set, we need to consider HS
3320 * transition time of both data and clock lanes. HS transition time
3321 * of Scenario 3 is considered.
3322 */
3323 if (ddr_alwon) {
3324 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3325 } else {
3326 int trans1, trans2;
3327 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3328 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3329 enter_hs + 1;
3330 transition = max(trans1, trans2);
3331 }
3332
3333 return blank > transition ? blank - transition : 0;
3334 }
3335
3336 /*
3337 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3338 * results in maximum transition time for data lanes to enter and exit LP mode.
3339 * Hence, this is the scenario where the least amount of command mode data can
3340 * be interleaved. We program the minimum amount of bytes that can be
3341 * interleaved in LP so that all scenarios are satisfied.
3342 */
3343 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3344 int lp_clk_div, int tdsi_fclk)
3345 {
3346 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3347 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3348 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3349 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3350 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3351
3352 /* maximum LP transition time according to Scenario 1 */
3353 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3354
3355 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3356 tlp_avail = thsbyte_clk * (blank - trans_lp);
3357
3358 ttxclkesc = tdsi_fclk * lp_clk_div;
3359
3360 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3361 26) / 16;
3362
3363 return max(lp_inter, 0);
3364 }
3365
3366 static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi)
3367 {
3368 int blanking_mode;
3369 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3370 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3371 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3372 int tclk_trail, ths_exit, exiths_clk;
3373 bool ddr_alwon;
3374 const struct videomode *vm = &dsi->vm;
3375 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3376 int ndl = dsi->num_lanes_used - 1;
3377 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3378 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3379 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3380 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3381 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3382 u32 r;
3383
3384 r = dsi_read_reg(dsi, DSI_CTRL);
3385 blanking_mode = FLD_GET(r, 20, 20);
3386 hfp_blanking_mode = FLD_GET(r, 21, 21);
3387 hbp_blanking_mode = FLD_GET(r, 22, 22);
3388 hsa_blanking_mode = FLD_GET(r, 23, 23);
3389
3390 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3391 hbp = FLD_GET(r, 11, 0);
3392 hfp = FLD_GET(r, 23, 12);
3393 hsa = FLD_GET(r, 31, 24);
3394
3395 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3396 ddr_clk_post = FLD_GET(r, 7, 0);
3397 ddr_clk_pre = FLD_GET(r, 15, 8);
3398
3399 r = dsi_read_reg(dsi, DSI_VM_TIMING7);
3400 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3401 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3402
3403 r = dsi_read_reg(dsi, DSI_CLK_CTRL);
3404 lp_clk_div = FLD_GET(r, 12, 0);
3405 ddr_alwon = FLD_GET(r, 13, 13);
3406
3407 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3408 ths_exit = FLD_GET(r, 7, 0);
3409
3410 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3411 tclk_trail = FLD_GET(r, 15, 8);
3412
3413 exiths_clk = ths_exit + tclk_trail;
3414
3415 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3416 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3417
3418 if (!hsa_blanking_mode) {
3419 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3420 enter_hs_mode_lat, exit_hs_mode_lat,
3421 exiths_clk, ddr_clk_pre, ddr_clk_post);
3422 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3423 enter_hs_mode_lat, exit_hs_mode_lat,
3424 lp_clk_div, dsi_fclk_hsdiv);
3425 }
3426
3427 if (!hfp_blanking_mode) {
3428 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3429 enter_hs_mode_lat, exit_hs_mode_lat,
3430 exiths_clk, ddr_clk_pre, ddr_clk_post);
3431 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3432 enter_hs_mode_lat, exit_hs_mode_lat,
3433 lp_clk_div, dsi_fclk_hsdiv);
3434 }
3435
3436 if (!hbp_blanking_mode) {
3437 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3438 enter_hs_mode_lat, exit_hs_mode_lat,
3439 exiths_clk, ddr_clk_pre, ddr_clk_post);
3440
3441 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3442 enter_hs_mode_lat, exit_hs_mode_lat,
3443 lp_clk_div, dsi_fclk_hsdiv);
3444 }
3445
3446 if (!blanking_mode) {
3447 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3448 enter_hs_mode_lat, exit_hs_mode_lat,
3449 exiths_clk, ddr_clk_pre, ddr_clk_post);
3450
3451 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3452 enter_hs_mode_lat, exit_hs_mode_lat,
3453 lp_clk_div, dsi_fclk_hsdiv);
3454 }
3455
3456 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3457 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3458 bl_interleave_hs);
3459
3460 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3461 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3462 bl_interleave_lp);
3463
3464 r = dsi_read_reg(dsi, DSI_VM_TIMING4);
3465 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3466 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3467 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3468 dsi_write_reg(dsi, DSI_VM_TIMING4, r);
3469
3470 r = dsi_read_reg(dsi, DSI_VM_TIMING5);
3471 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3472 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3473 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3474 dsi_write_reg(dsi, DSI_VM_TIMING5, r);
3475
3476 r = dsi_read_reg(dsi, DSI_VM_TIMING6);
3477 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3478 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3479 dsi_write_reg(dsi, DSI_VM_TIMING6, r);
3480 }
3481
3482 static int dsi_proto_config(struct dsi_data *dsi)
3483 {
3484 u32 r;
3485 int buswidth = 0;
3486
3487 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32,
3488 DSI_FIFO_SIZE_32,
3489 DSI_FIFO_SIZE_32,
3490 DSI_FIFO_SIZE_32);
3491
3492 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32,
3493 DSI_FIFO_SIZE_32,
3494 DSI_FIFO_SIZE_32,
3495 DSI_FIFO_SIZE_32);
3496
3497 /* XXX what values for the timeouts? */
3498 dsi_set_stop_state_counter(dsi, 0x1000, false, false);
3499 dsi_set_ta_timeout(dsi, 0x1fff, true, true);
3500 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true);
3501 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true);
3502
3503 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3504 case 16:
3505 buswidth = 0;
3506 break;
3507 case 18:
3508 buswidth = 1;
3509 break;
3510 case 24:
3511 buswidth = 2;
3512 break;
3513 default:
3514 BUG();
3515 return -EINVAL;
3516 }
3517
3518 r = dsi_read_reg(dsi, DSI_CTRL);
3519 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3520 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3521 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3522 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3523 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3524 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3525 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3526 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3527 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
3528 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3529 /* DCS_CMD_CODE, 1=start, 0=continue */
3530 r = FLD_MOD(r, 0, 25, 25);
3531 }
3532
3533 dsi_write_reg(dsi, DSI_CTRL, r);
3534
3535 dsi_config_vp_num_line_buffers(dsi);
3536
3537 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3538 dsi_config_vp_sync_events(dsi);
3539 dsi_config_blanking_modes(dsi);
3540 dsi_config_cmd_mode_interleaving(dsi);
3541 }
3542
3543 dsi_vc_initial_config(dsi, 0);
3544 dsi_vc_initial_config(dsi, 1);
3545 dsi_vc_initial_config(dsi, 2);
3546 dsi_vc_initial_config(dsi, 3);
3547
3548 return 0;
3549 }
3550
3551 static void dsi_proto_timings(struct dsi_data *dsi)
3552 {
3553 unsigned int tlpx, tclk_zero, tclk_prepare;
3554 unsigned int tclk_pre, tclk_post;
3555 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero;
3556 unsigned int ths_trail, ths_exit;
3557 unsigned int ddr_clk_pre, ddr_clk_post;
3558 unsigned int enter_hs_mode_lat, exit_hs_mode_lat;
3559 unsigned int ths_eot;
3560 int ndl = dsi->num_lanes_used - 1;
3561 u32 r;
3562
3563 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3564 ths_prepare = FLD_GET(r, 31, 24);
3565 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3566 ths_zero = ths_prepare_ths_zero - ths_prepare;
3567 ths_trail = FLD_GET(r, 15, 8);
3568 ths_exit = FLD_GET(r, 7, 0);
3569
3570 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3571 tlpx = FLD_GET(r, 20, 16) * 2;
3572 tclk_zero = FLD_GET(r, 7, 0);
3573
3574 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
3575 tclk_prepare = FLD_GET(r, 7, 0);
3576
3577 /* min 8*UI */
3578 tclk_pre = 20;
3579 /* min 60ns + 52*UI */
3580 tclk_post = ns2ddr(dsi, 60) + 26;
3581
3582 ths_eot = DIV_ROUND_UP(4, ndl);
3583
3584 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3585 4);
3586 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3587
3588 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3589 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3590
3591 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3592 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3593 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3594 dsi_write_reg(dsi, DSI_CLK_TIMING, r);
3595
3596 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3597 ddr_clk_pre,
3598 ddr_clk_post);
3599
3600 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3601 DIV_ROUND_UP(ths_prepare, 4) +
3602 DIV_ROUND_UP(ths_zero + 3, 4);
3603
3604 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3605
3606 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3607 FLD_VAL(exit_hs_mode_lat, 15, 0);
3608 dsi_write_reg(dsi, DSI_VM_TIMING7, r);
3609
3610 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3611 enter_hs_mode_lat, exit_hs_mode_lat);
3612
3613 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3614 /* TODO: Implement a video mode check_timings function */
3615 int hsa = dsi->vm_timings.hsa;
3616 int hfp = dsi->vm_timings.hfp;
3617 int hbp = dsi->vm_timings.hbp;
3618 int vsa = dsi->vm_timings.vsa;
3619 int vfp = dsi->vm_timings.vfp;
3620 int vbp = dsi->vm_timings.vbp;
3621 int window_sync = dsi->vm_timings.window_sync;
3622 bool hsync_end;
3623 const struct videomode *vm = &dsi->vm;
3624 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3625 int tl, t_he, width_bytes;
3626
3627 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3628 t_he = hsync_end ?
3629 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3630
3631 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3632
3633 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3634 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3635 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3636
3637 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3638 hfp, hsync_end ? hsa : 0, tl);
3639 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3640 vsa, vm->vactive);
3641
3642 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3643 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3644 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3645 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3646 dsi_write_reg(dsi, DSI_VM_TIMING1, r);
3647
3648 r = dsi_read_reg(dsi, DSI_VM_TIMING2);
3649 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3650 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3651 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3652 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3653 dsi_write_reg(dsi, DSI_VM_TIMING2, r);
3654
3655 r = dsi_read_reg(dsi, DSI_VM_TIMING3);
3656 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */
3657 r = FLD_MOD(r, tl, 31, 16); /* TL */
3658 dsi_write_reg(dsi, DSI_VM_TIMING3, r);
3659 }
3660 }
3661
3662 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3663 const struct omap_dsi_pin_config *pin_cfg)
3664 {
3665 struct dsi_data *dsi = to_dsi_data(dssdev);
3666 int num_pins;
3667 const int *pins;
3668 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3669 int num_lanes;
3670 int i;
3671
3672 static const enum dsi_lane_function functions[] = {
3673 DSI_LANE_CLK,
3674 DSI_LANE_DATA1,
3675 DSI_LANE_DATA2,
3676 DSI_LANE_DATA3,
3677 DSI_LANE_DATA4,
3678 };
3679
3680 num_pins = pin_cfg->num_pins;
3681 pins = pin_cfg->pins;
3682
3683 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3684 || num_pins % 2 != 0)
3685 return -EINVAL;
3686
3687 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3688 lanes[i].function = DSI_LANE_UNUSED;
3689
3690 num_lanes = 0;
3691
3692 for (i = 0; i < num_pins; i += 2) {
3693 u8 lane, pol;
3694 int dx, dy;
3695
3696 dx = pins[i];
3697 dy = pins[i + 1];
3698
3699 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3700 return -EINVAL;
3701
3702 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3703 return -EINVAL;
3704
3705 if (dx & 1) {
3706 if (dy != dx - 1)
3707 return -EINVAL;
3708 pol = 1;
3709 } else {
3710 if (dy != dx + 1)
3711 return -EINVAL;
3712 pol = 0;
3713 }
3714
3715 lane = dx / 2;
3716
3717 lanes[lane].function = functions[i / 2];
3718 lanes[lane].polarity = pol;
3719 num_lanes++;
3720 }
3721
3722 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3723 dsi->num_lanes_used = num_lanes;
3724
3725 return 0;
3726 }
3727
3728 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3729 {
3730 struct dsi_data *dsi = to_dsi_data(dssdev);
3731 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3732 u8 data_type;
3733 u16 word_count;
3734 int r;
3735
3736 r = dsi_display_init_dispc(dsi);
3737 if (r)
3738 return r;
3739
3740 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3741 switch (dsi->pix_fmt) {
3742 case OMAP_DSS_DSI_FMT_RGB888:
3743 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3744 break;
3745 case OMAP_DSS_DSI_FMT_RGB666:
3746 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3747 break;
3748 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3749 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3750 break;
3751 case OMAP_DSS_DSI_FMT_RGB565:
3752 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3753 break;
3754 default:
3755 r = -EINVAL;
3756 goto err_pix_fmt;
3757 }
3758
3759 dsi_if_enable(dsi, false);
3760 dsi_vc_enable(dsi, channel, false);
3761
3762 /* MODE, 1 = video mode */
3763 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4);
3764
3765 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3766
3767 dsi_vc_write_long_header(dsi, channel, data_type,
3768 word_count, 0);
3769
3770 dsi_vc_enable(dsi, channel, true);
3771 dsi_if_enable(dsi, true);
3772 }
3773
3774 r = dss_mgr_enable(&dsi->output);
3775 if (r)
3776 goto err_mgr_enable;
3777
3778 return 0;
3779
3780 err_mgr_enable:
3781 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3782 dsi_if_enable(dsi, false);
3783 dsi_vc_enable(dsi, channel, false);
3784 }
3785 err_pix_fmt:
3786 dsi_display_uninit_dispc(dsi);
3787 return r;
3788 }
3789
3790 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3791 {
3792 struct dsi_data *dsi = to_dsi_data(dssdev);
3793
3794 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3795 dsi_if_enable(dsi, false);
3796 dsi_vc_enable(dsi, channel, false);
3797
3798 /* MODE, 0 = command mode */
3799 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4);
3800
3801 dsi_vc_enable(dsi, channel, true);
3802 dsi_if_enable(dsi, true);
3803 }
3804
3805 dss_mgr_disable(&dsi->output);
3806
3807 dsi_display_uninit_dispc(dsi);
3808 }
3809
3810 static void dsi_update_screen_dispc(struct dsi_data *dsi)
3811 {
3812 unsigned int bytespp;
3813 unsigned int bytespl;
3814 unsigned int bytespf;
3815 unsigned int total_len;
3816 unsigned int packet_payload;
3817 unsigned int packet_len;
3818 u32 l;
3819 int r;
3820 const unsigned channel = dsi->update_channel;
3821 const unsigned int line_buf_size = dsi->line_buffer_size;
3822 u16 w = dsi->vm.hactive;
3823 u16 h = dsi->vm.vactive;
3824
3825 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3826
3827 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP);
3828
3829 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
3830 bytespl = w * bytespp;
3831 bytespf = bytespl * h;
3832
3833 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3834 * number of lines in a packet. See errata about VP_CLK_RATIO */
3835
3836 if (bytespf < line_buf_size)
3837 packet_payload = bytespf;
3838 else
3839 packet_payload = (line_buf_size) / bytespl * bytespl;
3840
3841 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3842 total_len = (bytespf / packet_payload) * packet_len;
3843
3844 if (bytespf % packet_payload)
3845 total_len += (bytespf % packet_payload) + 1;
3846
3847 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3848 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
3849
3850 dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE,
3851 packet_len, 0);
3852
3853 if (dsi->te_enabled)
3854 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3855 else
3856 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3857 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
3858
3859 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3860 * because DSS interrupts are not capable of waking up the CPU and the
3861 * framedone interrupt could be delayed for quite a long time. I think
3862 * the same goes for any DSS interrupts, but for some reason I have not
3863 * seen the problem anywhere else than here.
3864 */
3865 dispc_disable_sidle(dsi->dss->dispc);
3866
3867 dsi_perf_mark_start(dsi);
3868
3869 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3870 msecs_to_jiffies(250));
3871 BUG_ON(r == 0);
3872
3873 dss_mgr_start_update(&dsi->output);
3874
3875 if (dsi->te_enabled) {
3876 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3877 * for TE is longer than the timer allows */
3878 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3879
3880 dsi_vc_send_bta(dsi, channel);
3881
3882 #ifdef DSI_CATCH_MISSING_TE
3883 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3884 #endif
3885 }
3886 }
3887
3888 #ifdef DSI_CATCH_MISSING_TE
3889 static void dsi_te_timeout(struct timer_list *unused)
3890 {
3891 DSSERR("TE not received for 250ms!\n");
3892 }
3893 #endif
3894
3895 static void dsi_handle_framedone(struct dsi_data *dsi, int error)
3896 {
3897 /* SIDLEMODE back to smart-idle */
3898 dispc_enable_sidle(dsi->dss->dispc);
3899
3900 if (dsi->te_enabled) {
3901 /* enable LP_RX_TO again after the TE */
3902 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3903 }
3904
3905 dsi->framedone_callback(error, dsi->framedone_data);
3906
3907 if (!error)
3908 dsi_perf_show(dsi, "DISPC");
3909 }
3910
3911 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3912 {
3913 struct dsi_data *dsi = container_of(work, struct dsi_data,
3914 framedone_timeout_work.work);
3915 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3916 * 250ms which would conflict with this timeout work. What should be
3917 * done is first cancel the transfer on the HW, and then cancel the
3918 * possibly scheduled framedone work. However, cancelling the transfer
3919 * on the HW is buggy, and would probably require resetting the whole
3920 * DSI */
3921
3922 DSSERR("Framedone not received for 250ms!\n");
3923
3924 dsi_handle_framedone(dsi, -ETIMEDOUT);
3925 }
3926
3927 static void dsi_framedone_irq_callback(void *data)
3928 {
3929 struct dsi_data *dsi = data;
3930
3931 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3932 * turns itself off. However, DSI still has the pixels in its buffers,
3933 * and is sending the data.
3934 */
3935
3936 cancel_delayed_work(&dsi->framedone_timeout_work);
3937
3938 dsi_handle_framedone(dsi, 0);
3939 }
3940
3941 static int dsi_update(struct omap_dss_device *dssdev, int channel,
3942 void (*callback)(int, void *), void *data)
3943 {
3944 struct dsi_data *dsi = to_dsi_data(dssdev);
3945
3946 dsi_perf_mark_setup(dsi);
3947
3948 dsi->update_channel = channel;
3949
3950 dsi->framedone_callback = callback;
3951 dsi->framedone_data = data;
3952
3953 #ifdef DSI_PERF_MEASURE
3954 dsi->update_bytes = dsi->vm.hactive * dsi->vm.vactive *
3955 dsi_get_pixel_size(dsi->pix_fmt) / 8;
3956 #endif
3957 dsi_update_screen_dispc(dsi);
3958
3959 return 0;
3960 }
3961
3962 /* Display funcs */
3963
3964 static int dsi_configure_dispc_clocks(struct dsi_data *dsi)
3965 {
3966 struct dispc_clock_info dispc_cinfo;
3967 int r;
3968 unsigned long fck;
3969
3970 fck = dsi_get_pll_hsdiv_dispc_rate(dsi);
3971
3972 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
3973 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
3974
3975 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo);
3976 if (r) {
3977 DSSERR("Failed to calc dispc clocks\n");
3978 return r;
3979 }
3980
3981 dsi->mgr_config.clock_info = dispc_cinfo;
3982
3983 return 0;
3984 }
3985
3986 static int dsi_display_init_dispc(struct dsi_data *dsi)
3987 {
3988 enum omap_channel channel = dsi->output.dispc_channel;
3989 int r;
3990
3991 dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ?
3992 DSS_CLK_SRC_PLL1_1 :
3993 DSS_CLK_SRC_PLL2_1);
3994
3995 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
3996 r = dss_mgr_register_framedone_handler(&dsi->output,
3997 dsi_framedone_irq_callback, dsi);
3998 if (r) {
3999 DSSERR("can't register FRAMEDONE handler\n");
4000 goto err;
4001 }
4002
4003 dsi->mgr_config.stallmode = true;
4004 dsi->mgr_config.fifohandcheck = true;
4005 } else {
4006 dsi->mgr_config.stallmode = false;
4007 dsi->mgr_config.fifohandcheck = false;
4008 }
4009
4010 r = dsi_configure_dispc_clocks(dsi);
4011 if (r)
4012 goto err1;
4013
4014 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4015 dsi->mgr_config.video_port_width =
4016 dsi_get_pixel_size(dsi->pix_fmt);
4017 dsi->mgr_config.lcden_sig_polarity = 0;
4018
4019 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config);
4020
4021 return 0;
4022 err1:
4023 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4024 dss_mgr_unregister_framedone_handler(&dsi->output,
4025 dsi_framedone_irq_callback, dsi);
4026 err:
4027 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4028 return r;
4029 }
4030
4031 static void dsi_display_uninit_dispc(struct dsi_data *dsi)
4032 {
4033 enum omap_channel channel = dsi->output.dispc_channel;
4034
4035 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4036 dss_mgr_unregister_framedone_handler(&dsi->output,
4037 dsi_framedone_irq_callback, dsi);
4038
4039 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4040 }
4041
4042 static int dsi_configure_dsi_clocks(struct dsi_data *dsi)
4043 {
4044 struct dss_pll_clock_info cinfo;
4045 int r;
4046
4047 cinfo = dsi->user_dsi_cinfo;
4048
4049 r = dss_pll_set_config(&dsi->pll, &cinfo);
4050 if (r) {
4051 DSSERR("Failed to set dsi clocks\n");
4052 return r;
4053 }
4054
4055 return 0;
4056 }
4057
4058 static int dsi_display_init_dsi(struct dsi_data *dsi)
4059 {
4060 int r;
4061
4062 r = dss_pll_enable(&dsi->pll);
4063 if (r)
4064 return r;
4065
4066 r = dsi_configure_dsi_clocks(dsi);
4067 if (r)
4068 goto err0;
4069
4070 dss_select_dsi_clk_source(dsi->dss, dsi->module_id,
4071 dsi->module_id == 0 ?
4072 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2);
4073
4074 DSSDBG("PLL OK\n");
4075
4076 if (!dsi->vdds_dsi_enabled) {
4077 r = regulator_enable(dsi->vdds_dsi_reg);
4078 if (r)
4079 goto err1;
4080
4081 dsi->vdds_dsi_enabled = true;
4082 }
4083
4084 r = dsi_cio_init(dsi);
4085 if (r)
4086 goto err2;
4087
4088 _dsi_print_reset_status(dsi);
4089
4090 dsi_proto_timings(dsi);
4091 dsi_set_lp_clk_divisor(dsi);
4092
4093 if (1)
4094 _dsi_print_reset_status(dsi);
4095
4096 r = dsi_proto_config(dsi);
4097 if (r)
4098 goto err3;
4099
4100 /* enable interface */
4101 dsi_vc_enable(dsi, 0, 1);
4102 dsi_vc_enable(dsi, 1, 1);
4103 dsi_vc_enable(dsi, 2, 1);
4104 dsi_vc_enable(dsi, 3, 1);
4105 dsi_if_enable(dsi, 1);
4106 dsi_force_tx_stop_mode_io(dsi);
4107
4108 return 0;
4109 err3:
4110 dsi_cio_uninit(dsi);
4111 err2:
4112 regulator_disable(dsi->vdds_dsi_reg);
4113 dsi->vdds_dsi_enabled = false;
4114 err1:
4115 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4116 err0:
4117 dss_pll_disable(&dsi->pll);
4118
4119 return r;
4120 }
4121
4122 static void dsi_display_uninit_dsi(struct dsi_data *dsi, bool disconnect_lanes,
4123 bool enter_ulps)
4124 {
4125 if (enter_ulps && !dsi->ulps_enabled)
4126 dsi_enter_ulps(dsi);
4127
4128 /* disable interface */
4129 dsi_if_enable(dsi, 0);
4130 dsi_vc_enable(dsi, 0, 0);
4131 dsi_vc_enable(dsi, 1, 0);
4132 dsi_vc_enable(dsi, 2, 0);
4133 dsi_vc_enable(dsi, 3, 0);
4134
4135 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4136 dsi_cio_uninit(dsi);
4137 dss_pll_disable(&dsi->pll);
4138
4139 if (disconnect_lanes) {
4140 regulator_disable(dsi->vdds_dsi_reg);
4141 dsi->vdds_dsi_enabled = false;
4142 }
4143 }
4144
4145 static void dsi_display_enable(struct omap_dss_device *dssdev)
4146 {
4147 struct dsi_data *dsi = to_dsi_data(dssdev);
4148 int r;
4149
4150 DSSDBG("dsi_display_enable\n");
4151
4152 WARN_ON(!dsi_bus_is_locked(dsi));
4153
4154 mutex_lock(&dsi->lock);
4155
4156 r = dsi_runtime_get(dsi);
4157 if (r)
4158 goto err_get_dsi;
4159
4160 _dsi_initialize_irq(dsi);
4161
4162 r = dsi_display_init_dsi(dsi);
4163 if (r)
4164 goto err_init_dsi;
4165
4166 mutex_unlock(&dsi->lock);
4167
4168 return;
4169
4170 err_init_dsi:
4171 dsi_runtime_put(dsi);
4172 err_get_dsi:
4173 mutex_unlock(&dsi->lock);
4174 DSSDBG("dsi_display_enable FAILED\n");
4175 }
4176
4177 static void dsi_display_disable(struct omap_dss_device *dssdev,
4178 bool disconnect_lanes, bool enter_ulps)
4179 {
4180 struct dsi_data *dsi = to_dsi_data(dssdev);
4181
4182 DSSDBG("dsi_display_disable\n");
4183
4184 WARN_ON(!dsi_bus_is_locked(dsi));
4185
4186 mutex_lock(&dsi->lock);
4187
4188 dsi_sync_vc(dsi, 0);
4189 dsi_sync_vc(dsi, 1);
4190 dsi_sync_vc(dsi, 2);
4191 dsi_sync_vc(dsi, 3);
4192
4193 dsi_display_uninit_dsi(dsi, disconnect_lanes, enter_ulps);
4194
4195 dsi_runtime_put(dsi);
4196
4197 mutex_unlock(&dsi->lock);
4198 }
4199
4200 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4201 {
4202 struct dsi_data *dsi = to_dsi_data(dssdev);
4203
4204 dsi->te_enabled = enable;
4205 return 0;
4206 }
4207
4208 #ifdef PRINT_VERBOSE_VM_TIMINGS
4209 static void print_dsi_vm(const char *str,
4210 const struct omap_dss_dsi_videomode_timings *t)
4211 {
4212 unsigned long byteclk = t->hsclk / 4;
4213 int bl, wc, pps, tot;
4214
4215 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4216 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4217 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4218 tot = bl + pps;
4219
4220 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4221
4222 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4223 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4224 str,
4225 byteclk,
4226 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4227 bl, pps, tot,
4228 TO_DSI_T(t->hss),
4229 TO_DSI_T(t->hsa),
4230 TO_DSI_T(t->hse),
4231 TO_DSI_T(t->hbp),
4232 TO_DSI_T(pps),
4233 TO_DSI_T(t->hfp),
4234
4235 TO_DSI_T(bl),
4236 TO_DSI_T(pps),
4237
4238 TO_DSI_T(tot));
4239 #undef TO_DSI_T
4240 }
4241
4242 static void print_dispc_vm(const char *str, const struct videomode *vm)
4243 {
4244 unsigned long pck = vm->pixelclock;
4245 int hact, bl, tot;
4246
4247 hact = vm->hactive;
4248 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch;
4249 tot = hact + bl;
4250
4251 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4252
4253 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4254 "%u/%u/%u/%u = %u + %u = %u\n",
4255 str,
4256 pck,
4257 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch,
4258 bl, hact, tot,
4259 TO_DISPC_T(vm->hsync_len),
4260 TO_DISPC_T(vm->hback_porch),
4261 TO_DISPC_T(hact),
4262 TO_DISPC_T(vm->hfront_porch),
4263 TO_DISPC_T(bl),
4264 TO_DISPC_T(hact),
4265 TO_DISPC_T(tot));
4266 #undef TO_DISPC_T
4267 }
4268
4269 /* note: this is not quite accurate */
4270 static void print_dsi_dispc_vm(const char *str,
4271 const struct omap_dss_dsi_videomode_timings *t)
4272 {
4273 struct videomode vm = { 0 };
4274 unsigned long byteclk = t->hsclk / 4;
4275 unsigned long pck;
4276 u64 dsi_tput;
4277 int dsi_hact, dsi_htot;
4278
4279 dsi_tput = (u64)byteclk * t->ndl * 8;
4280 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4281 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4282 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4283
4284 vm.pixelclock = pck;
4285 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4286 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk);
4287 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk);
4288 vm.hactive = t->hact;
4289
4290 print_dispc_vm(str, &vm);
4291 }
4292 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4293
4294 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4295 unsigned long pck, void *data)
4296 {
4297 struct dsi_clk_calc_ctx *ctx = data;
4298 struct videomode *vm = &ctx->vm;
4299
4300 ctx->dispc_cinfo.lck_div = lckd;
4301 ctx->dispc_cinfo.pck_div = pckd;
4302 ctx->dispc_cinfo.lck = lck;
4303 ctx->dispc_cinfo.pck = pck;
4304
4305 *vm = *ctx->config->vm;
4306 vm->pixelclock = pck;
4307 vm->hactive = ctx->config->vm->hactive;
4308 vm->vactive = ctx->config->vm->vactive;
4309 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
4310 vm->vfront_porch = vm->vback_porch = 0;
4311
4312 return true;
4313 }
4314
4315 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4316 void *data)
4317 {
4318 struct dsi_clk_calc_ctx *ctx = data;
4319
4320 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4321 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4322
4323 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4324 ctx->req_pck_min, ctx->req_pck_max,
4325 dsi_cm_calc_dispc_cb, ctx);
4326 }
4327
4328 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4329 unsigned long clkdco, void *data)
4330 {
4331 struct dsi_clk_calc_ctx *ctx = data;
4332 struct dsi_data *dsi = ctx->dsi;
4333
4334 ctx->dsi_cinfo.n = n;
4335 ctx->dsi_cinfo.m = m;
4336 ctx->dsi_cinfo.fint = fint;
4337 ctx->dsi_cinfo.clkdco = clkdco;
4338
4339 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4340 dsi->data->max_fck_freq,
4341 dsi_cm_calc_hsdiv_cb, ctx);
4342 }
4343
4344 static bool dsi_cm_calc(struct dsi_data *dsi,
4345 const struct omap_dss_dsi_config *cfg,
4346 struct dsi_clk_calc_ctx *ctx)
4347 {
4348 unsigned long clkin;
4349 int bitspp, ndl;
4350 unsigned long pll_min, pll_max;
4351 unsigned long pck, txbyteclk;
4352
4353 clkin = clk_get_rate(dsi->pll.clkin);
4354 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4355 ndl = dsi->num_lanes_used - 1;
4356
4357 /*
4358 * Here we should calculate minimum txbyteclk to be able to send the
4359 * frame in time, and also to handle TE. That's not very simple, though,
4360 * especially as we go to LP between each pixel packet due to HW
4361 * "feature". So let's just estimate very roughly and multiply by 1.5.
4362 */
4363 pck = cfg->vm->pixelclock;
4364 pck = pck * 3 / 2;
4365 txbyteclk = pck * bitspp / 8 / ndl;
4366
4367 memset(ctx, 0, sizeof(*ctx));
4368 ctx->dsi = dsi;
4369 ctx->pll = &dsi->pll;
4370 ctx->config = cfg;
4371 ctx->req_pck_min = pck;
4372 ctx->req_pck_nom = pck;
4373 ctx->req_pck_max = pck * 3 / 2;
4374
4375 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4376 pll_max = cfg->hs_clk_max * 4;
4377
4378 return dss_pll_calc_a(ctx->pll, clkin,
4379 pll_min, pll_max,
4380 dsi_cm_calc_pll_cb, ctx);
4381 }
4382
4383 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4384 {
4385 struct dsi_data *dsi = ctx->dsi;
4386 const struct omap_dss_dsi_config *cfg = ctx->config;
4387 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4388 int ndl = dsi->num_lanes_used - 1;
4389 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4390 unsigned long byteclk = hsclk / 4;
4391
4392 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4393 int xres;
4394 int panel_htot, panel_hbl; /* pixels */
4395 int dispc_htot, dispc_hbl; /* pixels */
4396 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4397 int hfp, hsa, hbp;
4398 const struct videomode *req_vm;
4399 struct videomode *dispc_vm;
4400 struct omap_dss_dsi_videomode_timings *dsi_vm;
4401 u64 dsi_tput, dispc_tput;
4402
4403 dsi_tput = (u64)byteclk * ndl * 8;
4404
4405 req_vm = cfg->vm;
4406 req_pck_min = ctx->req_pck_min;
4407 req_pck_max = ctx->req_pck_max;
4408 req_pck_nom = ctx->req_pck_nom;
4409
4410 dispc_pck = ctx->dispc_cinfo.pck;
4411 dispc_tput = (u64)dispc_pck * bitspp;
4412
4413 xres = req_vm->hactive;
4414
4415 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch +
4416 req_vm->hsync_len;
4417 panel_htot = xres + panel_hbl;
4418
4419 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4420
4421 /*
4422 * When there are no line buffers, DISPC and DSI must have the
4423 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4424 */
4425 if (dsi->line_buffer_size < xres * bitspp / 8) {
4426 if (dispc_tput != dsi_tput)
4427 return false;
4428 } else {
4429 if (dispc_tput < dsi_tput)
4430 return false;
4431 }
4432
4433 /* DSI tput must be over the min requirement */
4434 if (dsi_tput < (u64)bitspp * req_pck_min)
4435 return false;
4436
4437 /* When non-burst mode, DSI tput must be below max requirement. */
4438 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4439 if (dsi_tput > (u64)bitspp * req_pck_max)
4440 return false;
4441 }
4442
4443 hss = DIV_ROUND_UP(4, ndl);
4444
4445 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4446 if (ndl == 3 && req_vm->hsync_len == 0)
4447 hse = 1;
4448 else
4449 hse = DIV_ROUND_UP(4, ndl);
4450 } else {
4451 hse = 0;
4452 }
4453
4454 /* DSI htot to match the panel's nominal pck */
4455 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4456
4457 /* fail if there would be no time for blanking */
4458 if (dsi_htot < hss + hse + dsi_hact)
4459 return false;
4460
4461 /* total DSI blanking needed to achieve panel's TL */
4462 dsi_hbl = dsi_htot - dsi_hact;
4463
4464 /* DISPC htot to match the DSI TL */
4465 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4466
4467 /* verify that the DSI and DISPC TLs are the same */
4468 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4469 return false;
4470
4471 dispc_hbl = dispc_htot - xres;
4472
4473 /* setup DSI videomode */
4474
4475 dsi_vm = &ctx->dsi_vm;
4476 memset(dsi_vm, 0, sizeof(*dsi_vm));
4477
4478 dsi_vm->hsclk = hsclk;
4479
4480 dsi_vm->ndl = ndl;
4481 dsi_vm->bitspp = bitspp;
4482
4483 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4484 hsa = 0;
4485 } else if (ndl == 3 && req_vm->hsync_len == 0) {
4486 hsa = 0;
4487 } else {
4488 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
4489 hsa = max(hsa - hse, 1);
4490 }
4491
4492 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom);
4493 hbp = max(hbp, 1);
4494
4495 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4496 if (hfp < 1) {
4497 int t;
4498 /* we need to take cycles from hbp */
4499
4500 t = 1 - hfp;
4501 hbp = max(hbp - t, 1);
4502 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4503
4504 if (hfp < 1 && hsa > 0) {
4505 /* we need to take cycles from hsa */
4506 t = 1 - hfp;
4507 hsa = max(hsa - t, 1);
4508 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4509 }
4510 }
4511
4512 if (hfp < 1)
4513 return false;
4514
4515 dsi_vm->hss = hss;
4516 dsi_vm->hsa = hsa;
4517 dsi_vm->hse = hse;
4518 dsi_vm->hbp = hbp;
4519 dsi_vm->hact = xres;
4520 dsi_vm->hfp = hfp;
4521
4522 dsi_vm->vsa = req_vm->vsync_len;
4523 dsi_vm->vbp = req_vm->vback_porch;
4524 dsi_vm->vact = req_vm->vactive;
4525 dsi_vm->vfp = req_vm->vfront_porch;
4526
4527 dsi_vm->trans_mode = cfg->trans_mode;
4528
4529 dsi_vm->blanking_mode = 0;
4530 dsi_vm->hsa_blanking_mode = 1;
4531 dsi_vm->hfp_blanking_mode = 1;
4532 dsi_vm->hbp_blanking_mode = 1;
4533
4534 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4535 dsi_vm->window_sync = 4;
4536
4537 /* setup DISPC videomode */
4538
4539 dispc_vm = &ctx->vm;
4540 *dispc_vm = *req_vm;
4541 dispc_vm->pixelclock = dispc_pck;
4542
4543 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4544 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
4545 req_pck_nom);
4546 hsa = max(hsa, 1);
4547 } else {
4548 hsa = 1;
4549 }
4550
4551 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom);
4552 hbp = max(hbp, 1);
4553
4554 hfp = dispc_hbl - hsa - hbp;
4555 if (hfp < 1) {
4556 int t;
4557 /* we need to take cycles from hbp */
4558
4559 t = 1 - hfp;
4560 hbp = max(hbp - t, 1);
4561 hfp = dispc_hbl - hsa - hbp;
4562
4563 if (hfp < 1) {
4564 /* we need to take cycles from hsa */
4565 t = 1 - hfp;
4566 hsa = max(hsa - t, 1);
4567 hfp = dispc_hbl - hsa - hbp;
4568 }
4569 }
4570
4571 if (hfp < 1)
4572 return false;
4573
4574 dispc_vm->hfront_porch = hfp;
4575 dispc_vm->hsync_len = hsa;
4576 dispc_vm->hback_porch = hbp;
4577
4578 return true;
4579 }
4580
4581
4582 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4583 unsigned long pck, void *data)
4584 {
4585 struct dsi_clk_calc_ctx *ctx = data;
4586
4587 ctx->dispc_cinfo.lck_div = lckd;
4588 ctx->dispc_cinfo.pck_div = pckd;
4589 ctx->dispc_cinfo.lck = lck;
4590 ctx->dispc_cinfo.pck = pck;
4591
4592 if (dsi_vm_calc_blanking(ctx) == false)
4593 return false;
4594
4595 #ifdef PRINT_VERBOSE_VM_TIMINGS
4596 print_dispc_vm("dispc", &ctx->vm);
4597 print_dsi_vm("dsi ", &ctx->dsi_vm);
4598 print_dispc_vm("req ", ctx->config->vm);
4599 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4600 #endif
4601
4602 return true;
4603 }
4604
4605 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4606 void *data)
4607 {
4608 struct dsi_clk_calc_ctx *ctx = data;
4609 unsigned long pck_max;
4610
4611 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4612 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4613
4614 /*
4615 * In burst mode we can let the dispc pck be arbitrarily high, but it
4616 * limits our scaling abilities. So for now, don't aim too high.
4617 */
4618
4619 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4620 pck_max = ctx->req_pck_max + 10000000;
4621 else
4622 pck_max = ctx->req_pck_max;
4623
4624 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4625 ctx->req_pck_min, pck_max,
4626 dsi_vm_calc_dispc_cb, ctx);
4627 }
4628
4629 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4630 unsigned long clkdco, void *data)
4631 {
4632 struct dsi_clk_calc_ctx *ctx = data;
4633 struct dsi_data *dsi = ctx->dsi;
4634
4635 ctx->dsi_cinfo.n = n;
4636 ctx->dsi_cinfo.m = m;
4637 ctx->dsi_cinfo.fint = fint;
4638 ctx->dsi_cinfo.clkdco = clkdco;
4639
4640 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4641 dsi->data->max_fck_freq,
4642 dsi_vm_calc_hsdiv_cb, ctx);
4643 }
4644
4645 static bool dsi_vm_calc(struct dsi_data *dsi,
4646 const struct omap_dss_dsi_config *cfg,
4647 struct dsi_clk_calc_ctx *ctx)
4648 {
4649 const struct videomode *vm = cfg->vm;
4650 unsigned long clkin;
4651 unsigned long pll_min;
4652 unsigned long pll_max;
4653 int ndl = dsi->num_lanes_used - 1;
4654 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4655 unsigned long byteclk_min;
4656
4657 clkin = clk_get_rate(dsi->pll.clkin);
4658
4659 memset(ctx, 0, sizeof(*ctx));
4660 ctx->dsi = dsi;
4661 ctx->pll = &dsi->pll;
4662 ctx->config = cfg;
4663
4664 /* these limits should come from the panel driver */
4665 ctx->req_pck_min = vm->pixelclock - 1000;
4666 ctx->req_pck_nom = vm->pixelclock;
4667 ctx->req_pck_max = vm->pixelclock + 1000;
4668
4669 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4670 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4671
4672 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4673 pll_max = cfg->hs_clk_max * 4;
4674 } else {
4675 unsigned long byteclk_max;
4676 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4677 ndl * 8);
4678
4679 pll_max = byteclk_max * 4 * 4;
4680 }
4681
4682 return dss_pll_calc_a(ctx->pll, clkin,
4683 pll_min, pll_max,
4684 dsi_vm_calc_pll_cb, ctx);
4685 }
4686
4687 static int dsi_set_config(struct omap_dss_device *dssdev,
4688 const struct omap_dss_dsi_config *config)
4689 {
4690 struct dsi_data *dsi = to_dsi_data(dssdev);
4691 struct dsi_clk_calc_ctx ctx;
4692 bool ok;
4693 int r;
4694
4695 mutex_lock(&dsi->lock);
4696
4697 dsi->pix_fmt = config->pixel_format;
4698 dsi->mode = config->mode;
4699
4700 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4701 ok = dsi_vm_calc(dsi, config, &ctx);
4702 else
4703 ok = dsi_cm_calc(dsi, config, &ctx);
4704
4705 if (!ok) {
4706 DSSERR("failed to find suitable DSI clock settings\n");
4707 r = -EINVAL;
4708 goto err;
4709 }
4710
4711 dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo);
4712
4713 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4714 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4715 if (r) {
4716 DSSERR("failed to find suitable DSI LP clock settings\n");
4717 goto err;
4718 }
4719
4720 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4721 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4722
4723 dsi->vm = ctx.vm;
4724
4725 /*
4726 * override interlace, logic level and edge related parameters in
4727 * videomode with default values
4728 */
4729 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4730 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4731 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4732 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4733 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4734 /*
4735 * HACK: These flags should be handled through the omap_dss_device bus
4736 * flags, but this will only be possible when the DSI encoder will be
4737 * converted to the omapdrm-managed encoder model.
4738 */
4739 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4740 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4741 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4742 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4743 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4744 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4745
4746 dss_mgr_set_timings(&dsi->output, &dsi->vm);
4747
4748 dsi->vm_timings = ctx.dsi_vm;
4749
4750 mutex_unlock(&dsi->lock);
4751
4752 return 0;
4753 err:
4754 mutex_unlock(&dsi->lock);
4755
4756 return r;
4757 }
4758
4759 /*
4760 * Return a hardcoded channel for the DSI output. This should work for
4761 * current use cases, but this can be later expanded to either resolve
4762 * the channel in some more dynamic manner, or get the channel as a user
4763 * parameter.
4764 */
4765 static enum omap_channel dsi_get_channel(struct dsi_data *dsi)
4766 {
4767 switch (dsi->data->model) {
4768 case DSI_MODEL_OMAP3:
4769 return OMAP_DSS_CHANNEL_LCD;
4770
4771 case DSI_MODEL_OMAP4:
4772 switch (dsi->module_id) {
4773 case 0:
4774 return OMAP_DSS_CHANNEL_LCD;
4775 case 1:
4776 return OMAP_DSS_CHANNEL_LCD2;
4777 default:
4778 DSSWARN("unsupported module id\n");
4779 return OMAP_DSS_CHANNEL_LCD;
4780 }
4781
4782 case DSI_MODEL_OMAP5:
4783 switch (dsi->module_id) {
4784 case 0:
4785 return OMAP_DSS_CHANNEL_LCD;
4786 case 1:
4787 return OMAP_DSS_CHANNEL_LCD3;
4788 default:
4789 DSSWARN("unsupported module id\n");
4790 return OMAP_DSS_CHANNEL_LCD;
4791 }
4792
4793 default:
4794 DSSWARN("unsupported DSS version\n");
4795 return OMAP_DSS_CHANNEL_LCD;
4796 }
4797 }
4798
4799 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4800 {
4801 struct dsi_data *dsi = to_dsi_data(dssdev);
4802 int i;
4803
4804 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4805 if (!dsi->vc[i].dssdev) {
4806 dsi->vc[i].dssdev = dssdev;
4807 *channel = i;
4808 return 0;
4809 }
4810 }
4811
4812 DSSERR("cannot get VC for display %s", dssdev->name);
4813 return -ENOSPC;
4814 }
4815
4816 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4817 {
4818 struct dsi_data *dsi = to_dsi_data(dssdev);
4819
4820 if (vc_id < 0 || vc_id > 3) {
4821 DSSERR("VC ID out of range\n");
4822 return -EINVAL;
4823 }
4824
4825 if (channel < 0 || channel > 3) {
4826 DSSERR("Virtual Channel out of range\n");
4827 return -EINVAL;
4828 }
4829
4830 if (dsi->vc[channel].dssdev != dssdev) {
4831 DSSERR("Virtual Channel not allocated to display %s\n",
4832 dssdev->name);
4833 return -EINVAL;
4834 }
4835
4836 dsi->vc[channel].vc_id = vc_id;
4837
4838 return 0;
4839 }
4840
4841 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4842 {
4843 struct dsi_data *dsi = to_dsi_data(dssdev);
4844
4845 if ((channel >= 0 && channel <= 3) &&
4846 dsi->vc[channel].dssdev == dssdev) {
4847 dsi->vc[channel].dssdev = NULL;
4848 dsi->vc[channel].vc_id = 0;
4849 }
4850 }
4851
4852
4853 static int dsi_get_clocks(struct dsi_data *dsi)
4854 {
4855 struct clk *clk;
4856
4857 clk = devm_clk_get(dsi->dev, "fck");
4858 if (IS_ERR(clk)) {
4859 DSSERR("can't get fck\n");
4860 return PTR_ERR(clk);
4861 }
4862
4863 dsi->dss_clk = clk;
4864
4865 return 0;
4866 }
4867
4868 static int dsi_connect(struct omap_dss_device *src,
4869 struct omap_dss_device *dst)
4870 {
4871 return omapdss_device_connect(dst->dss, dst, dst->next);
4872 }
4873
4874 static void dsi_disconnect(struct omap_dss_device *src,
4875 struct omap_dss_device *dst)
4876 {
4877 omapdss_device_disconnect(dst, dst->next);
4878 }
4879
4880 static const struct omap_dss_device_ops dsi_ops = {
4881 .connect = dsi_connect,
4882 .disconnect = dsi_disconnect,
4883 .enable = dsi_display_enable,
4884
4885 .dsi = {
4886 .bus_lock = dsi_bus_lock,
4887 .bus_unlock = dsi_bus_unlock,
4888
4889 .disable = dsi_display_disable,
4890
4891 .enable_hs = dsi_vc_enable_hs,
4892
4893 .configure_pins = dsi_configure_pins,
4894 .set_config = dsi_set_config,
4895
4896 .enable_video_output = dsi_enable_video_output,
4897 .disable_video_output = dsi_disable_video_output,
4898
4899 .update = dsi_update,
4900
4901 .enable_te = dsi_enable_te,
4902
4903 .request_vc = dsi_request_vc,
4904 .set_vc_id = dsi_set_vc_id,
4905 .release_vc = dsi_release_vc,
4906
4907 .dcs_write = dsi_vc_dcs_write,
4908 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
4909 .dcs_read = dsi_vc_dcs_read,
4910
4911 .gen_write = dsi_vc_generic_write,
4912 .gen_write_nosync = dsi_vc_generic_write_nosync,
4913 .gen_read = dsi_vc_generic_read,
4914
4915 .bta_sync = dsi_vc_send_bta_sync,
4916
4917 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
4918 },
4919 };
4920
4921 /* -----------------------------------------------------------------------------
4922 * PLL
4923 */
4924
4925 static const struct dss_pll_ops dsi_pll_ops = {
4926 .enable = dsi_pll_enable,
4927 .disable = dsi_pll_disable,
4928 .set_config = dss_pll_write_config_type_a,
4929 };
4930
4931 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
4932 .type = DSS_PLL_TYPE_A,
4933
4934 .n_max = (1 << 7) - 1,
4935 .m_max = (1 << 11) - 1,
4936 .mX_max = (1 << 4) - 1,
4937 .fint_min = 750000,
4938 .fint_max = 2100000,
4939 .clkdco_low = 1000000000,
4940 .clkdco_max = 1800000000,
4941
4942 .n_msb = 7,
4943 .n_lsb = 1,
4944 .m_msb = 18,
4945 .m_lsb = 8,
4946
4947 .mX_msb[0] = 22,
4948 .mX_lsb[0] = 19,
4949 .mX_msb[1] = 26,
4950 .mX_lsb[1] = 23,
4951
4952 .has_stopmode = true,
4953 .has_freqsel = true,
4954 .has_selfreqdco = false,
4955 .has_refsel = false,
4956 };
4957
4958 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
4959 .type = DSS_PLL_TYPE_A,
4960
4961 .n_max = (1 << 8) - 1,
4962 .m_max = (1 << 12) - 1,
4963 .mX_max = (1 << 5) - 1,
4964 .fint_min = 500000,
4965 .fint_max = 2500000,
4966 .clkdco_low = 1000000000,
4967 .clkdco_max = 1800000000,
4968
4969 .n_msb = 8,
4970 .n_lsb = 1,
4971 .m_msb = 20,
4972 .m_lsb = 9,
4973
4974 .mX_msb[0] = 25,
4975 .mX_lsb[0] = 21,
4976 .mX_msb[1] = 30,
4977 .mX_lsb[1] = 26,
4978
4979 .has_stopmode = true,
4980 .has_freqsel = false,
4981 .has_selfreqdco = false,
4982 .has_refsel = false,
4983 };
4984
4985 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
4986 .type = DSS_PLL_TYPE_A,
4987
4988 .n_max = (1 << 8) - 1,
4989 .m_max = (1 << 12) - 1,
4990 .mX_max = (1 << 5) - 1,
4991 .fint_min = 150000,
4992 .fint_max = 52000000,
4993 .clkdco_low = 1000000000,
4994 .clkdco_max = 1800000000,
4995
4996 .n_msb = 8,
4997 .n_lsb = 1,
4998 .m_msb = 20,
4999 .m_lsb = 9,
5000
5001 .mX_msb[0] = 25,
5002 .mX_lsb[0] = 21,
5003 .mX_msb[1] = 30,
5004 .mX_lsb[1] = 26,
5005
5006 .has_stopmode = true,
5007 .has_freqsel = false,
5008 .has_selfreqdco = true,
5009 .has_refsel = true,
5010 };
5011
5012 static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi)
5013 {
5014 struct dss_pll *pll = &dsi->pll;
5015 struct clk *clk;
5016 int r;
5017
5018 clk = devm_clk_get(dsi->dev, "sys_clk");
5019 if (IS_ERR(clk)) {
5020 DSSERR("can't get sys_clk\n");
5021 return PTR_ERR(clk);
5022 }
5023
5024 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5025 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5026 pll->clkin = clk;
5027 pll->base = dsi->pll_base;
5028 pll->hw = dsi->data->pll_hw;
5029 pll->ops = &dsi_pll_ops;
5030
5031 r = dss_pll_register(dss, pll);
5032 if (r)
5033 return r;
5034
5035 return 0;
5036 }
5037
5038 /* -----------------------------------------------------------------------------
5039 * Component Bind & Unbind
5040 */
5041
5042 static int dsi_bind(struct device *dev, struct device *master, void *data)
5043 {
5044 struct dss_device *dss = dss_get_device(master);
5045 struct dsi_data *dsi = dev_get_drvdata(dev);
5046 char name[10];
5047 u32 rev;
5048 int r;
5049
5050 dsi->dss = dss;
5051
5052 dsi_init_pll_data(dss, dsi);
5053
5054 r = dsi_runtime_get(dsi);
5055 if (r)
5056 return r;
5057
5058 rev = dsi_read_reg(dsi, DSI_REVISION);
5059 dev_dbg(dev, "OMAP DSI rev %d.%d\n",
5060 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5061
5062 dsi->line_buffer_size = dsi_get_line_buf_size(dsi);
5063
5064 dsi_runtime_put(dsi);
5065
5066 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1);
5067 dsi->debugfs.regs = dss_debugfs_create_file(dss, name,
5068 dsi_dump_dsi_regs, dsi);
5069 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5070 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1);
5071 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name,
5072 dsi_dump_dsi_irqs, dsi);
5073 #endif
5074 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1);
5075 dsi->debugfs.clks = dss_debugfs_create_file(dss, name,
5076 dsi_dump_dsi_clocks, dsi);
5077
5078 return 0;
5079 }
5080
5081 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5082 {
5083 struct dsi_data *dsi = dev_get_drvdata(dev);
5084
5085 dss_debugfs_remove_file(dsi->debugfs.clks);
5086 dss_debugfs_remove_file(dsi->debugfs.irqs);
5087 dss_debugfs_remove_file(dsi->debugfs.regs);
5088
5089 WARN_ON(dsi->scp_clk_refcount > 0);
5090
5091 dss_pll_unregister(&dsi->pll);
5092 }
5093
5094 static const struct component_ops dsi_component_ops = {
5095 .bind = dsi_bind,
5096 .unbind = dsi_unbind,
5097 };
5098
5099 /* -----------------------------------------------------------------------------
5100 * Probe & Remove, Suspend & Resume
5101 */
5102
5103 static int dsi_init_output(struct dsi_data *dsi)
5104 {
5105 struct omap_dss_device *out = &dsi->output;
5106 int r;
5107
5108 out->dev = dsi->dev;
5109 out->id = dsi->module_id == 0 ?
5110 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5111
5112 out->type = OMAP_DISPLAY_TYPE_DSI;
5113 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5114 out->dispc_channel = dsi_get_channel(dsi);
5115 out->ops = &dsi_ops;
5116 out->owner = THIS_MODULE;
5117 out->of_port = 0;
5118 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
5119 | DRM_BUS_FLAG_DE_HIGH
5120 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
5121
5122 r = omapdss_device_init_output(out, NULL);
5123 if (r < 0)
5124 return r;
5125
5126 omapdss_device_register(out);
5127
5128 return 0;
5129 }
5130
5131 static void dsi_uninit_output(struct dsi_data *dsi)
5132 {
5133 struct omap_dss_device *out = &dsi->output;
5134
5135 omapdss_device_unregister(out);
5136 omapdss_device_cleanup_output(out);
5137 }
5138
5139 static int dsi_probe_of(struct dsi_data *dsi)
5140 {
5141 struct device_node *node = dsi->dev->of_node;
5142 struct property *prop;
5143 u32 lane_arr[10];
5144 int len, num_pins;
5145 int r, i;
5146 struct device_node *ep;
5147 struct omap_dsi_pin_config pin_cfg;
5148
5149 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
5150 if (!ep)
5151 return 0;
5152
5153 prop = of_find_property(ep, "lanes", &len);
5154 if (prop == NULL) {
5155 dev_err(dsi->dev, "failed to find lane data\n");
5156 r = -EINVAL;
5157 goto err;
5158 }
5159
5160 num_pins = len / sizeof(u32);
5161
5162 if (num_pins < 4 || num_pins % 2 != 0 ||
5163 num_pins > dsi->num_lanes_supported * 2) {
5164 dev_err(dsi->dev, "bad number of lanes\n");
5165 r = -EINVAL;
5166 goto err;
5167 }
5168
5169 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5170 if (r) {
5171 dev_err(dsi->dev, "failed to read lane data\n");
5172 goto err;
5173 }
5174
5175 pin_cfg.num_pins = num_pins;
5176 for (i = 0; i < num_pins; ++i)
5177 pin_cfg.pins[i] = (int)lane_arr[i];
5178
5179 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5180 if (r) {
5181 dev_err(dsi->dev, "failed to configure pins");
5182 goto err;
5183 }
5184
5185 of_node_put(ep);
5186
5187 return 0;
5188
5189 err:
5190 of_node_put(ep);
5191 return r;
5192 }
5193
5194 static const struct dsi_of_data dsi_of_data_omap34xx = {
5195 .model = DSI_MODEL_OMAP3,
5196 .pll_hw = &dss_omap3_dsi_pll_hw,
5197 .modules = (const struct dsi_module_id_data[]) {
5198 { .address = 0x4804fc00, .id = 0, },
5199 { },
5200 },
5201 .max_fck_freq = 173000000,
5202 .max_pll_lpdiv = (1 << 13) - 1,
5203 .quirks = DSI_QUIRK_REVERSE_TXCLKESC,
5204 };
5205
5206 static const struct dsi_of_data dsi_of_data_omap36xx = {
5207 .model = DSI_MODEL_OMAP3,
5208 .pll_hw = &dss_omap3_dsi_pll_hw,
5209 .modules = (const struct dsi_module_id_data[]) {
5210 { .address = 0x4804fc00, .id = 0, },
5211 { },
5212 },
5213 .max_fck_freq = 173000000,
5214 .max_pll_lpdiv = (1 << 13) - 1,
5215 .quirks = DSI_QUIRK_PLL_PWR_BUG,
5216 };
5217
5218 static const struct dsi_of_data dsi_of_data_omap4 = {
5219 .model = DSI_MODEL_OMAP4,
5220 .pll_hw = &dss_omap4_dsi_pll_hw,
5221 .modules = (const struct dsi_module_id_data[]) {
5222 { .address = 0x58004000, .id = 0, },
5223 { .address = 0x58005000, .id = 1, },
5224 { },
5225 },
5226 .max_fck_freq = 170000000,
5227 .max_pll_lpdiv = (1 << 13) - 1,
5228 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5229 | DSI_QUIRK_GNQ,
5230 };
5231
5232 static const struct dsi_of_data dsi_of_data_omap5 = {
5233 .model = DSI_MODEL_OMAP5,
5234 .pll_hw = &dss_omap5_dsi_pll_hw,
5235 .modules = (const struct dsi_module_id_data[]) {
5236 { .address = 0x58004000, .id = 0, },
5237 { .address = 0x58009000, .id = 1, },
5238 { },
5239 },
5240 .max_fck_freq = 209250000,
5241 .max_pll_lpdiv = (1 << 13) - 1,
5242 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5243 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC,
5244 };
5245
5246 static const struct of_device_id dsi_of_match[] = {
5247 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
5248 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
5249 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
5250 {},
5251 };
5252
5253 static const struct soc_device_attribute dsi_soc_devices[] = {
5254 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx },
5255 { .machine = "AM35*", .data = &dsi_of_data_omap34xx },
5256 { /* sentinel */ }
5257 };
5258
5259 static int dsi_probe(struct platform_device *pdev)
5260 {
5261 const struct soc_device_attribute *soc;
5262 const struct dsi_module_id_data *d;
5263 struct device *dev = &pdev->dev;
5264 struct dsi_data *dsi;
5265 struct resource *dsi_mem;
5266 struct resource *res;
5267 unsigned int i;
5268 int r;
5269
5270 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
5271 if (!dsi)
5272 return -ENOMEM;
5273
5274 dsi->dev = dev;
5275 dev_set_drvdata(dev, dsi);
5276
5277 spin_lock_init(&dsi->irq_lock);
5278 spin_lock_init(&dsi->errors_lock);
5279 dsi->errors = 0;
5280
5281 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5282 spin_lock_init(&dsi->irq_stats_lock);
5283 dsi->irq_stats.last_reset = jiffies;
5284 #endif
5285
5286 mutex_init(&dsi->lock);
5287 sema_init(&dsi->bus_lock, 1);
5288
5289 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5290 dsi_framedone_timeout_work_callback);
5291
5292 #ifdef DSI_CATCH_MISSING_TE
5293 timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5294 #endif
5295
5296 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto");
5297 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem);
5298 if (IS_ERR(dsi->proto_base))
5299 return PTR_ERR(dsi->proto_base);
5300
5301 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
5302 dsi->phy_base = devm_ioremap_resource(dev, res);
5303 if (IS_ERR(dsi->phy_base))
5304 return PTR_ERR(dsi->phy_base);
5305
5306 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
5307 dsi->pll_base = devm_ioremap_resource(dev, res);
5308 if (IS_ERR(dsi->pll_base))
5309 return PTR_ERR(dsi->pll_base);
5310
5311 dsi->irq = platform_get_irq(pdev, 0);
5312 if (dsi->irq < 0) {
5313 DSSERR("platform_get_irq failed\n");
5314 return -ENODEV;
5315 }
5316
5317 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler,
5318 IRQF_SHARED, dev_name(dev), dsi);
5319 if (r < 0) {
5320 DSSERR("request_irq failed\n");
5321 return r;
5322 }
5323
5324 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd");
5325 if (IS_ERR(dsi->vdds_dsi_reg)) {
5326 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER)
5327 DSSERR("can't get DSI VDD regulator\n");
5328 return PTR_ERR(dsi->vdds_dsi_reg);
5329 }
5330
5331 soc = soc_device_match(dsi_soc_devices);
5332 if (soc)
5333 dsi->data = soc->data;
5334 else
5335 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
5336
5337 d = dsi->data->modules;
5338 while (d->address != 0 && d->address != dsi_mem->start)
5339 d++;
5340
5341 if (d->address == 0) {
5342 DSSERR("unsupported DSI module\n");
5343 return -ENODEV;
5344 }
5345
5346 dsi->module_id = d->id;
5347
5348 if (dsi->data->model == DSI_MODEL_OMAP4 ||
5349 dsi->data->model == DSI_MODEL_OMAP5) {
5350 struct device_node *np;
5351
5352 /*
5353 * The OMAP4/5 display DT bindings don't reference the padconf
5354 * syscon. Our only option to retrieve it is to find it by name.
5355 */
5356 np = of_find_node_by_name(NULL,
5357 dsi->data->model == DSI_MODEL_OMAP4 ?
5358 "omap4_padconf_global" : "omap5_padconf_global");
5359 if (!np)
5360 return -ENODEV;
5361
5362 dsi->syscon = syscon_node_to_regmap(np);
5363 of_node_put(np);
5364 }
5365
5366 /* DSI VCs initialization */
5367 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5368 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5369 dsi->vc[i].dssdev = NULL;
5370 dsi->vc[i].vc_id = 0;
5371 }
5372
5373 r = dsi_get_clocks(dsi);
5374 if (r)
5375 return r;
5376
5377 pm_runtime_enable(dev);
5378
5379 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5380 * of data to 3 by default */
5381 if (dsi->data->quirks & DSI_QUIRK_GNQ) {
5382 dsi_runtime_get(dsi);
5383 /* NB_DATA_LANES */
5384 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9);
5385 dsi_runtime_put(dsi);
5386 } else {
5387 dsi->num_lanes_supported = 3;
5388 }
5389
5390 r = of_platform_populate(dev->of_node, NULL, NULL, dev);
5391 if (r) {
5392 DSSERR("Failed to populate DSI child devices: %d\n", r);
5393 goto err_pm_disable;
5394 }
5395
5396 r = dsi_init_output(dsi);
5397 if (r)
5398 goto err_of_depopulate;
5399
5400 r = dsi_probe_of(dsi);
5401 if (r) {
5402 DSSERR("Invalid DSI DT data\n");
5403 goto err_uninit_output;
5404 }
5405
5406 r = component_add(&pdev->dev, &dsi_component_ops);
5407 if (r)
5408 goto err_uninit_output;
5409
5410 return 0;
5411
5412 err_uninit_output:
5413 dsi_uninit_output(dsi);
5414 err_of_depopulate:
5415 of_platform_depopulate(dev);
5416 err_pm_disable:
5417 pm_runtime_disable(dev);
5418 return r;
5419 }
5420
5421 static int dsi_remove(struct platform_device *pdev)
5422 {
5423 struct dsi_data *dsi = platform_get_drvdata(pdev);
5424
5425 component_del(&pdev->dev, &dsi_component_ops);
5426
5427 dsi_uninit_output(dsi);
5428
5429 of_platform_depopulate(&pdev->dev);
5430
5431 pm_runtime_disable(&pdev->dev);
5432
5433 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5434 regulator_disable(dsi->vdds_dsi_reg);
5435 dsi->vdds_dsi_enabled = false;
5436 }
5437
5438 return 0;
5439 }
5440
5441 static int dsi_runtime_suspend(struct device *dev)
5442 {
5443 struct dsi_data *dsi = dev_get_drvdata(dev);
5444
5445 dsi->is_enabled = false;
5446 /* ensure the irq handler sees the is_enabled value */
5447 smp_wmb();
5448 /* wait for current handler to finish before turning the DSI off */
5449 synchronize_irq(dsi->irq);
5450
5451 return 0;
5452 }
5453
5454 static int dsi_runtime_resume(struct device *dev)
5455 {
5456 struct dsi_data *dsi = dev_get_drvdata(dev);
5457
5458 dsi->is_enabled = true;
5459 /* ensure the irq handler sees the is_enabled value */
5460 smp_wmb();
5461
5462 return 0;
5463 }
5464
5465 static const struct dev_pm_ops dsi_pm_ops = {
5466 .runtime_suspend = dsi_runtime_suspend,
5467 .runtime_resume = dsi_runtime_resume,
5468 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
5469 };
5470
5471 struct platform_driver omap_dsihw_driver = {
5472 .probe = dsi_probe,
5473 .remove = dsi_remove,
5474 .driver = {
5475 .name = "omapdss_dsi",
5476 .pm = &dsi_pm_ops,
5477 .of_match_table = dsi_of_match,
5478 .suppress_bind_attrs = true,
5479 },
5480 };
Linux with added FPC-III support