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WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / omapdrm / dss / hdmi5_core.c
blob6cc2ad7a420cb03eb7310c7b89635b7448fdffe0
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * OMAP5 HDMI CORE IP driver library
4 *
5 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/seq_file.h>
20 #include <drm/drm_edid.h>
21 #include <sound/asound.h>
22 #include <sound/asoundef.h>
23
24 #include "hdmi5_core.h"
25
26 void hdmi5_core_ddc_init(struct hdmi_core_data *core)
27 {
28 void __iomem *base = core->base;
29 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
30 const unsigned int ss_scl_high = 4700; /* ns */
31 const unsigned int ss_scl_low = 5500; /* ns */
32 const unsigned int fs_scl_high = 600; /* ns */
33 const unsigned int fs_scl_low = 1300; /* ns */
34 const unsigned int sda_hold = 1000; /* ns */
35 const unsigned int sfr_div = 10;
36 unsigned long long sfr;
37 unsigned int v;
38
39 sfr = iclk / sfr_div; /* SFR_DIV */
40 sfr /= 1000; /* SFR clock in kHz */
41
42 /* Reset */
43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
44 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
45 0, 0, 1) != 1)
46 DSSERR("HDMI I2CM reset failed\n");
47
48 /* Standard (0) or Fast (1) Mode */
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
50
51 /* Standard Mode SCL High counter */
52 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
53 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
54 (v >> 8) & 0xff, 7, 0);
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
56 v & 0xff, 7, 0);
57
58 /* Standard Mode SCL Low counter */
59 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
60 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
61 (v >> 8) & 0xff, 7, 0);
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
63 v & 0xff, 7, 0);
64
65 /* Fast Mode SCL High Counter */
66 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
68 (v >> 8) & 0xff, 7, 0);
69 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
70 v & 0xff, 7, 0);
71
72 /* Fast Mode SCL Low Counter */
73 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
74 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
75 (v >> 8) & 0xff, 7, 0);
76 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
77 v & 0xff, 7, 0);
78
79 /* SDA Hold Time */
80 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
81 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
82
83 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
84 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
85
86 /* NACK_POL to high */
87 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
88
89 /* NACK_MASK to unmasked */
90 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
91
92 /* ARBITRATION_POL to high */
93 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
94
95 /* ARBITRATION_MASK to unmasked */
96 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
97
98 /* DONE_POL to high */
99 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
100
101 /* DONE_MASK to unmasked */
102 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
103 }
104
105 void hdmi5_core_ddc_uninit(struct hdmi_core_data *core)
106 {
107 void __iomem *base = core->base;
108
109 /* Mask I2C interrupts */
110 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
111 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
112 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
113 }
114
115 int hdmi5_core_ddc_read(void *data, u8 *buf, unsigned int block, size_t len)
116 {
117 struct hdmi_core_data *core = data;
118 void __iomem *base = core->base;
119 u8 cur_addr;
120 const int retries = 1000;
121 u8 seg_ptr = block / 2;
122 u8 edidbase = ((block % 2) * EDID_LENGTH);
123
124 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
125
126 /*
127 * TODO: We use polling here, although we probably should use proper
128 * interrupts.
129 */
130 for (cur_addr = 0; cur_addr < len; ++cur_addr) {
131 int i;
132
133 /* clear ERROR and DONE */
134 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
135
136 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
137 edidbase + cur_addr, 7, 0);
138
139 if (seg_ptr)
140 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
141 else
142 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
143
144 for (i = 0; i < retries; ++i) {
145 u32 stat;
146
147 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
148
149 /* I2CM_ERROR */
150 if (stat & 1) {
151 DSSERR("HDMI I2C Master Error\n");
152 return -EIO;
153 }
154
155 /* I2CM_DONE */
156 if (stat & (1 << 1))
157 break;
158
159 usleep_range(250, 1000);
160 }
161
162 if (i == retries) {
163 DSSERR("HDMI I2C timeout reading EDID\n");
164 return -EIO;
165 }
166
167 buf[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
168 }
169
170 return 0;
171
172 }
173
174 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
175 {
176
177 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
178 hdmi_read_reg(core->base, r))
179
180 DUMPCORE(HDMI_CORE_FC_INVIDCONF);
181 DUMPCORE(HDMI_CORE_FC_INHACTIV0);
182 DUMPCORE(HDMI_CORE_FC_INHACTIV1);
183 DUMPCORE(HDMI_CORE_FC_INHBLANK0);
184 DUMPCORE(HDMI_CORE_FC_INHBLANK1);
185 DUMPCORE(HDMI_CORE_FC_INVACTIV0);
186 DUMPCORE(HDMI_CORE_FC_INVACTIV1);
187 DUMPCORE(HDMI_CORE_FC_INVBLANK);
188 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
189 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
190 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
191 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
192 DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
193 DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
194 DUMPCORE(HDMI_CORE_FC_CTRLDUR);
195 DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
196 DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
197 DUMPCORE(HDMI_CORE_FC_CH0PREAM);
198 DUMPCORE(HDMI_CORE_FC_CH1PREAM);
199 DUMPCORE(HDMI_CORE_FC_CH2PREAM);
200 DUMPCORE(HDMI_CORE_FC_AVICONF0);
201 DUMPCORE(HDMI_CORE_FC_AVICONF1);
202 DUMPCORE(HDMI_CORE_FC_AVICONF2);
203 DUMPCORE(HDMI_CORE_FC_AVIVID);
204 DUMPCORE(HDMI_CORE_FC_PRCONF);
205
206 DUMPCORE(HDMI_CORE_MC_CLKDIS);
207 DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
208 DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
209 DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
210 DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
211
212 DUMPCORE(HDMI_CORE_I2CM_SLAVE);
213 DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
214 DUMPCORE(HDMI_CORE_I2CM_DATAO);
215 DUMPCORE(HDMI_CORE_I2CM_DATAI);
216 DUMPCORE(HDMI_CORE_I2CM_OPERATION);
217 DUMPCORE(HDMI_CORE_I2CM_INT);
218 DUMPCORE(HDMI_CORE_I2CM_CTLINT);
219 DUMPCORE(HDMI_CORE_I2CM_DIV);
220 DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
221 DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
222 DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
223 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
224 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
225 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
226 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
227 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
228 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
229 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
230 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
231 DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
232 }
233
234 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
235 const struct hdmi_config *cfg)
236 {
237 DSSDBG("hdmi_core_init\n");
238
239 video_cfg->v_fc_config.vm = cfg->vm;
240
241 /* video core */
242 video_cfg->data_enable_pol = 1; /* It is always 1*/
243 video_cfg->hblank = cfg->vm.hfront_porch +
244 cfg->vm.hback_porch + cfg->vm.hsync_len;
245 video_cfg->vblank_osc = 0;
246 video_cfg->vblank = cfg->vm.vsync_len + cfg->vm.vfront_porch +
247 cfg->vm.vback_porch;
248 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
249
250 if (cfg->vm.flags & DISPLAY_FLAGS_INTERLACED) {
251 /* set vblank_osc if vblank is fractional */
252 if (video_cfg->vblank % 2 != 0)
253 video_cfg->vblank_osc = 1;
254
255 video_cfg->v_fc_config.vm.vactive /= 2;
256 video_cfg->vblank /= 2;
257 video_cfg->v_fc_config.vm.vfront_porch /= 2;
258 video_cfg->v_fc_config.vm.vsync_len /= 2;
259 video_cfg->v_fc_config.vm.vback_porch /= 2;
260 }
261
262 if (cfg->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
263 video_cfg->v_fc_config.vm.hactive *= 2;
264 video_cfg->hblank *= 2;
265 video_cfg->v_fc_config.vm.hfront_porch *= 2;
266 video_cfg->v_fc_config.vm.hsync_len *= 2;
267 video_cfg->v_fc_config.vm.hback_porch *= 2;
268 }
269 }
270
271 /* DSS_HDMI_CORE_VIDEO_CONFIG */
272 static void hdmi_core_video_config(struct hdmi_core_data *core,
273 const struct hdmi_core_vid_config *cfg)
274 {
275 void __iomem *base = core->base;
276 const struct videomode *vm = &cfg->v_fc_config.vm;
277 unsigned char r = 0;
278 bool vsync_pol, hsync_pol;
279
280 vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
281 hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
282
283 /* Set hsync, vsync and data-enable polarity */
284 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
285 r = FLD_MOD(r, vsync_pol, 6, 6);
286 r = FLD_MOD(r, hsync_pol, 5, 5);
287 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
288 r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
289 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
290 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
291
292 /* set x resolution */
293 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0);
294 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0);
295
296 /* set y resolution */
297 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0);
298 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0);
299
300 /* set horizontal blanking pixels */
301 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
302 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
303
304 /* set vertial blanking pixels */
305 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
306
307 /* set horizontal sync offset */
308 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8,
309 4, 0);
310 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF,
311 7, 0);
312
313 /* set vertical sync offset */
314 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0);
315
316 /* set horizontal sync pulse width */
317 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8),
318 1, 0);
319 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF,
320 7, 0);
321
322 /* set vertical sync pulse width */
323 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0);
324
325 /* select DVI mode */
326 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
327 cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
328
329 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
330 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
331 else
332 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
333 }
334
335 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
336 {
337 void __iomem *base = core->base;
338 int clr_depth = 0; /* 24 bit color depth */
339
340 /* COLOR_DEPTH */
341 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
342 /* BYPASS_EN */
343 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
344 /* PP_EN */
345 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
346 /* YCC422_EN */
347 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
348 /* PP_STUFFING */
349 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
350 /* YCC422_STUFFING */
351 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
352 /* OUTPUT_SELECTOR */
353 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
354 }
355
356 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
357 {
358 int video_mapping = 1; /* for 24 bit color depth */
359
360 /* VIDEO_MAPPING */
361 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
362 }
363
364 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
365 struct hdmi_avi_infoframe *frame)
366 {
367 void __iomem *base = core->base;
368 u8 data[HDMI_INFOFRAME_SIZE(AVI)];
369 u8 *ptr;
370 unsigned int y, a, b, s;
371 unsigned int c, m, r;
372 unsigned int itc, ec, q, sc;
373 unsigned int vic;
374 unsigned int yq, cn, pr;
375
376 hdmi_avi_infoframe_pack(frame, data, sizeof(data));
377
378 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
379 HDMI_INFOFRAME_SIZE(AVI), false);
380
381 ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
382
383 y = (ptr[0] >> 5) & 0x3;
384 a = (ptr[0] >> 4) & 0x1;
385 b = (ptr[0] >> 2) & 0x3;
386 s = (ptr[0] >> 0) & 0x3;
387
388 c = (ptr[1] >> 6) & 0x3;
389 m = (ptr[1] >> 4) & 0x3;
390 r = (ptr[1] >> 0) & 0xf;
391
392 itc = (ptr[2] >> 7) & 0x1;
393 ec = (ptr[2] >> 4) & 0x7;
394 q = (ptr[2] >> 2) & 0x3;
395 sc = (ptr[2] >> 0) & 0x3;
396
397 vic = ptr[3];
398
399 yq = (ptr[4] >> 6) & 0x3;
400 cn = (ptr[4] >> 4) & 0x3;
401 pr = (ptr[4] >> 0) & 0xf;
402
403 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
404 (a << 6) | (s << 4) | (b << 2) | (y << 0));
405
406 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
407 (c << 6) | (m << 4) | (r << 0));
408
409 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
410 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
411
412 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
413
414 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
415 (yq << 2) | (cn << 0));
416
417 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
418 }
419
420 static void hdmi_core_write_csc(struct hdmi_core_data *core,
421 const struct csc_table *csc_coeff)
422 {
423 void __iomem *base = core->base;
424
425 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff->a1 >> 8, 6, 0);
426 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff->a1, 7, 0);
427 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff->a2 >> 8, 6, 0);
428 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff->a2, 7, 0);
429 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff->a3 >> 8, 6, 0);
430 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff->a3, 7, 0);
431 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff->a4 >> 8, 6, 0);
432 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff->a4, 7, 0);
433 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff->b1 >> 8, 6, 0);
434 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff->b1, 7, 0);
435 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff->b2 >> 8, 6, 0);
436 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff->b2, 7, 0);
437 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff->b3 >> 8, 6, 0);
438 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff->b3, 7, 0);
439 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff->b4 >> 8, 6, 0);
440 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff->b4, 7, 0);
441 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff->c1 >> 8, 6, 0);
442 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff->c1, 7, 0);
443 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff->c2 >> 8, 6, 0);
444 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff->c2, 7, 0);
445 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff->c3 >> 8, 6, 0);
446 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff->c3, 7, 0);
447 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff->c4 >> 8, 6, 0);
448 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff->c4, 7, 0);
449
450 /* enable CSC */
451 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
452 }
453
454 static void hdmi_core_configure_range(struct hdmi_core_data *core,
455 enum hdmi_quantization_range range)
456 {
457 static const struct csc_table csc_limited_range = {
458 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32
459 };
460 static const struct csc_table csc_full_range = {
461 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0
462 };
463 const struct csc_table *csc_coeff;
464
465 /* CSC_COLORDEPTH = 24 bits*/
466 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, 0, 7, 4);
467
468 switch (range) {
469 case HDMI_QUANTIZATION_RANGE_FULL:
470 csc_coeff = &csc_full_range;
471 break;
472
473 case HDMI_QUANTIZATION_RANGE_DEFAULT:
474 case HDMI_QUANTIZATION_RANGE_LIMITED:
475 default:
476 csc_coeff = &csc_limited_range;
477 break;
478 }
479
480 hdmi_core_write_csc(core, csc_coeff);
481 }
482
483 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
484 {
485 void __iomem *base = core->base;
486
487 DSSDBG("hdmi_core_enable_video_path\n");
488
489 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
490 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
491 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
492 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
493 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
494 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
495 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
496 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
497 }
498
499 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
500 {
501 void __iomem *base = core->base;
502
503 /* Master IRQ mask */
504 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
505
506 /* Mask all the interrupts in HDMI core */
507
508 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
509 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
510 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
511 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
512
513 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
514 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
515
516 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
517
518 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
519 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
520 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
521
522 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
523
524 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
525
526 /* Clear all the current interrupt bits */
527
528 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
529 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
530 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
531 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
532
533 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
534
535 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
536
537 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
538
539 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
540 }
541
542 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
543 {
544 /* Unmute interrupts */
545 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
546 }
547
548 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
549 {
550 void __iomem *base = core->base;
551
552 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
553 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
554 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
555 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
556 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
557 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
558 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
559 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
560 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
561
562 return 0;
563 }
564
565 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
566 struct hdmi_config *cfg)
567 {
568 struct videomode vm;
569 struct hdmi_video_format video_format;
570 struct hdmi_core_vid_config v_core_cfg;
571 enum hdmi_quantization_range range;
572
573 hdmi_core_mask_interrupts(core);
574
575 if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
576 char vic = cfg->infoframe.video_code;
577
578 /* All CEA modes other than VIC 1 use limited quantization range. */
579 range = vic > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED :
580 HDMI_QUANTIZATION_RANGE_FULL;
581 } else {
582 range = HDMI_QUANTIZATION_RANGE_FULL;
583 }
584
585 hdmi_core_init(&v_core_cfg, cfg);
586
587 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
588
589 hdmi_wp_video_config_timing(wp, &vm);
590
591 /* video config */
592 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
593
594 hdmi_wp_video_config_format(wp, &video_format);
595
596 hdmi_wp_video_config_interface(wp, &vm);
597
598 hdmi_core_configure_range(core, range);
599 cfg->infoframe.quantization_range = range;
600
601 /*
602 * configure core video part, set software reset in the core
603 */
604 v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
605
606 hdmi_core_video_config(core, &v_core_cfg);
607
608 hdmi_core_config_video_packetizer(core);
609 hdmi_core_config_video_sampler(core);
610
611 if (cfg->hdmi_dvi_mode == HDMI_HDMI)
612 hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
613
614 hdmi_core_enable_video_path(core);
615
616 hdmi_core_enable_interrupts(core);
617 }
618
619 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
620 struct hdmi_core_audio_config *cfg)
621 {
622 void __iomem *base = core->base;
623 u8 val;
624
625 /* Mute audio before configuring */
626 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
627
628 /* Set the N parameter */
629 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
630 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
631 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
632
633 /*
634 * CTS manual mode. Automatic mode is not supported when using audio
635 * parallel interface.
636 */
637 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
638 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
639 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
640 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
641
642 /* Layout of Audio Sample Packets: 2-channel or multichannels */
643 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
644 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
645 else
646 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
647
648 /* Configure IEC-609580 Validity bits */
649 /* Channel 0 is valid */
650 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
651 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
652
653 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
654 val = 1;
655 else
656 val = 0;
657
658 /* Channels 1, 2 setting */
659 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
660 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
661 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
662 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
663 /* Channel 3 setting */
664 if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
665 val = 1;
666 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
667 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
668
669 /* Configure IEC-60958 User bits */
670 /* TODO: should be set by user. */
671 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
672
673 /* Configure IEC-60958 Channel Status word */
674 /* CGMSA */
675 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
676 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
677
678 /* Copyright */
679 val = (cfg->iec60958_cfg->status[0] &
680 IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
681 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
682
683 /* Category */
684 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
685 cfg->iec60958_cfg->status[1]);
686
687 /* PCM audio mode */
688 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
689 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
690
691 /* Source number */
692 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
693 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
694
695 /* Channel number right 0 */
696 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
697 /* Channel number right 1*/
698 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
699 /* Channel number right 2 */
700 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
701 /* Channel number right 3*/
702 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
703 /* Channel number left 0 */
704 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
705 /* Channel number left 1*/
706 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
707 /* Channel number left 2 */
708 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
709 /* Channel number left 3*/
710 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
711
712 /* Clock accuracy and sample rate */
713 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
714 cfg->iec60958_cfg->status[3]);
715
716 /* Original sample rate and word length */
717 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
718 cfg->iec60958_cfg->status[4]);
719
720 /* Enable FIFO empty and full interrupts */
721 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
722
723 /* Configure GPA */
724 /* select HBR/SPDIF interfaces */
725 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
726 /* select HBR/SPDIF interfaces */
727 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
728 /* enable two channels in GPA */
729 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
730 } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
731 /* select HBR/SPDIF interfaces */
732 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
733 /* enable six channels in GPA */
734 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
735 } else {
736 /* select HBR/SPDIF interfaces */
737 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
738 /* enable eight channels in GPA */
739 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
740 }
741
742 /* disable HBR */
743 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
744 /* enable PCUV */
745 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
746 /* enable GPA FIFO full and empty mask */
747 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
748 /* set polarity of GPA FIFO empty interrupts */
749 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
750
751 /* unmute audio */
752 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
753 }
754
755 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
756 struct snd_cea_861_aud_if *info_aud)
757 {
758 void __iomem *base = core->base;
759
760 /* channel count and coding type fields in AUDICONF0 are swapped */
761 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
762 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
763 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
764
765 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
766 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
767 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
768 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
769 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
770 }
771
772 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
773 struct omap_dss_audio *audio, u32 pclk)
774 {
775 struct hdmi_audio_format audio_format;
776 struct hdmi_audio_dma audio_dma;
777 struct hdmi_core_audio_config core_cfg;
778 int n, cts, channel_count;
779 unsigned int fs_nr;
780 bool word_length_16b = false;
781
782 if (!audio || !audio->iec || !audio->cea || !core)
783 return -EINVAL;
784
785 core_cfg.iec60958_cfg = audio->iec;
786
787 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
788 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
789 word_length_16b = true;
790
791 /* only 16-bit word length supported atm */
792 if (!word_length_16b)
793 return -EINVAL;
794
795 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
796 case IEC958_AES3_CON_FS_32000:
797 fs_nr = 32000;
798 break;
799 case IEC958_AES3_CON_FS_44100:
800 fs_nr = 44100;
801 break;
802 case IEC958_AES3_CON_FS_48000:
803 fs_nr = 48000;
804 break;
805 case IEC958_AES3_CON_FS_88200:
806 fs_nr = 88200;
807 break;
808 case IEC958_AES3_CON_FS_96000:
809 fs_nr = 96000;
810 break;
811 case IEC958_AES3_CON_FS_176400:
812 fs_nr = 176400;
813 break;
814 case IEC958_AES3_CON_FS_192000:
815 fs_nr = 192000;
816 break;
817 default:
818 return -EINVAL;
819 }
820
821 hdmi_compute_acr(pclk, fs_nr, &n, &cts);
822 core_cfg.n = n;
823 core_cfg.cts = cts;
824
825 /* Audio channels settings */
826 channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
827 + 1;
828
829 if (channel_count == 2)
830 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
831 else if (channel_count == 6)
832 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
833 else
834 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
835
836 /* DMA settings */
837 if (word_length_16b)
838 audio_dma.transfer_size = 0x10;
839 else
840 audio_dma.transfer_size = 0x20;
841 audio_dma.block_size = 0xC0;
842 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
843 audio_dma.fifo_threshold = 0x20; /* in number of samples */
844
845 /* audio FIFO format settings for 16-bit samples*/
846 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
847 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
848 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
849 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
850
851 /* only LPCM atm */
852 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
853
854 /* only allowed option */
855 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
856
857 /* disable start/stop signals of IEC 60958 blocks */
858 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
859
860 /* configure DMA and audio FIFO format*/
861 hdmi_wp_audio_config_dma(wp, &audio_dma);
862 hdmi_wp_audio_config_format(wp, &audio_format);
863
864 /* configure the core */
865 hdmi5_core_audio_config(core, &core_cfg);
866
867 /* configure CEA 861 audio infoframe */
868 hdmi5_core_audio_infoframe_cfg(core, audio->cea);
869
870 return 0;
871 }
872
873 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
874 {
875 struct resource *res;
876
877 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
878 core->base = devm_ioremap_resource(&pdev->dev, res);
879 if (IS_ERR(core->base))
880 return PTR_ERR(core->base);
881
882 return 0;
883 }
Linux with added FPC-III support