drivers/gpu/drm/omapdrm/dss/omapdss.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
   4  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
   5  */
   6
   7 #ifndef __OMAP_DRM_DSS_H
   8 #define __OMAP_DRM_DSS_H
   9
  10 #include <linux/list.h>
  11 #include <linux/device.h>
  12 #include <linux/interrupt.h>
  13 #include <video/videomode.h>
  14 #include <linux/platform_data/omapdss.h>
  15 #include <uapi/drm/drm_mode.h>
  16 #include <drm/drm_crtc.h>
  17
  18 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
  19 #define DISPC_IRQ_VSYNC                 (1 << 1)
  20 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  21 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  22 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  23 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  24 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  25 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  26 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  27 #define DISPC_IRQ_OCP_ERR               (1 << 9)
  28 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  29 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  30 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  31 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  32 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
  33 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  34 #define DISPC_IRQ_WAKEUP                (1 << 16)
  35 #define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  36 #define DISPC_IRQ_VSYNC2                (1 << 18)
  37 #define DISPC_IRQ_VID3_END_WIN          (1 << 19)
  38 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW   (1 << 20)
  39 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  40 #define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  41 #define DISPC_IRQ_FRAMEDONEWB           (1 << 23)
  42 #define DISPC_IRQ_FRAMEDONETV           (1 << 24)
  43 #define DISPC_IRQ_WBBUFFEROVERFLOW      (1 << 25)
  44 #define DISPC_IRQ_WBUNCOMPLETEERROR     (1 << 26)
  45 #define DISPC_IRQ_SYNC_LOST3            (1 << 27)
  46 #define DISPC_IRQ_VSYNC3                (1 << 28)
  47 #define DISPC_IRQ_ACBIAS_COUNT_STAT3    (1 << 29)
  48 #define DISPC_IRQ_FRAMEDONE3            (1 << 30)
  49
  50 struct dss_device;
  51 struct omap_drm_private;
  52 struct omap_dss_device;
  53 struct dispc_device;
  54 struct dss_device;
  55 struct dss_lcd_mgr_config;
  56 struct snd_aes_iec958;
  57 struct snd_cea_861_aud_if;
  58 struct hdmi_avi_infoframe;
  59 struct drm_connector;
  60
  61 enum omap_display_type {
  62         OMAP_DISPLAY_TYPE_NONE          = 0,
  63         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  64         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  65         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  66         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  67         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  68         OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  69         OMAP_DISPLAY_TYPE_DVI           = 1 << 6,
  70 };
  71
  72 enum omap_plane_id {
  73         OMAP_DSS_GFX    = 0,
  74         OMAP_DSS_VIDEO1 = 1,
  75         OMAP_DSS_VIDEO2 = 2,
  76         OMAP_DSS_VIDEO3 = 3,
  77         OMAP_DSS_WB     = 4,
  78 };
  79
  80 enum omap_channel {
  81         OMAP_DSS_CHANNEL_LCD    = 0,
  82         OMAP_DSS_CHANNEL_DIGIT  = 1,
  83         OMAP_DSS_CHANNEL_LCD2   = 2,
  84         OMAP_DSS_CHANNEL_LCD3   = 3,
  85         OMAP_DSS_CHANNEL_WB     = 4,
  86 };
  87
  88 enum omap_color_mode {
  89         _UNUSED_,
  90 };
  91
  92 enum omap_dss_load_mode {
  93         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
  94         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
  95         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
  96         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
  97 };
  98
  99 enum omap_dss_trans_key_type {
 100         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 101         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 102 };
 103
 104 enum omap_dss_signal_level {
 105         OMAPDSS_SIG_ACTIVE_LOW,
 106         OMAPDSS_SIG_ACTIVE_HIGH,
 107 };
 108
 109 enum omap_dss_signal_edge {
 110         OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 111         OMAPDSS_DRIVE_SIG_RISING_EDGE,
 112 };
 113
 114 enum omap_dss_venc_type {
 115         OMAP_DSS_VENC_TYPE_COMPOSITE,
 116         OMAP_DSS_VENC_TYPE_SVIDEO,
 117 };
 118
 119 enum omap_dss_dsi_pixel_format {
 120         OMAP_DSS_DSI_FMT_RGB888,
 121         OMAP_DSS_DSI_FMT_RGB666,
 122         OMAP_DSS_DSI_FMT_RGB666_PACKED,
 123         OMAP_DSS_DSI_FMT_RGB565,
 124 };
 125
 126 enum omap_dss_dsi_mode {
 127         OMAP_DSS_DSI_CMD_MODE = 0,
 128         OMAP_DSS_DSI_VIDEO_MODE,
 129 };
 130
 131 enum omap_display_caps {
 132         OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 133         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 134 };
 135
 136 enum omap_dss_display_state {
 137         OMAP_DSS_DISPLAY_DISABLED = 0,
 138         OMAP_DSS_DISPLAY_ACTIVE,
 139 };
 140
 141 enum omap_dss_rotation_type {
 142         OMAP_DSS_ROT_NONE       = 0,
 143         OMAP_DSS_ROT_TILER      = 1 << 0,
 144 };
 145
 146 enum omap_overlay_caps {
 147         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 148         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
 149         OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
 150         OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
 151         OMAP_DSS_OVL_CAP_POS = 1 << 4,
 152         OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
 153 };
 154
 155 enum omap_dss_output_id {
 156         OMAP_DSS_OUTPUT_DPI     = 1 << 0,
 157         OMAP_DSS_OUTPUT_DBI     = 1 << 1,
 158         OMAP_DSS_OUTPUT_SDI     = 1 << 2,
 159         OMAP_DSS_OUTPUT_DSI1    = 1 << 3,
 160         OMAP_DSS_OUTPUT_DSI2    = 1 << 4,
 161         OMAP_DSS_OUTPUT_VENC    = 1 << 5,
 162         OMAP_DSS_OUTPUT_HDMI    = 1 << 6,
 163 };
 164
 165 /* DSI */
 166
 167 enum omap_dss_dsi_trans_mode {
 168         /* Sync Pulses: both sync start and end packets sent */
 169         OMAP_DSS_DSI_PULSE_MODE,
 170         /* Sync Events: only sync start packets sent */
 171         OMAP_DSS_DSI_EVENT_MODE,
 172         /* Burst: only sync start packets sent, pixels are time compressed */
 173         OMAP_DSS_DSI_BURST_MODE,
 174 };
 175
 176 struct omap_dss_dsi_videomode_timings {
 177         unsigned long hsclk;
 178
 179         unsigned int ndl;
 180         unsigned int bitspp;
 181
 182         /* pixels */
 183         u16 hact;
 184         /* lines */
 185         u16 vact;
 186
 187         /* DSI video mode blanking data */
 188         /* Unit: byte clock cycles */
 189         u16 hss;
 190         u16 hsa;
 191         u16 hse;
 192         u16 hfp;
 193         u16 hbp;
 194         /* Unit: line clocks */
 195         u16 vsa;
 196         u16 vfp;
 197         u16 vbp;
 198
 199         /* DSI blanking modes */
 200         int blanking_mode;
 201         int hsa_blanking_mode;
 202         int hbp_blanking_mode;
 203         int hfp_blanking_mode;
 204
 205         enum omap_dss_dsi_trans_mode trans_mode;
 206
 207         bool ddr_clk_always_on;
 208         int window_sync;
 209 };
 210
 211 struct omap_dss_dsi_config {
 212         enum omap_dss_dsi_mode mode;
 213         enum omap_dss_dsi_pixel_format pixel_format;
 214         const struct videomode *vm;
 215
 216         unsigned long hs_clk_min, hs_clk_max;
 217         unsigned long lp_clk_min, lp_clk_max;
 218
 219         bool ddr_clk_always_on;
 220         enum omap_dss_dsi_trans_mode trans_mode;
 221 };
 222
 223 struct omap_dss_cpr_coefs {
 224         s16 rr, rg, rb;
 225         s16 gr, gg, gb;
 226         s16 br, bg, bb;
 227 };
 228
 229 struct omap_overlay_info {
 230         dma_addr_t paddr;
 231         dma_addr_t p_uv_addr;  /* for NV12 format */
 232         u16 screen_width;
 233         u16 width;
 234         u16 height;
 235         u32 fourcc;
 236         u8 rotation;
 237         enum omap_dss_rotation_type rotation_type;
 238
 239         u16 pos_x;
 240         u16 pos_y;
 241         u16 out_width;  /* if 0, out_width == width */
 242         u16 out_height; /* if 0, out_height == height */
 243         u8 global_alpha;
 244         u8 pre_mult_alpha;
 245         u8 zorder;
 246 };
 247
 248 struct omap_overlay_manager_info {
 249         u32 default_color;
 250
 251         enum omap_dss_trans_key_type trans_key_type;
 252         u32 trans_key;
 253         bool trans_enabled;
 254
 255         bool partial_alpha_enabled;
 256
 257         bool cpr_enable;
 258         struct omap_dss_cpr_coefs cpr_coefs;
 259 };
 260
 261 /* 22 pins means 1 clk lane and 10 data lanes */
 262 #define OMAP_DSS_MAX_DSI_PINS 22
 263
 264 struct omap_dsi_pin_config {
 265         int num_pins;
 266         /*
 267          * pin numbers in the following order:
 268          * clk+, clk-
 269          * data1+, data1-
 270          * data2+, data2-
 271          * ...
 272          */
 273         int pins[OMAP_DSS_MAX_DSI_PINS];
 274 };
 275
 276 struct omap_dss_writeback_info {
 277         u32 paddr;
 278         u32 p_uv_addr;
 279         u16 buf_width;
 280         u16 width;
 281         u16 height;
 282         u32 fourcc;
 283         u8 rotation;
 284         enum omap_dss_rotation_type rotation_type;
 285         u8 pre_mult_alpha;
 286 };
 287
 288 struct omapdss_dsi_ops {
 289         void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
 290                         bool enter_ulps);
 291
 292         /* bus configuration */
 293         int (*set_config)(struct omap_dss_device *dssdev,
 294                         const struct omap_dss_dsi_config *cfg);
 295         int (*configure_pins)(struct omap_dss_device *dssdev,
 296                         const struct omap_dsi_pin_config *pin_cfg);
 297
 298         void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
 299                         bool enable);
 300         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 301
 302         int (*update)(struct omap_dss_device *dssdev, int channel,
 303                         void (*callback)(int, void *), void *data);
 304
 305         void (*bus_lock)(struct omap_dss_device *dssdev);
 306         void (*bus_unlock)(struct omap_dss_device *dssdev);
 307
 308         int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
 309         void (*disable_video_output)(struct omap_dss_device *dssdev,
 310                         int channel);
 311
 312         int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
 313         int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
 314                         int vc_id);
 315         void (*release_vc)(struct omap_dss_device *dssdev, int channel);
 316
 317         /* data transfer */
 318         int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
 319                         u8 *data, int len);
 320         int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
 321                         u8 *data, int len);
 322         int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 323                         u8 *data, int len);
 324
 325         int (*gen_write)(struct omap_dss_device *dssdev, int channel,
 326                         u8 *data, int len);
 327         int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
 328                         u8 *data, int len);
 329         int (*gen_read)(struct omap_dss_device *dssdev, int channel,
 330                         u8 *reqdata, int reqlen,
 331                         u8 *data, int len);
 332
 333         int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
 334
 335         int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
 336                         int channel, u16 plen);
 337 };
 338
 339 struct omap_dss_device_ops {
 340         int (*connect)(struct omap_dss_device *dssdev,
 341                         struct omap_dss_device *dst);
 342         void (*disconnect)(struct omap_dss_device *dssdev,
 343                         struct omap_dss_device *dst);
 344
 345         void (*enable)(struct omap_dss_device *dssdev);
 346         void (*disable)(struct omap_dss_device *dssdev);
 347
 348         int (*check_timings)(struct omap_dss_device *dssdev,
 349                              struct drm_display_mode *mode);
 350
 351         int (*get_modes)(struct omap_dss_device *dssdev,
 352                          struct drm_connector *connector);
 353
 354         const struct omapdss_dsi_ops dsi;
 355 };
 356
 357 /**
 358  * enum omap_dss_device_ops_flag - Indicates which device ops are supported
 359  * @OMAP_DSS_DEVICE_OP_MODES: The device supports reading modes
 360  */
 361 enum omap_dss_device_ops_flag {
 362         OMAP_DSS_DEVICE_OP_MODES = BIT(3),
 363 };
 364
 365 struct omap_dss_device {
 366         struct device *dev;
 367
 368         struct module *owner;
 369
 370         struct dss_device *dss;
 371         struct omap_dss_device *next;
 372         struct drm_bridge *bridge;
 373         struct drm_bridge *next_bridge;
 374         struct drm_panel *panel;
 375
 376         struct list_head list;
 377
 378         /*
 379          * DSS type that this device generates (for DSS internal devices) or
 380          * requires (for external encoders, connectors and panels). Must be a
 381          * non-zero (different than OMAP_DISPLAY_TYPE_NONE) value.
 382          */
 383         enum omap_display_type type;
 384
 385         /*
 386          * True if the device is a display (panel or connector) at the end of
 387          * the pipeline, false otherwise.
 388          */
 389         bool display;
 390
 391         const char *name;
 392
 393         const struct omap_dss_driver *driver;
 394         const struct omap_dss_device_ops *ops;
 395         unsigned long ops_flags;
 396         u32 bus_flags;
 397
 398         enum omap_display_caps caps;
 399
 400         enum omap_dss_display_state state;
 401
 402         /* OMAP DSS output specific fields */
 403
 404         /* DISPC channel for this output */
 405         enum omap_channel dispc_channel;
 406
 407         /* output instance */
 408         enum omap_dss_output_id id;
 409
 410         /* port number in DT */
 411         unsigned int of_port;
 412 };
 413
 414 struct omap_dss_driver {
 415         int (*update)(struct omap_dss_device *dssdev,
 416                                u16 x, u16 y, u16 w, u16 h);
 417         int (*sync)(struct omap_dss_device *dssdev);
 418
 419         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 420         int (*get_te)(struct omap_dss_device *dssdev);
 421
 422         int (*memory_read)(struct omap_dss_device *dssdev,
 423                         void *buf, size_t size,
 424                         u16 x, u16 y, u16 w, u16 h);
 425 };
 426
 427 struct dss_device *omapdss_get_dss(void);
 428 void omapdss_set_dss(struct dss_device *dss);
 429 static inline bool omapdss_is_initialized(void)
 430 {
 431         return !!omapdss_get_dss();
 432 }
 433
 434 void omapdss_display_init(struct omap_dss_device *dssdev);
 435 int omapdss_display_get_modes(struct drm_connector *connector,
 436                               const struct videomode *vm);
 437
 438 void omapdss_device_register(struct omap_dss_device *dssdev);
 439 void omapdss_device_unregister(struct omap_dss_device *dssdev);
 440 struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev);
 441 void omapdss_device_put(struct omap_dss_device *dssdev);
 442 struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node);
 443 int omapdss_device_connect(struct dss_device *dss,
 444                            struct omap_dss_device *src,
 445                            struct omap_dss_device *dst);
 446 void omapdss_device_disconnect(struct omap_dss_device *src,
 447                                struct omap_dss_device *dst);
 448 void omapdss_device_enable(struct omap_dss_device *dssdev);
 449 void omapdss_device_disable(struct omap_dss_device *dssdev);
 450
 451 int omap_dss_get_num_overlay_managers(void);
 452
 453 int omap_dss_get_num_overlays(void);
 454
 455 #define for_each_dss_output(d) \
 456         while ((d = omapdss_device_next_output(d)) != NULL)
 457 struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from);
 458 int omapdss_device_init_output(struct omap_dss_device *out,
 459                                struct drm_bridge *local_bridge);
 460 void omapdss_device_cleanup_output(struct omap_dss_device *out);
 461
 462 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 463 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 464 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 465
 466 int omapdss_compat_init(void);
 467 void omapdss_compat_uninit(void);
 468
 469 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
 470 {
 471         return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
 472 }
 473
 474 enum dss_writeback_channel {
 475         DSS_WB_LCD1_MGR =       0,
 476         DSS_WB_LCD2_MGR =       1,
 477         DSS_WB_TV_MGR =         2,
 478         DSS_WB_OVL0 =           3,
 479         DSS_WB_OVL1 =           4,
 480         DSS_WB_OVL2 =           5,
 481         DSS_WB_OVL3 =           6,
 482         DSS_WB_LCD3_MGR =       7,
 483 };
 484
 485 struct dss_mgr_ops {
 486         void (*start_update)(struct omap_drm_private *priv,
 487                              enum omap_channel channel);
 488         int (*enable)(struct omap_drm_private *priv,
 489                       enum omap_channel channel);
 490         void (*disable)(struct omap_drm_private *priv,
 491                         enum omap_channel channel);
 492         void (*set_timings)(struct omap_drm_private *priv,
 493                             enum omap_channel channel,
 494                             const struct videomode *vm);
 495         void (*set_lcd_config)(struct omap_drm_private *priv,
 496                                enum omap_channel channel,
 497                                const struct dss_lcd_mgr_config *config);
 498         int (*register_framedone_handler)(struct omap_drm_private *priv,
 499                         enum omap_channel channel,
 500                         void (*handler)(void *), void *data);
 501         void (*unregister_framedone_handler)(struct omap_drm_private *priv,
 502                         enum omap_channel channel,
 503                         void (*handler)(void *), void *data);
 504 };
 505
 506 int dss_install_mgr_ops(struct dss_device *dss,
 507                         const struct dss_mgr_ops *mgr_ops,
 508                         struct omap_drm_private *priv);
 509 void dss_uninstall_mgr_ops(struct dss_device *dss);
 510
 511 void dss_mgr_set_timings(struct omap_dss_device *dssdev,
 512                 const struct videomode *vm);
 513 void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
 514                 const struct dss_lcd_mgr_config *config);
 515 int dss_mgr_enable(struct omap_dss_device *dssdev);
 516 void dss_mgr_disable(struct omap_dss_device *dssdev);
 517 void dss_mgr_start_update(struct omap_dss_device *dssdev);
 518 int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
 519                 void (*handler)(void *), void *data);
 520 void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
 521                 void (*handler)(void *), void *data);
 522
 523 /* dispc ops */
 524
 525 struct dispc_ops {
 526         u32 (*read_irqstatus)(struct dispc_device *dispc);
 527         void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask);
 528         void (*write_irqenable)(struct dispc_device *dispc, u32 mask);
 529
 530         int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler,
 531                            void *dev_id);
 532         void (*free_irq)(struct dispc_device *dispc, void *dev_id);
 533
 534         int (*runtime_get)(struct dispc_device *dispc);
 535         void (*runtime_put)(struct dispc_device *dispc);
 536
 537         int (*get_num_ovls)(struct dispc_device *dispc);
 538         int (*get_num_mgrs)(struct dispc_device *dispc);
 539
 540         u32 (*get_memory_bandwidth_limit)(struct dispc_device *dispc);
 541
 542         void (*mgr_enable)(struct dispc_device *dispc,
 543                            enum omap_channel channel, bool enable);
 544         bool (*mgr_is_enabled)(struct dispc_device *dispc,
 545                                enum omap_channel channel);
 546         u32 (*mgr_get_vsync_irq)(struct dispc_device *dispc,
 547                                  enum omap_channel channel);
 548         u32 (*mgr_get_framedone_irq)(struct dispc_device *dispc,
 549                                      enum omap_channel channel);
 550         u32 (*mgr_get_sync_lost_irq)(struct dispc_device *dispc,
 551                                      enum omap_channel channel);
 552         bool (*mgr_go_busy)(struct dispc_device *dispc,
 553                             enum omap_channel channel);
 554         void (*mgr_go)(struct dispc_device *dispc, enum omap_channel channel);
 555         void (*mgr_set_lcd_config)(struct dispc_device *dispc,
 556                                    enum omap_channel channel,
 557                                    const struct dss_lcd_mgr_config *config);
 558         int (*mgr_check_timings)(struct dispc_device *dispc,
 559                                  enum omap_channel channel,
 560                                  const struct videomode *vm);
 561         void (*mgr_set_timings)(struct dispc_device *dispc,
 562                                 enum omap_channel channel,
 563                                 const struct videomode *vm);
 564         void (*mgr_setup)(struct dispc_device *dispc, enum omap_channel channel,
 565                           const struct omap_overlay_manager_info *info);
 566         u32 (*mgr_gamma_size)(struct dispc_device *dispc,
 567                               enum omap_channel channel);
 568         void (*mgr_set_gamma)(struct dispc_device *dispc,
 569                               enum omap_channel channel,
 570                               const struct drm_color_lut *lut,
 571                               unsigned int length);
 572
 573         int (*ovl_enable)(struct dispc_device *dispc, enum omap_plane_id plane,
 574                           bool enable);
 575         int (*ovl_setup)(struct dispc_device *dispc, enum omap_plane_id plane,
 576                          const struct omap_overlay_info *oi,
 577                          const struct videomode *vm, bool mem_to_mem,
 578                          enum omap_channel channel);
 579
 580         const u32 *(*ovl_get_color_modes)(struct dispc_device *dispc,
 581                                           enum omap_plane_id plane);
 582
 583         u32 (*wb_get_framedone_irq)(struct dispc_device *dispc);
 584         int (*wb_setup)(struct dispc_device *dispc,
 585                 const struct omap_dss_writeback_info *wi,
 586                 bool mem_to_mem, const struct videomode *vm,
 587                 enum dss_writeback_channel channel_in);
 588         bool (*has_writeback)(struct dispc_device *dispc);
 589         bool (*wb_go_busy)(struct dispc_device *dispc);
 590         void (*wb_go)(struct dispc_device *dispc);
 591 };
 592
 593 struct dispc_device *dispc_get_dispc(struct dss_device *dss);
 594 const struct dispc_ops *dispc_get_ops(struct dss_device *dss);
 595
 596 bool omapdss_stack_is_ready(void);
 597 void omapdss_gather_components(struct device *dev);
 598
 599 #endif /* __OMAP_DRM_DSS_H */