1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
7 #define DSS_SUBSYS_NAME "SDI"
9 #include <linux/delay.h>
10 #include <linux/err.h>
11 #include <linux/export.h>
12 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/string.h>
18 #include <drm/drm_bridge.h>
24 struct platform_device
*pdev
;
25 struct dss_device
*dss
;
28 struct regulator
*vdds_sdi_reg
;
30 struct dss_lcd_mgr_config mgr_config
;
31 unsigned long pixelclock
;
34 struct omap_dss_device output
;
35 struct drm_bridge bridge
;
38 #define drm_bridge_to_sdi(bridge) \
39 container_of(bridge, struct sdi_device, bridge)
41 struct sdi_clk_calc_ctx
{
42 struct sdi_device
*sdi
;
43 unsigned long pck_min
, pck_max
;
46 struct dispc_clock_info dispc_cinfo
;
49 static bool dpi_calc_dispc_cb(int lckd
, int pckd
, unsigned long lck
,
50 unsigned long pck
, void *data
)
52 struct sdi_clk_calc_ctx
*ctx
= data
;
54 ctx
->dispc_cinfo
.lck_div
= lckd
;
55 ctx
->dispc_cinfo
.pck_div
= pckd
;
56 ctx
->dispc_cinfo
.lck
= lck
;
57 ctx
->dispc_cinfo
.pck
= pck
;
62 static bool dpi_calc_dss_cb(unsigned long fck
, void *data
)
64 struct sdi_clk_calc_ctx
*ctx
= data
;
68 return dispc_div_calc(ctx
->sdi
->dss
->dispc
, fck
,
69 ctx
->pck_min
, ctx
->pck_max
,
70 dpi_calc_dispc_cb
, ctx
);
73 static int sdi_calc_clock_div(struct sdi_device
*sdi
, unsigned long pclk
,
75 struct dispc_clock_info
*dispc_cinfo
)
78 struct sdi_clk_calc_ctx ctx
;
81 * DSS fclk gives us very few possibilities, so finding a good pixel
82 * clock may not be possible. We try multiple times to find the clock,
83 * each time widening the pixel clock range we look for, up to
87 for (i
= 0; i
< 10; ++i
) {
90 memset(&ctx
, 0, sizeof(ctx
));
94 if (pclk
> 1000 * i
* i
* i
)
95 ctx
.pck_min
= max(pclk
- 1000 * i
* i
* i
, 0lu);
98 ctx
.pck_max
= pclk
+ 1000 * i
* i
* i
;
100 ok
= dss_div_calc(sdi
->dss
, pclk
, ctx
.pck_min
,
101 dpi_calc_dss_cb
, &ctx
);
104 *dispc_cinfo
= ctx
.dispc_cinfo
;
112 static void sdi_config_lcd_manager(struct sdi_device
*sdi
)
114 sdi
->mgr_config
.io_pad_mode
= DSS_IO_PAD_MODE_BYPASS
;
116 sdi
->mgr_config
.stallmode
= false;
117 sdi
->mgr_config
.fifohandcheck
= false;
119 sdi
->mgr_config
.video_port_width
= 24;
120 sdi
->mgr_config
.lcden_sig_polarity
= 1;
122 dss_mgr_set_lcd_config(&sdi
->output
, &sdi
->mgr_config
);
125 /* -----------------------------------------------------------------------------
126 * DRM Bridge Operations
129 static int sdi_bridge_attach(struct drm_bridge
*bridge
,
130 enum drm_bridge_attach_flags flags
)
132 struct sdi_device
*sdi
= drm_bridge_to_sdi(bridge
);
134 if (!(flags
& DRM_BRIDGE_ATTACH_NO_CONNECTOR
))
137 return drm_bridge_attach(bridge
->encoder
, sdi
->output
.next_bridge
,
141 static enum drm_mode_status
142 sdi_bridge_mode_valid(struct drm_bridge
*bridge
,
143 const struct drm_display_info
*info
,
144 const struct drm_display_mode
*mode
)
146 struct sdi_device
*sdi
= drm_bridge_to_sdi(bridge
);
147 unsigned long pixelclock
= mode
->clock
* 1000;
148 struct dispc_clock_info dispc_cinfo
;
155 ret
= sdi_calc_clock_div(sdi
, pixelclock
, &fck
, &dispc_cinfo
);
157 return MODE_CLOCK_RANGE
;
162 static bool sdi_bridge_mode_fixup(struct drm_bridge
*bridge
,
163 const struct drm_display_mode
*mode
,
164 struct drm_display_mode
*adjusted_mode
)
166 struct sdi_device
*sdi
= drm_bridge_to_sdi(bridge
);
167 unsigned long pixelclock
= mode
->clock
* 1000;
168 struct dispc_clock_info dispc_cinfo
;
173 ret
= sdi_calc_clock_div(sdi
, pixelclock
, &fck
, &dispc_cinfo
);
177 pck
= fck
/ dispc_cinfo
.lck_div
/ dispc_cinfo
.pck_div
;
179 if (pck
!= pixelclock
)
180 dev_dbg(&sdi
->pdev
->dev
,
181 "pixel clock adjusted from %lu Hz to %lu Hz\n",
184 adjusted_mode
->clock
= pck
/ 1000;
189 static void sdi_bridge_mode_set(struct drm_bridge
*bridge
,
190 const struct drm_display_mode
*mode
,
191 const struct drm_display_mode
*adjusted_mode
)
193 struct sdi_device
*sdi
= drm_bridge_to_sdi(bridge
);
195 sdi
->pixelclock
= adjusted_mode
->clock
* 1000;
198 static void sdi_bridge_enable(struct drm_bridge
*bridge
)
200 struct sdi_device
*sdi
= drm_bridge_to_sdi(bridge
);
201 struct dispc_clock_info dispc_cinfo
;
205 r
= regulator_enable(sdi
->vdds_sdi_reg
);
209 r
= dispc_runtime_get(sdi
->dss
->dispc
);
213 r
= sdi_calc_clock_div(sdi
, sdi
->pixelclock
, &fck
, &dispc_cinfo
);
215 goto err_calc_clock_div
;
217 sdi
->mgr_config
.clock_info
= dispc_cinfo
;
219 r
= dss_set_fck_rate(sdi
->dss
, fck
);
221 goto err_set_dss_clock_div
;
223 sdi_config_lcd_manager(sdi
);
226 * LCLK and PCLK divisors are located in shadow registers, and we
227 * normally write them to DISPC registers when enabling the output.
228 * However, SDI uses pck-free as source clock for its PLL, and pck-free
229 * is affected by the divisors. And as we need the PLL before enabling
230 * the output, we need to write the divisors early.
232 * It seems just writing to the DISPC register is enough, and we don't
233 * need to care about the shadow register mechanism for pck-free. The
234 * exact reason for this is unknown.
236 dispc_mgr_set_clock_div(sdi
->dss
->dispc
, sdi
->output
.dispc_channel
,
237 &sdi
->mgr_config
.clock_info
);
239 dss_sdi_init(sdi
->dss
, sdi
->datapairs
);
240 r
= dss_sdi_enable(sdi
->dss
);
245 r
= dss_mgr_enable(&sdi
->output
);
252 dss_sdi_disable(sdi
->dss
);
254 err_set_dss_clock_div
:
256 dispc_runtime_put(sdi
->dss
->dispc
);
258 regulator_disable(sdi
->vdds_sdi_reg
);
261 static void sdi_bridge_disable(struct drm_bridge
*bridge
)
263 struct sdi_device
*sdi
= drm_bridge_to_sdi(bridge
);
265 dss_mgr_disable(&sdi
->output
);
267 dss_sdi_disable(sdi
->dss
);
269 dispc_runtime_put(sdi
->dss
->dispc
);
271 regulator_disable(sdi
->vdds_sdi_reg
);
274 static const struct drm_bridge_funcs sdi_bridge_funcs
= {
275 .attach
= sdi_bridge_attach
,
276 .mode_valid
= sdi_bridge_mode_valid
,
277 .mode_fixup
= sdi_bridge_mode_fixup
,
278 .mode_set
= sdi_bridge_mode_set
,
279 .enable
= sdi_bridge_enable
,
280 .disable
= sdi_bridge_disable
,
283 static void sdi_bridge_init(struct sdi_device
*sdi
)
285 sdi
->bridge
.funcs
= &sdi_bridge_funcs
;
286 sdi
->bridge
.of_node
= sdi
->pdev
->dev
.of_node
;
287 sdi
->bridge
.type
= DRM_MODE_CONNECTOR_LVDS
;
289 drm_bridge_add(&sdi
->bridge
);
292 static void sdi_bridge_cleanup(struct sdi_device
*sdi
)
294 drm_bridge_remove(&sdi
->bridge
);
297 /* -----------------------------------------------------------------------------
298 * Initialisation and Cleanup
301 static int sdi_init_output(struct sdi_device
*sdi
)
303 struct omap_dss_device
*out
= &sdi
->output
;
306 sdi_bridge_init(sdi
);
308 out
->dev
= &sdi
->pdev
->dev
;
309 out
->id
= OMAP_DSS_OUTPUT_SDI
;
310 out
->type
= OMAP_DISPLAY_TYPE_SDI
;
312 out
->dispc_channel
= OMAP_DSS_CHANNEL_LCD
;
313 /* We have SDI only on OMAP3, where it's on port 1 */
315 out
->owner
= THIS_MODULE
;
316 out
->bus_flags
= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
/* 15.5.9.1.2 */
317 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE
;
319 r
= omapdss_device_init_output(out
, &sdi
->bridge
);
321 sdi_bridge_cleanup(sdi
);
325 omapdss_device_register(out
);
330 static void sdi_uninit_output(struct sdi_device
*sdi
)
332 omapdss_device_unregister(&sdi
->output
);
333 omapdss_device_cleanup_output(&sdi
->output
);
335 sdi_bridge_cleanup(sdi
);
338 int sdi_init_port(struct dss_device
*dss
, struct platform_device
*pdev
,
339 struct device_node
*port
)
341 struct sdi_device
*sdi
;
342 struct device_node
*ep
;
346 sdi
= kzalloc(sizeof(*sdi
), GFP_KERNEL
);
350 ep
= of_get_next_child(port
, NULL
);
356 r
= of_property_read_u32(ep
, "datapairs", &datapairs
);
359 DSSERR("failed to parse datapairs\n");
363 sdi
->datapairs
= datapairs
;
369 sdi
->vdds_sdi_reg
= devm_regulator_get(&pdev
->dev
, "vdds_sdi");
370 if (IS_ERR(sdi
->vdds_sdi_reg
)) {
371 r
= PTR_ERR(sdi
->vdds_sdi_reg
);
372 if (r
!= -EPROBE_DEFER
)
373 DSSERR("can't get VDDS_SDI regulator\n");
377 r
= sdi_init_output(sdi
);
389 void sdi_uninit_port(struct device_node
*port
)
391 struct sdi_device
*sdi
= port
->data
;
396 sdi_uninit_output(sdi
);