drivers/gpu/drm/panel/panel-feixin-k101-im2ba02.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019-2020 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #include <linux/gpio/consumer.h>
   7 #include <linux/delay.h>
   8 #include <linux/mod_devicetable.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/regulator/consumer.h>
  12
  13 #include <drm/drm_mipi_dsi.h>
  14 #include <drm/drm_modes.h>
  15 #include <drm/drm_panel.h>
  16
  17 #define K101_IM2BA02_INIT_CMD_LEN       2
  18
  19 static const char * const regulator_names[] = {
  20         "dvdd",
  21         "avdd",
  22         "cvdd"
  23 };
  24
  25 struct k101_im2ba02 {
  26         struct drm_panel        panel;
  27         struct mipi_dsi_device  *dsi;
  28
  29         struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)];
  30         struct gpio_desc        *reset;
  31 };
  32
  33 static inline struct k101_im2ba02 *panel_to_k101_im2ba02(struct drm_panel *panel)
  34 {
  35         return container_of(panel, struct k101_im2ba02, panel);
  36 }
  37
  38 struct k101_im2ba02_init_cmd {
  39         u8 data[K101_IM2BA02_INIT_CMD_LEN];
  40 };
  41
  42 static const struct k101_im2ba02_init_cmd k101_im2ba02_init_cmds[] = {
  43         /* Switch to page 0 */
  44         { .data = { 0xE0, 0x00 } },
  45
  46         /* Seems to be some password */
  47         { .data = { 0xE1, 0x93} },
  48         { .data = { 0xE2, 0x65 } },
  49         { .data = { 0xE3, 0xF8 } },
  50
  51         /* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */
  52         { .data = { 0x80, 0x03 } },
  53
  54         /* Sequence control */
  55         { .data = { 0x70, 0x02 } },
  56         { .data = { 0x71, 0x23 } },
  57         { .data = { 0x72, 0x06 } },
  58
  59         /* Switch to page 1 */
  60         { .data = { 0xE0, 0x01 } },
  61
  62         /* Set VCOM */
  63         { .data = { 0x00, 0x00 } },
  64         { .data = { 0x01, 0x66 } },
  65         /* Set VCOM_Reverse */
  66         { .data = { 0x03, 0x00 } },
  67         { .data = { 0x04, 0x25 } },
  68
  69         /* Set Gamma Power, VG[MS][PN] */
  70         { .data = { 0x17, 0x00 } },
  71         { .data = { 0x18, 0x6D } },
  72         { .data = { 0x19, 0x00 } },
  73         { .data = { 0x1A, 0x00 } },
  74         { .data = { 0x1B, 0xBF } }, /* VGMN = -4.5V */
  75         { .data = { 0x1C, 0x00 } },
  76
  77         /* Set Gate Power */
  78         { .data = { 0x1F, 0x3E } }, /* VGH_R = 15V */
  79         { .data = { 0x20, 0x28 } }, /* VGL_R = -11V */
  80         { .data = { 0x21, 0x28 } }, /* VGL_R2 = -11V */
  81         { .data = { 0x22, 0x0E } }, /* PA[6:4] = 0, PA[0] = 0 */
  82
  83         /* Set Panel */
  84         { .data = { 0x37, 0x09 } }, /* SS = 1, BGR = 1 */
  85
  86         /* Set RGBCYC */
  87         { .data = { 0x38, 0x04 } }, /* JDT = 100 column inversion */
  88         { .data = { 0x39, 0x08 } }, /* RGB_N_EQ1 */
  89         { .data = { 0x3A, 0x12 } }, /* RGB_N_EQ2 */
  90         { .data = { 0x3C, 0x78 } }, /* set EQ3 for TE_H */
  91         { .data = { 0x3D, 0xFF } }, /* set CHGEN_ON */
  92         { .data = { 0x3E, 0xFF } }, /* set CHGEN_OFF */
  93         { .data = { 0x3F, 0x7F } }, /* set CHGEN_OFF2 */
  94
  95         /* Set TCON parameter */
  96         { .data = { 0x40, 0x06 } }, /* RSO = 800 points */
  97         { .data = { 0x41, 0xA0 } }, /* LN = 1280 lines */
  98
  99         /* Set power voltage */
 100         { .data = { 0x55, 0x0F } }, /* DCDCM */
 101         { .data = { 0x56, 0x01 } },
 102         { .data = { 0x57, 0x69 } },
 103         { .data = { 0x58, 0x0A } },
 104         { .data = { 0x59, 0x0A } },
 105         { .data = { 0x5A, 0x45 } },
 106         { .data = { 0x5B, 0x15 } },
 107
 108         /* Set gamma */
 109         { .data = { 0x5D, 0x7C } },
 110         { .data = { 0x5E, 0x65 } },
 111         { .data = { 0x5F, 0x55 } },
 112         { .data = { 0x60, 0x49 } },
 113         { .data = { 0x61, 0x44 } },
 114         { .data = { 0x62, 0x35 } },
 115         { .data = { 0x63, 0x3A } },
 116         { .data = { 0x64, 0x23 } },
 117         { .data = { 0x65, 0x3D } },
 118         { .data = { 0x66, 0x3C } },
 119         { .data = { 0x67, 0x3D } },
 120         { .data = { 0x68, 0x5D } },
 121         { .data = { 0x69, 0x4D } },
 122         { .data = { 0x6A, 0x56 } },
 123         { .data = { 0x6B, 0x48 } },
 124         { .data = { 0x6C, 0x45 } },
 125         { .data = { 0x6D, 0x38 } },
 126         { .data = { 0x6E, 0x25 } },
 127         { .data = { 0x6F, 0x00 } },
 128         { .data = { 0x70, 0x7C } },
 129         { .data = { 0x71, 0x65 } },
 130         { .data = { 0x72, 0x55 } },
 131         { .data = { 0x73, 0x49 } },
 132         { .data = { 0x74, 0x44 } },
 133         { .data = { 0x75, 0x35 } },
 134         { .data = { 0x76, 0x3A } },
 135         { .data = { 0x77, 0x23 } },
 136         { .data = { 0x78, 0x3D } },
 137         { .data = { 0x79, 0x3C } },
 138         { .data = { 0x7A, 0x3D } },
 139         { .data = { 0x7B, 0x5D } },
 140         { .data = { 0x7C, 0x4D } },
 141         { .data = { 0x7D, 0x56 } },
 142         { .data = { 0x7E, 0x48 } },
 143         { .data = { 0x7F, 0x45 } },
 144         { .data = { 0x80, 0x38 } },
 145         { .data = { 0x81, 0x25 } },
 146         { .data = { 0x82, 0x00 } },
 147
 148         /* Switch to page 2, for GIP */
 149         { .data = { 0xE0, 0x02 } },
 150
 151         { .data = { 0x00, 0x1E } },
 152         { .data = { 0x01, 0x1E } },
 153         { .data = { 0x02, 0x41 } },
 154         { .data = { 0x03, 0x41 } },
 155         { .data = { 0x04, 0x43 } },
 156         { .data = { 0x05, 0x43 } },
 157         { .data = { 0x06, 0x1F } },
 158         { .data = { 0x07, 0x1F } },
 159         { .data = { 0x08, 0x1F } },
 160         { .data = { 0x09, 0x1F } },
 161         { .data = { 0x0A, 0x1E } },
 162         { .data = { 0x0B, 0x1E } },
 163         { .data = { 0x0C, 0x1F } },
 164         { .data = { 0x0D, 0x47 } },
 165         { .data = { 0x0E, 0x47 } },
 166         { .data = { 0x0F, 0x45 } },
 167         { .data = { 0x10, 0x45 } },
 168         { .data = { 0x11, 0x4B } },
 169         { .data = { 0x12, 0x4B } },
 170         { .data = { 0x13, 0x49 } },
 171         { .data = { 0x14, 0x49 } },
 172         { .data = { 0x15, 0x1F } },
 173
 174         { .data = { 0x16, 0x1E } },
 175         { .data = { 0x17, 0x1E } },
 176         { .data = { 0x18, 0x40 } },
 177         { .data = { 0x19, 0x40 } },
 178         { .data = { 0x1A, 0x42 } },
 179         { .data = { 0x1B, 0x42 } },
 180         { .data = { 0x1C, 0x1F } },
 181         { .data = { 0x1D, 0x1F } },
 182         { .data = { 0x1E, 0x1F } },
 183         { .data = { 0x1F, 0x1f } },
 184         { .data = { 0x20, 0x1E } },
 185         { .data = { 0x21, 0x1E } },
 186         { .data = { 0x22, 0x1f } },
 187         { .data = { 0x23, 0x46 } },
 188         { .data = { 0x24, 0x46 } },
 189         { .data = { 0x25, 0x44 } },
 190         { .data = { 0x26, 0x44 } },
 191         { .data = { 0x27, 0x4A } },
 192         { .data = { 0x28, 0x4A } },
 193         { .data = { 0x29, 0x48 } },
 194         { .data = { 0x2A, 0x48 } },
 195         { .data = { 0x2B, 0x1f } },
 196
 197         { .data = { 0x2C, 0x1F } },
 198         { .data = { 0x2D, 0x1F } },
 199         { .data = { 0x2E, 0x42 } },
 200         { .data = { 0x2F, 0x42 } },
 201         { .data = { 0x30, 0x40 } },
 202         { .data = { 0x31, 0x40 } },
 203         { .data = { 0x32, 0x1E } },
 204         { .data = { 0x33, 0x1E } },
 205         { .data = { 0x34, 0x1F } },
 206         { .data = { 0x35, 0x1F } },
 207         { .data = { 0x36, 0x1E } },
 208         { .data = { 0x37, 0x1E } },
 209         { .data = { 0x38, 0x1F } },
 210         { .data = { 0x39, 0x48 } },
 211         { .data = { 0x3A, 0x48 } },
 212         { .data = { 0x3B, 0x4A } },
 213         { .data = { 0x3C, 0x4A } },
 214         { .data = { 0x3D, 0x44 } },
 215         { .data = { 0x3E, 0x44 } },
 216         { .data = { 0x3F, 0x46 } },
 217         { .data = { 0x40, 0x46 } },
 218         { .data = { 0x41, 0x1F } },
 219
 220         { .data = { 0x42, 0x1F } },
 221         { .data = { 0x43, 0x1F } },
 222         { .data = { 0x44, 0x43 } },
 223         { .data = { 0x45, 0x43 } },
 224         { .data = { 0x46, 0x41 } },
 225         { .data = { 0x47, 0x41 } },
 226         { .data = { 0x48, 0x1E } },
 227         { .data = { 0x49, 0x1E } },
 228         { .data = { 0x4A, 0x1E } },
 229         { .data = { 0x4B, 0x1F } },
 230         { .data = { 0x4C, 0x1E } },
 231         { .data = { 0x4D, 0x1E } },
 232         { .data = { 0x4E, 0x1F } },
 233         { .data = { 0x4F, 0x49 } },
 234         { .data = { 0x50, 0x49 } },
 235         { .data = { 0x51, 0x4B } },
 236         { .data = { 0x52, 0x4B } },
 237         { .data = { 0x53, 0x45 } },
 238         { .data = { 0x54, 0x45 } },
 239         { .data = { 0x55, 0x47 } },
 240         { .data = { 0x56, 0x47 } },
 241         { .data = { 0x57, 0x1F } },
 242
 243         { .data = { 0x58, 0x10 } },
 244         { .data = { 0x59, 0x00 } },
 245         { .data = { 0x5A, 0x00 } },
 246         { .data = { 0x5B, 0x30 } },
 247         { .data = { 0x5C, 0x02 } },
 248         { .data = { 0x5D, 0x40 } },
 249         { .data = { 0x5E, 0x01 } },
 250         { .data = { 0x5F, 0x02 } },
 251         { .data = { 0x60, 0x30 } },
 252         { .data = { 0x61, 0x01 } },
 253         { .data = { 0x62, 0x02 } },
 254         { .data = { 0x63, 0x6A } },
 255         { .data = { 0x64, 0x6A } },
 256         { .data = { 0x65, 0x05 } },
 257         { .data = { 0x66, 0x12 } },
 258         { .data = { 0x67, 0x74 } },
 259         { .data = { 0x68, 0x04 } },
 260         { .data = { 0x69, 0x6A } },
 261         { .data = { 0x6A, 0x6A } },
 262         { .data = { 0x6B, 0x08 } },
 263
 264         { .data = { 0x6C, 0x00 } },
 265         { .data = { 0x6D, 0x04 } },
 266         { .data = { 0x6E, 0x04 } },
 267         { .data = { 0x6F, 0x88 } },
 268         { .data = { 0x70, 0x00 } },
 269         { .data = { 0x71, 0x00 } },
 270         { .data = { 0x72, 0x06 } },
 271         { .data = { 0x73, 0x7B } },
 272         { .data = { 0x74, 0x00 } },
 273         { .data = { 0x75, 0x07 } },
 274         { .data = { 0x76, 0x00 } },
 275         { .data = { 0x77, 0x5D } },
 276         { .data = { 0x78, 0x17 } },
 277         { .data = { 0x79, 0x1F } },
 278         { .data = { 0x7A, 0x00 } },
 279         { .data = { 0x7B, 0x00 } },
 280         { .data = { 0x7C, 0x00 } },
 281         { .data = { 0x7D, 0x03 } },
 282         { .data = { 0x7E, 0x7B } },
 283
 284         { .data = { 0xE0, 0x04 } },
 285         { .data = { 0x2B, 0x2B } },
 286         { .data = { 0x2E, 0x44 } },
 287
 288         { .data = { 0xE0, 0x01 } },
 289         { .data = { 0x0E, 0x01 } },
 290
 291         { .data = { 0xE0, 0x03 } },
 292         { .data = { 0x98, 0x2F } },
 293
 294         { .data = { 0xE0, 0x00 } },
 295         { .data = { 0xE6, 0x02 } },
 296         { .data = { 0xE7, 0x02 } },
 297
 298         { .data = { 0x11, 0x00 } },
 299 };
 300
 301 static const struct k101_im2ba02_init_cmd timed_cmds[] = {
 302         { .data = { 0x29, 0x00 } },
 303         { .data = { 0x35, 0x00 } },
 304 };
 305
 306 static int k101_im2ba02_prepare(struct drm_panel *panel)
 307 {
 308         struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
 309         struct mipi_dsi_device *dsi = ctx->dsi;
 310         unsigned int i;
 311         int ret;
 312
 313         ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 314         if (ret)
 315                 return ret;
 316
 317         msleep(30);
 318
 319         gpiod_set_value(ctx->reset, 1);
 320         msleep(50);
 321
 322         gpiod_set_value(ctx->reset, 0);
 323         msleep(50);
 324
 325         gpiod_set_value(ctx->reset, 1);
 326         msleep(200);
 327
 328         for (i = 0; i < ARRAY_SIZE(k101_im2ba02_init_cmds); i++) {
 329                 const struct k101_im2ba02_init_cmd *cmd = &k101_im2ba02_init_cmds[i];
 330
 331                 ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN);
 332                 if (ret < 0)
 333                         goto powerdown;
 334         }
 335
 336         return 0;
 337
 338 powerdown:
 339         gpiod_set_value(ctx->reset, 0);
 340         msleep(50);
 341
 342         return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 343 }
 344
 345 static int k101_im2ba02_enable(struct drm_panel *panel)
 346 {
 347         struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
 348         const struct k101_im2ba02_init_cmd *cmd = &timed_cmds[1];
 349         int ret;
 350
 351         msleep(150);
 352
 353         ret = mipi_dsi_dcs_set_display_on(ctx->dsi);
 354         if (ret < 0)
 355                 return ret;
 356
 357         msleep(50);
 358
 359         return mipi_dsi_dcs_write_buffer(ctx->dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN);
 360 }
 361
 362 static int k101_im2ba02_disable(struct drm_panel *panel)
 363 {
 364         struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
 365
 366         return mipi_dsi_dcs_set_display_off(ctx->dsi);
 367 }
 368
 369 static int k101_im2ba02_unprepare(struct drm_panel *panel)
 370 {
 371         struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
 372         int ret;
 373
 374         ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
 375         if (ret < 0)
 376                 dev_err(panel->dev, "failed to set display off: %d\n", ret);
 377
 378         ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
 379         if (ret < 0)
 380                 dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
 381
 382         msleep(200);
 383
 384         gpiod_set_value(ctx->reset, 0);
 385         msleep(20);
 386
 387         return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 388 }
 389
 390 static const struct drm_display_mode k101_im2ba02_default_mode = {
 391         .clock = 70000,
 392
 393         .hdisplay = 800,
 394         .hsync_start = 800 + 20,
 395         .hsync_end = 800 + 20 + 20,
 396         .htotal = 800 + 20 + 20 + 20,
 397
 398         .vdisplay = 1280,
 399         .vsync_start = 1280 + 16,
 400         .vsync_end = 1280 + 16 + 4,
 401         .vtotal = 1280 + 16 + 4 + 4,
 402
 403         .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 404         .width_mm       = 136,
 405         .height_mm      = 217,
 406 };
 407
 408 static int k101_im2ba02_get_modes(struct drm_panel *panel,
 409                                   struct drm_connector *connector)
 410 {
 411         struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
 412         struct drm_display_mode *mode;
 413
 414         mode = drm_mode_duplicate(connector->dev, &k101_im2ba02_default_mode);
 415         if (!mode) {
 416                 dev_err(&ctx->dsi->dev, "failed to add mode %ux%u@%u\n",
 417                         k101_im2ba02_default_mode.hdisplay,
 418                         k101_im2ba02_default_mode.vdisplay,
 419                         drm_mode_vrefresh(&k101_im2ba02_default_mode));
 420                 return -ENOMEM;
 421         }
 422
 423         drm_mode_set_name(mode);
 424
 425         mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 426         connector->display_info.width_mm = mode->width_mm;
 427         connector->display_info.height_mm = mode->height_mm;
 428         drm_mode_probed_add(connector, mode);
 429
 430         return 1;
 431 }
 432
 433 static const struct drm_panel_funcs k101_im2ba02_funcs = {
 434         .disable = k101_im2ba02_disable,
 435         .unprepare = k101_im2ba02_unprepare,
 436         .prepare = k101_im2ba02_prepare,
 437         .enable = k101_im2ba02_enable,
 438         .get_modes = k101_im2ba02_get_modes,
 439 };
 440
 441 static int k101_im2ba02_dsi_probe(struct mipi_dsi_device *dsi)
 442 {
 443         struct k101_im2ba02 *ctx;
 444         unsigned int i;
 445         int ret;
 446
 447         ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
 448         if (!ctx)
 449                 return -ENOMEM;
 450
 451         mipi_dsi_set_drvdata(dsi, ctx);
 452         ctx->dsi = dsi;
 453
 454         for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++)
 455                 ctx->supplies[i].supply = regulator_names[i];
 456
 457         ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(ctx->supplies),
 458                                       ctx->supplies);
 459         if (ret < 0) {
 460                 dev_err(&dsi->dev, "Couldn't get regulators\n");
 461                 return ret;
 462         }
 463
 464         ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
 465         if (IS_ERR(ctx->reset)) {
 466                 dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
 467                 return PTR_ERR(ctx->reset);
 468         }
 469
 470         drm_panel_init(&ctx->panel, &dsi->dev, &k101_im2ba02_funcs,
 471                        DRM_MODE_CONNECTOR_DSI);
 472
 473         ret = drm_panel_of_backlight(&ctx->panel);
 474         if (ret)
 475                 return ret;
 476
 477         drm_panel_add(&ctx->panel);
 478
 479         dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
 480         dsi->format = MIPI_DSI_FMT_RGB888;
 481         dsi->lanes = 4;
 482
 483         ret = mipi_dsi_attach(dsi);
 484         if (ret < 0) {
 485                 drm_panel_remove(&ctx->panel);
 486                 return ret;
 487         }
 488
 489         return 0;
 490 }
 491
 492 static int k101_im2ba02_dsi_remove(struct mipi_dsi_device *dsi)
 493 {
 494         struct k101_im2ba02 *ctx = mipi_dsi_get_drvdata(dsi);
 495
 496         mipi_dsi_detach(dsi);
 497         drm_panel_remove(&ctx->panel);
 498
 499         return 0;
 500 }
 501
 502 static const struct of_device_id k101_im2ba02_of_match[] = {
 503         { .compatible = "feixin,k101-im2ba02", },
 504         { /* sentinel */ }
 505 };
 506 MODULE_DEVICE_TABLE(of, k101_im2ba02_of_match);
 507
 508 static struct mipi_dsi_driver k101_im2ba02_driver = {
 509         .probe = k101_im2ba02_dsi_probe,
 510         .remove = k101_im2ba02_dsi_remove,
 511         .driver = {
 512                 .name = "feixin-k101-im2ba02",
 513                 .of_match_table = k101_im2ba02_of_match,
 514         },
 515 };
 516 module_mipi_dsi_driver(k101_im2ba02_driver);
 517
 518 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
 519 MODULE_DESCRIPTION("Feixin K101 IM2BA02 MIPI-DSI LCD panel");
 520 MODULE_LICENSE("GPL");