drivers/gpu/drm/r128/ati_pcigart.c

   1 /*
   2  * \file ati_pcigart.c
   3  * ATI PCI GART support
   4  *
   5  * \author Gareth Hughes <gareth@valinux.com>
   6  */
   7
   8 /*
   9  * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
  10  *
  11  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  12  * All Rights Reserved.
  13  *
  14  * Permission is hereby granted, free of charge, to any person obtaining a
  15  * copy of this software and associated documentation files (the "Software"),
  16  * to deal in the Software without restriction, including without limitation
  17  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  18  * and/or sell copies of the Software, and to permit persons to whom the
  19  * Software is furnished to do so, subject to the following conditions:
  20  *
  21  * The above copyright notice and this permission notice (including the next
  22  * paragraph) shall be included in all copies or substantial portions of the
  23  * Software.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  26  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  27  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  28  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  29  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  30  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  31  * DEALINGS IN THE SOFTWARE.
  32  */
  33
  34 #include <linux/export.h>
  35 #include <linux/pci.h>
  36
  37 #include <drm/drm_device.h>
  38 #include <drm/drm_legacy.h>
  39 #include <drm/drm_print.h>
  40
  41 #include "ati_pcigart.h"
  42
  43 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  44
  45 static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
  46                                        struct drm_ati_pcigart_info *gart_info)
  47 {
  48         gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
  49                                                 PAGE_SIZE);
  50         if (gart_info->table_handle == NULL)
  51                 return -ENOMEM;
  52
  53         return 0;
  54 }
  55
  56 static void drm_ati_free_pcigart_table(struct drm_device *dev,
  57                                        struct drm_ati_pcigart_info *gart_info)
  58 {
  59         drm_pci_free(dev, gart_info->table_handle);
  60         gart_info->table_handle = NULL;
  61 }
  62
  63 int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
  64 {
  65         struct drm_sg_mem *entry = dev->sg;
  66         unsigned long pages;
  67         int i;
  68         int max_pages;
  69
  70         /* we need to support large memory configurations */
  71         if (!entry) {
  72                 DRM_ERROR("no scatter/gather memory!\n");
  73                 return 0;
  74         }
  75
  76         if (gart_info->bus_addr) {
  77
  78                 max_pages = (gart_info->table_size / sizeof(u32));
  79                 pages = (entry->pages <= max_pages)
  80                   ? entry->pages : max_pages;
  81
  82                 for (i = 0; i < pages; i++) {
  83                         if (!entry->busaddr[i])
  84                                 break;
  85                         pci_unmap_page(dev->pdev, entry->busaddr[i],
  86                                          PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  87                 }
  88
  89                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
  90                         gart_info->bus_addr = 0;
  91         }
  92
  93         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
  94             gart_info->table_handle) {
  95                 drm_ati_free_pcigart_table(dev, gart_info);
  96         }
  97
  98         return 1;
  99 }
 100
 101 int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 102 {
 103         struct drm_local_map *map = &gart_info->mapping;
 104         struct drm_sg_mem *entry = dev->sg;
 105         void *address = NULL;
 106         unsigned long pages;
 107         u32 *pci_gart = NULL, page_base, gart_idx;
 108         dma_addr_t bus_address = 0;
 109         int i, j, ret = -ENOMEM;
 110         int max_ati_pages, max_real_pages;
 111
 112         if (!entry) {
 113                 DRM_ERROR("no scatter/gather memory!\n");
 114                 goto done;
 115         }
 116
 117         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
 118                 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
 119
 120                 if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) {
 121                         DRM_ERROR("fail to set dma mask to 0x%Lx\n",
 122                                   (unsigned long long)gart_info->table_mask);
 123                         ret = -EFAULT;
 124                         goto done;
 125                 }
 126
 127                 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
 128                 if (ret) {
 129                         DRM_ERROR("cannot allocate PCI GART page!\n");
 130                         goto done;
 131                 }
 132
 133                 pci_gart = gart_info->table_handle->vaddr;
 134                 address = gart_info->table_handle->vaddr;
 135                 bus_address = gart_info->table_handle->busaddr;
 136         } else {
 137                 address = gart_info->addr;
 138                 bus_address = gart_info->bus_addr;
 139                 DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
 140                           (unsigned long long)bus_address,
 141                           (unsigned long)address);
 142         }
 143
 144
 145         max_ati_pages = (gart_info->table_size / sizeof(u32));
 146         max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
 147         pages = (entry->pages <= max_real_pages)
 148             ? entry->pages : max_real_pages;
 149
 150         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
 151                 memset(pci_gart, 0, max_ati_pages * sizeof(u32));
 152         } else {
 153                 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u32));
 154         }
 155
 156         gart_idx = 0;
 157         for (i = 0; i < pages; i++) {
 158                 /* we need to support large memory configurations */
 159                 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
 160                                                  0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 161                 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
 162                         DRM_ERROR("unable to map PCIGART pages!\n");
 163                         drm_ati_pcigart_cleanup(dev, gart_info);
 164                         address = NULL;
 165                         bus_address = 0;
 166                         ret = -ENOMEM;
 167                         goto done;
 168                 }
 169                 page_base = (u32) entry->busaddr[i];
 170
 171                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 172                         u32 offset;
 173                         u32 val;
 174
 175                         switch(gart_info->gart_reg_if) {
 176                         case DRM_ATI_GART_IGP:
 177                                 val = page_base | 0xc;
 178                                 break;
 179                         case DRM_ATI_GART_PCIE:
 180                                 val = (page_base >> 8) | 0xc;
 181                                 break;
 182                         default:
 183                         case DRM_ATI_GART_PCI:
 184                                 val = page_base;
 185                                 break;
 186                         }
 187                         if (gart_info->gart_table_location ==
 188                             DRM_ATI_GART_MAIN) {
 189                                 pci_gart[gart_idx] = cpu_to_le32(val);
 190                         } else {
 191                                 offset = gart_idx * sizeof(u32);
 192                                 writel(val, (void __iomem *)map->handle + offset);
 193                         }
 194                         gart_idx++;
 195                         page_base += ATI_PCIGART_PAGE_SIZE;
 196                 }
 197         }
 198         ret = 0;
 199
 200 #if defined(__i386__) || defined(__x86_64__)
 201         wbinvd();
 202 #else
 203         mb();
 204 #endif
 205
 206       done:
 207         gart_info->addr = address;
 208         gart_info->bus_addr = bus_address;
 209         return ret;
 210 }