| blob | 318377df09ef43f6cdf0bccae48e2521cddc761e |
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #ifndef __CIK_REG_H__
25 #define __CIK_REG_H__
27 #define CIK_DIDT_IND_INDEX 0xca00
28 #define CIK_DIDT_IND_DATA 0xca04
30 #define CIK_DC_GPIO_HPD_MASK 0x65b0
31 #define CIK_DC_GPIO_HPD_A 0x65b4
32 #define CIK_DC_GPIO_HPD_EN 0x65b8
33 #define CIK_DC_GPIO_HPD_Y 0x65bc
35 #define CIK_GRPH_CONTROL 0x6804
36 # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0)
37 # define CIK_GRPH_DEPTH_8BPP 0
38 # define CIK_GRPH_DEPTH_16BPP 1
39 # define CIK_GRPH_DEPTH_32BPP 2
40 # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
41 # define CIK_ADDR_SURF_2_BANK 0
42 # define CIK_ADDR_SURF_4_BANK 1
43 # define CIK_ADDR_SURF_8_BANK 2
44 # define CIK_ADDR_SURF_16_BANK 3
45 # define CIK_GRPH_Z(x) (((x) & 0x3) << 4)
46 # define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
47 # define CIK_ADDR_SURF_BANK_WIDTH_1 0
48 # define CIK_ADDR_SURF_BANK_WIDTH_2 1
49 # define CIK_ADDR_SURF_BANK_WIDTH_4 2
50 # define CIK_ADDR_SURF_BANK_WIDTH_8 3
51 # define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8)
52 /* 8 BPP */
53 # define CIK_GRPH_FORMAT_INDEXED 0
54 /* 16 BPP */
55 # define CIK_GRPH_FORMAT_ARGB1555 0
56 # define CIK_GRPH_FORMAT_ARGB565 1
57 # define CIK_GRPH_FORMAT_ARGB4444 2
58 # define CIK_GRPH_FORMAT_AI88 3
59 # define CIK_GRPH_FORMAT_MONO16 4
60 # define CIK_GRPH_FORMAT_BGRA5551 5
61 /* 32 BPP */
62 # define CIK_GRPH_FORMAT_ARGB8888 0
63 # define CIK_GRPH_FORMAT_ARGB2101010 1
64 # define CIK_GRPH_FORMAT_32BPP_DIG 2
65 # define CIK_GRPH_FORMAT_8B_ARGB2101010 3
66 # define CIK_GRPH_FORMAT_BGRA1010102 4
67 # define CIK_GRPH_FORMAT_8B_BGRA1010102 5
68 # define CIK_GRPH_FORMAT_RGB111110 6
69 # define CIK_GRPH_FORMAT_BGR101111 7
70 # define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
71 # define CIK_ADDR_SURF_BANK_HEIGHT_1 0
72 # define CIK_ADDR_SURF_BANK_HEIGHT_2 1
73 # define CIK_ADDR_SURF_BANK_HEIGHT_4 2
74 # define CIK_ADDR_SURF_BANK_HEIGHT_8 3
75 # define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
76 # define CIK_ADDR_SURF_TILE_SPLIT_64B 0
77 # define CIK_ADDR_SURF_TILE_SPLIT_128B 1
78 # define CIK_ADDR_SURF_TILE_SPLIT_256B 2
79 # define CIK_ADDR_SURF_TILE_SPLIT_512B 3
80 # define CIK_ADDR_SURF_TILE_SPLIT_1KB 4
81 # define CIK_ADDR_SURF_TILE_SPLIT_2KB 5
82 # define CIK_ADDR_SURF_TILE_SPLIT_4KB 6
83 # define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
84 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 0
85 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_2 1
86 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_4 2
87 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_8 3
88 # define CIK_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
89 # define CIK_GRPH_ARRAY_LINEAR_GENERAL 0
90 # define CIK_GRPH_ARRAY_LINEAR_ALIGNED 1
91 # define CIK_GRPH_ARRAY_1D_TILED_THIN1 2
92 # define CIK_GRPH_ARRAY_2D_TILED_THIN1 4
93 # define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
94 # define CIK_ADDR_SURF_P2 0
95 # define CIK_ADDR_SURF_P4_8x16 4
96 # define CIK_ADDR_SURF_P4_16x16 5
97 # define CIK_ADDR_SURF_P4_16x32 6
98 # define CIK_ADDR_SURF_P4_32x32 7
99 # define CIK_ADDR_SURF_P8_16x16_8x16 8
100 # define CIK_ADDR_SURF_P8_16x32_8x16 9
101 # define CIK_ADDR_SURF_P8_32x32_8x16 10
102 # define CIK_ADDR_SURF_P8_16x32_16x16 11
103 # define CIK_ADDR_SURF_P8_32x32_16x16 12
104 # define CIK_ADDR_SURF_P8_32x32_16x32 13
105 # define CIK_ADDR_SURF_P8_32x64_32x32 14
106 # define CIK_GRPH_MICRO_TILE_MODE(x) (((x) & 0x7) << 29)
107 # define CIK_DISPLAY_MICRO_TILING 0
108 # define CIK_THIN_MICRO_TILING 1
109 # define CIK_DEPTH_MICRO_TILING 2
110 # define CIK_ROTATED_MICRO_TILING 4
112 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
113 #define CIK_CUR_CONTROL 0x6998
114 # define CIK_CURSOR_EN (1 << 0)
115 # define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8)
116 # define CIK_CURSOR_MONO 0
117 # define CIK_CURSOR_24_1 1
118 # define CIK_CURSOR_24_8_PRE_MULT 2
119 # define CIK_CURSOR_24_8_UNPRE_MULT 3
120 # define CIK_CURSOR_2X_MAGNIFY (1 << 16)
121 # define CIK_CURSOR_FORCE_MC_ON (1 << 20)
122 # define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
123 # define CIK_CURSOR_URGENT_ALWAYS 0
124 # define CIK_CURSOR_URGENT_1_8 1
125 # define CIK_CURSOR_URGENT_1_4 2
126 # define CIK_CURSOR_URGENT_3_8 3
127 # define CIK_CURSOR_URGENT_1_2 4
128 #define CIK_CUR_SURFACE_ADDRESS 0x699c
129 # define CIK_CUR_SURFACE_ADDRESS_MASK 0xfffff000
130 #define CIK_CUR_SIZE 0x69a0
131 #define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4
132 #define CIK_CUR_POSITION 0x69a8
133 #define CIK_CUR_HOT_SPOT 0x69ac
134 #define CIK_CUR_COLOR1 0x69b0
135 #define CIK_CUR_COLOR2 0x69b4
136 #define CIK_CUR_UPDATE 0x69b8
137 # define CIK_CURSOR_UPDATE_PENDING (1 << 0)
138 # define CIK_CURSOR_UPDATE_TAKEN (1 << 1)
139 # define CIK_CURSOR_UPDATE_LOCK (1 << 16)
140 # define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
142 #define CIK_ALPHA_CONTROL 0x6af0
143 # define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1)
145 #define CIK_LB_DATA_FORMAT 0x6b00
146 # define CIK_INTERLEAVE_EN (1 << 3)
148 #define CIK_LB_DESKTOP_HEIGHT 0x6b0c
150 #define SQ_IND_INDEX 0x8DE0
151 #define SQ_CMD 0x8DEC
152 #define SQ_IND_DATA 0x8DE4
154 /*
155 * The TCP_WATCHx_xxxx addresses that are shown here are in dwords,
156 * and that's why they are multiplied by 4
157 */
158 #define TCP_WATCH0_ADDR_H (0x32A0*4)
159 #define TCP_WATCH1_ADDR_H (0x32A3*4)
160 #define TCP_WATCH2_ADDR_H (0x32A6*4)
161 #define TCP_WATCH3_ADDR_H (0x32A9*4)
162 #define TCP_WATCH0_ADDR_L (0x32A1*4)
163 #define TCP_WATCH1_ADDR_L (0x32A4*4)
164 #define TCP_WATCH2_ADDR_L (0x32A7*4)
165 #define TCP_WATCH3_ADDR_L (0x32AA*4)
166 #define TCP_WATCH0_CNTL (0x32A2*4)
167 #define TCP_WATCH1_CNTL (0x32A5*4)
168 #define TCP_WATCH2_CNTL (0x32A8*4)
169 #define TCP_WATCH3_CNTL (0x32AB*4)
171 #define CPC_INT_CNTL 0xC2D0
173 #define CP_HQD_IQ_RPTR 0xC970u
174 #define SDMA0_RLC0_RB_CNTL 0xD400u
175 #define SDMA_RB_VMID(x) (x << 24)
176 #define SDMA0_RLC0_RB_BASE 0xD404u
177 #define SDMA0_RLC0_RB_BASE_HI 0xD408u
178 #define SDMA0_RLC0_RB_RPTR 0xD40Cu
179 #define SDMA0_RLC0_RB_WPTR 0xD410u
180 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL 0xD414u
181 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0xD418u
182 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0xD41Cu
183 #define SDMA0_RLC0_RB_RPTR_ADDR_HI 0xD420u
184 #define SDMA0_RLC0_RB_RPTR_ADDR_LO 0xD424u
185 #define SDMA0_RLC0_IB_CNTL 0xD428u
186 #define SDMA0_RLC0_IB_RPTR 0xD42Cu
187 #define SDMA0_RLC0_IB_OFFSET 0xD430u
188 #define SDMA0_RLC0_IB_BASE_LO 0xD434u
189 #define SDMA0_RLC0_IB_BASE_HI 0xD438u
190 #define SDMA0_RLC0_IB_SIZE 0xD43Cu
191 #define SDMA0_RLC0_SKIP_CNTL 0xD440u
192 #define SDMA0_RLC0_CONTEXT_STATUS 0xD444u
193 #define SDMA_RLC_IDLE (1 << 2)
194 #define SDMA0_RLC0_DOORBELL 0xD448u
195 #define SDMA_OFFSET(x) (x << 0)
196 #define SDMA_DB_ENABLE (1 << 28)
197 #define SDMA0_RLC0_VIRTUAL_ADDR 0xD49Cu
198 #define SDMA_ATC (1 << 0)
199 #define SDMA_VA_PTR32 (1 << 4)
200 #define SDMA_VA_SHARED_BASE(x) (x << 8)
201 #define SDMA0_RLC0_APE1_CNTL 0xD4A0u
202 #define SDMA0_RLC0_DOORBELL_LOG 0xD4A4u
203 #define SDMA0_RLC0_WATERMARK 0xD4A8u
204 #define SDMA0_CNTL 0xD010
205 #define SDMA1_CNTL 0xD810
210 };
214 ADDRESS_WATCH_REG_ADDR_LO,
215 ADDRESS_WATCH_REG_CNTL,
216 ADDRESS_WATCH_REG_MAX
217 };
223 /* extend the mask to 26 bits in order to match the low address field */
226 };
239 };
241 #endif