1 /* SPDX-License-Identifier: MIT */
5 #define R100_TRACK_MAX_TEXTURE 3
6 #define R200_TRACK_MAX_TEXTURE 6
7 #define R300_TRACK_MAX_TEXTURE 16
15 struct r100_cs_track_cb
{
16 struct radeon_bo
*robj
;
22 struct r100_cs_track_array
{
23 struct radeon_bo
*robj
;
27 struct r100_cs_cube_info
{
28 struct radeon_bo
*robj
;
34 #define R100_TRACK_COMP_NONE 0
35 #define R100_TRACK_COMP_DXT1 1
36 #define R100_TRACK_COMP_DXT35 2
38 struct r100_cs_track_texture
{
39 struct radeon_bo
*robj
;
40 struct r100_cs_cube_info cube_info
[5]; /* info for 5 non-primary faces */
46 unsigned tex_coord_type
;
55 unsigned compress_format
;
58 struct r100_cs_track
{
64 unsigned vap_alt_nverts
;
68 unsigned color_channel_mask
;
69 struct r100_cs_track_array arrays
[16];
70 struct r100_cs_track_cb cb
[R300_MAX_CB
];
71 struct r100_cs_track_cb zb
;
72 struct r100_cs_track_cb aa
;
73 struct r100_cs_track_texture textures
[R300_TRACK_MAX_TEXTURE
];
77 bool blend_read_enable
;
85 int r100_cs_track_check(struct radeon_device
*rdev
, struct r100_cs_track
*track
);
86 void r100_cs_track_clear(struct radeon_device
*rdev
, struct r100_cs_track
*track
);
88 int r100_cs_packet_parse_vline(struct radeon_cs_parser
*p
);
90 int r200_packet0_check(struct radeon_cs_parser
*p
,
91 struct radeon_cs_packet
*pkt
,
92 unsigned idx
, unsigned reg
);
94 int r100_reloc_pitch_offset(struct radeon_cs_parser
*p
,
95 struct radeon_cs_packet
*pkt
,
98 int r100_packet3_load_vbpntr(struct radeon_cs_parser
*p
,
99 struct radeon_cs_packet
*pkt
,